PIC32MX330/350/370/430/450/470 PIC32MX330/350/370/430/450/470 Family Silicon Errata and Data Sheet Clarification The PIC32MX330/350/370/430/450/470 family of devices that you have received conform functionally to the current Device Data Sheet (DS60001185G), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1 through Table 4. The silicon issues are summarized in Table 5. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: For example, to identify the silicon revision level using MPLAB X IDE in conjunction with a hardware debugger: 1. The errata described in this document will be addressed in future revisions of the PIC32MX330/350/370/430/450/ 470 family silicon. Note: 2. 3. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 5 apply to the current silicon revision (A1). 4. 5. Data Sheet clarifications and corrections (if applicable) start on page 14, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) X IDE and Microchip's programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Note: Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB X IDE project. Configure the MPLAB X IDE project for the appropriate device and hardware debugger. Select Window > Dashboard, and then click the Refresh Debug Tool Status icon ( ). The part number and the Device and Revision ID values appear in the Output window. If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The Device and Revision ID values for the various PIC32MX330/350/370/430/450/470 silicon revisions are shown in Table 1 and Table 4. SILICON DEVREV VALUES FOR DEVICES WITH 64 KB FLASH MEMORY Part Number Flash Memory Size (KB) Device ID(1) Revision ID for Silicon Revision(1) A0 A1 PIC32MX330F064H 64 0x05600053 PIC32MX330F064L 64 0x05601053 0x0 0x1 PIC32MX430F064H 64 0x05602053 PIC32MX430F064L 64 0x05603053 Note 1: Refer to the "Memory Organization" and "Special Features" chapters in the current Device Data Sheet (DS60001185G) for detailed information on Device and Revision IDs for your specific device. 2013-2018 Microchip Technology Inc. DS80000574G-page 1 PIC32MX330/350/370/430/450/470 TABLE 2: SILICON DEVREV VALUES FOR DEVICES WITH 128 KB FLASH MEMORY Part Number Flash Memory Size (KB) Device ID(1) Revision ID for Silicon Revision(1) A0 A1 B0 PIC32MX350F128H 128 0x0570C053 PIC32MX350F128L 128 0x0570D053 0x0 0x1 0x8 PIC32MX450F128H 128 0x0570E053 PIC32MX450F128L 128 0x0570F053 Note 1: Refer to the "Memory Organization" and "Special Features" chapters in the current Device Data Sheet (DS60001185G) for detailed information on Device and Revision IDs for your specific device. TABLE 3: SILICON DEVREV VALUES FOR DEVICES WITH 256 KB FLASH MEMORY Part Number Flash Memory Size (KB) Device ID(1) Revision ID for Silicon Revision(1) A0 A1 B1 PIC32MX350F256H 256 0x05704053 PIC32MX350F256L 256 0x05705053 0x0 0x1 0xA PIC32MX450F256H 256 0x05706053 PIC32MX450F256L 256 0x05707053 Note 1: Refer to the "Memory Organization" and "Special Features" chapters in the current Device Data Sheet (DS60001185G) for detailed information on Device and Revision IDs for your specific device. TABLE 4: SILICON DEVREV VALUES FOR DEVICES WITH 512 KB FLASH MEMORY Part Number Device ID(1) Revision ID for Silicon Revision(1) A0 PIC32MX370F512H 0x05808053 PIC32MX370F512L 0x05809053 0x0 PIC32MX470F512H 0x0580A053 PIC32MX470F512L 0x0580B053 Note 1: Refer to the "Memory Organization" and "Special Features" chapters in the current Device Data Sheet (DS60001185G) for detailed information on Device and Revision IDs for your specific device. 2013-2018 Microchip Technology Inc. DS80000574G-page 2 PIC32MX330/350/370/430/450/470 TABLE 5: SILICON ISSUE SUMMARY Affected Revisions Module Feature Differential Nonlinearity ADC Clock Clock Out Reserved -- I/O I/O 5V Tolerant I/O Pins Non-5V Tolerant I/O Pins Pull-ups Pull-ups Item # 1. 2. Issue Summary The ADC module is not within the published data sheet specification when operating at a conversion rate above 500 ksps. A clock signal is present on the CLKO pin, regardless of the clock source and setting of the CLKO Enable Configuration bit, during a Power-on Reset (POR) condition. 3. 4. 5. 6. -- Port pin RF6 is not 5V tolerant. Use RF6 as a non-5V tolerant pin only. Internal pull-up resistors may not guarantee a logical `1' on digital inputs on 5V tolerant pins. Internal pull-up resistors may not guarantee a logical `1' on digital inputs on non-5V tolerant pins. Flash Memory A0 A1 B0 B1 (KB) 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- -- -- -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X -- -- 128 X 256 X 512 2 I2C JTAG Legend: Slave Mode Boundary Scan 7. 8. When the I C slave receives any of the reserve address with STRICT = 1, an ACK will be generated, but an interrupt will not be generated. -- -- -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- Boundary Scan is not supported. An `X' indicates the issue is present in this revision of the silicon. Shaded cells with an Em dash (`--') indicate that this silicon revision does not exist for this issue. Blank cells indicate an issue has been corrected or does not exist in this revision of the silicon. 2013-2018 Microchip Technology Inc. DS80000574G-page 3 PIC32MX330/350/370/430/450/470 TABLE 5: SILICON ISSUE SUMMARY (CONTINUED) Affected Revisions Module Watchdog Timer Feature Windowed Watchdog Item # 9. Issue Summary Clearing the Watchdog Timer inside the window when in Window mode may cause a reset. Flash Memory A0 A1 B0 B1 (KB) 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- -- -- 64 Debug Debug Pins 10. 128 X X X -- 256 X X -- X -- -- -- On-chip debug pins require special consideration. 512 USB I/O Port Idle Interrupt Open Drain 11. 12. USB Idle interrupts cease if the IDLEIF flag is cleared and the bus is left idle for more than 3 ms. The Open Drain selection (ODCx) on I/O port pins is not available when the pin is configured for anything other than a standard port output. 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- -- -- 64 Flash Memory Timer1 UART Legend: Flash Memory Interrupts Auto-baud 13. 14. 15. The Program Write Protection (PWP) bits are not able to protect all 512 KB of Flash memory on PIC32MX370/470 devices. Under specific conditions, Timer1 will not generate interrupts. The Automatic Baud Rate feature does not function to set the baud rate. -- 128 -- 256 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- An `X' indicates the issue is present in this revision of the silicon. Shaded cells with an Em dash (`--') indicate that this silicon revision does not exist for this issue. Blank cells indicate an issue has been corrected or does not exist in this revision of the silicon. 2013-2018 Microchip Technology Inc. DS80000574G-page 4 PIC32MX330/350/370/430/450/470 TABLE 5: SILICON ISSUE SUMMARY (CONTINUED) Affected Revisions Module UART CTMU ADC HVD PowerSaving Modes Flash Memory Flash Memory Legend: Feature Synchronization Module Operation IVREF Sensing HVDR Idle Write Protection Write Protection Item # 16. 17. 18. 19. 20. 21. 22. Issue Summary On a RX FIFO overflow, shift registers stop receiving data, which causes the UART to lose synchronization. Flash Memory A0 A1 B0 B1 (KB) 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- The CTMU module is not functional Testing the IVREF setting with the ADC module does not function as intended. On power-up, the High-Voltage Detect Reset event flag, RCON<HVDR> is being set. On exit from Sleep mode, the SLEEP and IDLE status bits in the RCON register are being set. When enabled, the Boot Write Protect (BWP) bit also protects and overlaps the first page of user program space below 0x1000 in addition to the boot segment The Program Write Protection (PWP) bit field is off by one page relative to the definition in the data sheet. An `X' indicates the issue is present in this revision of the silicon. Shaded cells with an Em dash (`--') indicate that this silicon revision does not exist for this issue. Blank cells indicate an issue has been corrected or does not exist in this revision of the silicon. 2013-2018 Microchip Technology Inc. DS80000574G-page 5 PIC32MX330/350/370/430/450/470 TABLE 5: SILICON ISSUE SUMMARY (CONTINUED) Affected Revisions Module Flash Memory I/O Pins Legend: Feature Write Protection Peripheral Pin Select (PPS) Item # 23. 24. Issue Summary The Program Write Protection (PWP) bits are not enabled unless the Boot Write Protect (BWP) bit is also enabled. The RPF3 pin is not available for PPS functions on USB devices. Flash Memory A0 A1 B0 B1 (KB) 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- 64 X X -- -- 128 X X X -- 256 X X -- X 512 X -- -- -- An `X' indicates the issue is present in this revision of the silicon. Shaded cells with an Em dash (`--') indicate that this silicon revision does not exist for this issue. Blank cells indicate an issue has been corrected or does not exist in this revision of the silicon. 2013-2018 Microchip Technology Inc. DS80000574G-page 6 PIC32MX330/350/370/430/450/470 Silicon Errata Issues Note 1: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. The table provided in each issue indicates which issues exist for a particular revision of silicon based on Flash memory size. 2: The following applies to the Affected Silicon Revision tables in each silicon issue: * An `X' indicates the issue is present in this revision of silicon * Shaded cells with an Em dash (`--') indicate that this silicon revision does not exist for this issue * Blank cells indicate an issue has been corrected or does not exist in this revision of silicon. 1. Module: ADC When the ADC is configured for 10-bit operation, the specifications in the data sheet are not met for operation above 500 ksps. Work around For 600 ksps operation, RIN = 500 ohms, TSAMP = 2 TAD. The module specifications are shown in Table 6. For 1000 ksps operation, RIN = 200 ohms, TSAMP = 2 TAD. The module specifications are shown in Table 7. TABLE 6: 600 KSPS OPERATION Parameter No. Symbol Minimum Typical Maximum Units AD17 RIN -- -- 200 Ohm ADC Accuracy - Measurements taken with External VREF+/VREFAD21c INL -1.5 -- 1.5 LSB AD22c DNL -1.4 -- 2.1 LSB AD23c GERR -1.2 -- 1.2 LSB ADC Accuracy - Measurements taken with Internal VREF+/VREFAD21d INL -1.5 -- 1.5 LSB AD22d DNL -1.4 -- 2.1 LSB TABLE 7: 1000 KSPS OPERATION Parameter No. Symbol Minimum Typical Maximum Units AD17 RIN -- -- 200 Ohm ADC Accuracy - Measurements taken with External VREF+/VREFAD21c INL -5.2 -- 6.5 LSB AD22c DNL -3.4 -- 7 LSB AD23c GERR -1.5 -- 1.5 LSB ADC Accuracy - Measurements taken with Internal VREF+/VREFAD21d INL -5.2 -- 6.5 LSB AD22d DNL -3.4 -- 7 LSB Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- -- X -- 2013-2018 Microchip Technology Inc. DS80000574G-page 7 PIC32MX330/350/370/430/450/470 2. Module: Clock 4. Module: I/O A clock signal is present on the CLKO pin, regardless of the clock source and setting of the CLKO Enable Configuration bit, OSCIOFNC (DEVCFG1<10>), during a Power-on Reset (POR) condition. The port pin, RF6, is not 5V tolerant. Use RF6 as a non-5V tolerant pin only. Work around Affected Silicon Revisions Do not connect the CLKO pin to a device that would be adversely affected by rapid pin toggling or a frequency other than that defined by the oscillator configuration. Do not use the CLKO pin as an input if the device connected to the CLKO pin would be adversely affected by the pin driving a signal out. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 3. Module: Reserved The issue, previously reported in a prior revision of this errata, is no longer relevant and was removed. Work around None. Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 5. Module: 5V Tolerant I/O Pins When internal pull-ups are enabled on 5V tolerant pins, the level as measured on the pin and available to external device inputs may not exceed the minimum value of VIH, and therefore qualify as a logic "high". However, with respect to the PIC32 device, as long as VDD 3V and the load doesn't exceed -50 A, the internal pull-ups are guaranteed to be recognized as a logic "high" internally to the device. Work around It is recommend to only use external pull-ups: * To guarantee a logic "high" for external logic input circuits outside of the PIC32 device * For PIC32 device inputs, if the external load exceeds -50 A or VDD < 3V Affected Silicon Revisions 2013-2018 Microchip Technology Inc. Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- DS80000574G-page 8 PIC32MX330/350/370/430/450/470 6. Module: Non-5V Tolerant I/O Pins When internal pull-ups are enabled on non-5V tolerant pins, the level as measured on the pin and available to external device inputs may not exceed the minimum value of VIH, and therefore qualify as a logic "high". However, with respect to the PIC32 device, as long as VDD 3V and the load doesn't exceed -50 A, the internal pull-ups are guaranteed to be recognized as a logic "high" internally to the device. 8. Module: JTAG Boundary Scan is not supported. Work around None. Affected Silicon Revisions A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- Work around It is recommend to only use external pull-ups: * To guarantee a logic "high" for external logic input circuits outside of the PIC32 device * For PIC32 device inputs, if the external load exceeds -50 A or VDD < 3V Affected Silicon Revisions Device Flash Memory (KB) 64 128 256 512 Device Silicon Revision A0 A1 B0 B1 -- -- -- X X X -- -- -- -- -- X -- -- 9. Module: Watchdog Timer When the Watchdog Timer module is used in Windowed mode, the module may issue a reset even if the user tries to clear the module within the allowed window. Work around None. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- 7. Module: I2C The slave address, 0x78, is one of a group of reserved addresses. It is used as the upper byte of a 10-bit address when 10-bit addressing is enabled. The I2C module control register allows the programmer to enable both 10-bit addressing and strict enforcement of reserved addressing, with the A10M and STRICT bits, respectively. When both bits are cleared, the device should respond to the reserved address 0x78, but it does not. Device Silicon Revision Device Flash Memory (KB) -- X -- -- 10. Module: Debug For PIC32MX350/450 devices, the programming pin pairs at PGEC2/PGED2 and PGEC3/PGED3 may not function for on-chip debugging if PGEC1 is open or is a logical "high". Work arounds Work around 1. None. 2. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 2013-2018 Microchip Technology Inc. Use the PGEC1/PGED1 pins for debugging, or Hold PGEC1 to VSS with an external resistor with a value of 150k or less while debugging on another pair. Affected Silicon Revisions Device Flash Memory (KB) 64 128 256 512 Device Silicon Revision A0 X X A1 B0 B1 X X -- -- X -- -- -- -- X -- DS80000574G-page 9 PIC32MX330/350/370/430/450/470 11. Module: USB 13. Module: Flash Memory If the bus has been idle for more than 3 ms, the IDLEIF interrupt flag is set. If software clears the interrupt flag and the bus remains idle, the IDLEIF interrupt flag will not be set again. The Program Write Protection (PWP) bits are not able to protect all 512 KB of Flash memory on PIC32MX370/470 devices. Work around The PWP<7:0> bits in the DEVCFG0 Configuration register can protect a maximum of 508 KB of Flash memory. Software can leave the IDLEIF bit set until it has received some indication of bus resumption (i.e., Resume, Reset, SOF, or Error). Note: Resume and Reset are the only interrupts that should be following IDLEIF assertion. If the IDLEIF bit is set, it should be okay to suspend the USB module (as long as this code is protected by the GUARD and/or ACTPEND logic). This will require software to clear the IDLEIF interrupt enable bit to exit the USB ISR (if using interrupt driven code). Work around Use a PWP<7:0> value of 0x10000000 for a maximum of 508 KB (memory location 0xBD07EFFF). Affected Silicon Revisions Device Flash Memory (KB) 64 128 256 512 Device Silicon Revision A0 A1 B0 B1 -- -- -- -- X -- -- -- Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 14. Module: Timer1 Timer1 fails to generate configured as follows: interrupts when * External Clock Input and * Asynchronous Clock and * Prescaler other than 1:1 Work around 12. Module: I/O Port The Open Drain selection (ODCx) on I/O port pins is not available when the pin is configured for anything other than a standard port output. In addition, the Open Drain feature is not available for dedicated or remappable Peripheral Pin Select (PPS) output features. Work around None. Affected Silicon Revisions Any other combination of the timer will generate interrupts as expected. For example, Synchronous mode or leaving the prescaler at 1:1. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 2013-2018 Microchip Technology Inc. DS80000574G-page 10 PIC32MX330/350/370/430/450/470 15. Module: UART 17. Module: CTMU The UART Automatic baud rate feature is intended to set the baud rate during run-time based on external data input. However, this feature does not function. The CTMU module is not functional. Work around Affected Silicon Revisions None. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 16. Module: UART During a RX FIFO overflow condition, the shift register stops receiving data. This causes the UART to lose synchronization with the serial data stream. The only way to recover from this is to turn the UART OFF and ON until it synchronizes. This could require several OFF/ON sequences. Work arounds Work around 1: Avoid the RX overrun condition by ensuring that the UARTx module has a high enough interrupt priority such that other peripheral interrupt processing latencies do not exceed the time to overrun the UART RX buffer based on the application baud rate. Alternately or in addition to, set the URXISEL bits in the UxSTA register to generate an earlier RX interrupt based on RX FIFO fill status to buy more time for interrupt latency processing requirements. Work around 2: If avoiding RX FIFO overruns is not possible, implement a ACK/NAK software handshake protocol to repeat lost packet transfers after restoring UART synchronization. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 2013-2018 Microchip Technology Inc. Work around None. Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 18. Module: ADC Converting the Internal Band Gap (IVREF) voltage source generates a High-Voltage Detect (HVD) event and aborts the conversion; therefore, this feature is not functional. Work around None. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 19. Module: HVD On power-up, the High-Voltage Detect Reset, event flag, RCON<HVDR>, is set incorrectly. On a power-up, only the POR, BOR, and EXTR bits should be set with the proper VCAP bypass capacitor value, as stated in the current data sheet. Work around Check the status of the POR bit in the RCON register when checking the HVDR bit. If the POR bit is set, both bits can be cleared as the HVDR bit is a false detection. If the POR bit is clear, the HVDR bit has been correctly detected and can be handled according to the requirements of the application. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- DS80000574G-page 11 PIC32MX330/350/370/430/450/470 20. Module: Power-Saving Modes 22. Module: Flash Memory On exit from Sleep mode, both the SLEEP and IDLE status bits in the RCON register are set. The Program Write Protection (PWP) bit field is off by one page relative to the data sheet definition. In silicon, PWP<7:0> = (n + 1), where `n' is the DEVCFG0<19:12> value as defined in the data sheet. Work around Add the following code to the user application at the point it wakes from Sleep mode: rcon_var1 = RCON; // ... enter Sleep mode if (rcon_var1 & 0x4) Nop(); // If IDLE bit already set previously // before sleep do nothing else RCONbits.IDLE = 0x0; // If IDLE bit is not set previously // and is after Sleep mode then clear TABLE 8: Value Expected Actual 11111111 Disabled Disabled 11111110 Memory below 0x01000 is write protected Disabled 11111101 Memory below 0x02000 is write protected Memory below 0x01000 is write protected Memory below 0x80000 is write protected Memory below 0x7F000 is write protected Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- X -- -- 21. Module: Flash Memory When enabled, the Boot Write Protect (BWP) bit inadvertently also protects and overlaps the first page of PWP user program space below 0x1000, (i.e., PWP<7:0> = 0xFE), in addition to the boot segment, regardless of the state of the Program Write Protection (PWP) bits (DEVCFG0<19:12>). If BWP is enabled by setting the BWP bit (DEVCFG0<24>) = 0, users cannot Page Erase or program the first page of the PWP user program space. Only user run-time Page Erase or Program operations are affected, which does not include a Bulk erase of the entire Flash. PWP BITS (DEVCFG0<19:12>) ... 01111111 Work around Set the PWP<7:0> bits (DEVCFG0<19:12>) = (DEVCFG0<PWP> - 1) to correct for the first page protection offset. Please refer to silicon issues 21 and 23 for related information. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- -- X -- Work around None. Please refer to silicon issues 22 and 23 for related information Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- -- 2013-2018 Microchip Technology Inc. X -- DS80000574G-page 12 PIC32MX330/350/370/430/450/470 23. Module: Flash Memory The Program Write Protection (PWP) bits (DEVCFG0<19:12>) are not enabled unless the Boot Write Protect (BWP) bit (DEVCFG0<24> is also enabled (i.e., = 0). Work around None. Please refer to silicon issues 21 and 22 for related information. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- -- X -- 24. Module: I/O Pins The RPF3 PPS (i.e. Peripheral Pin Select) functions are not available on PIN32MX4xx USB device variants. The PIC32MX3xx General Purpose devices are not affected. Work around None. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 B0 B1 64 128 256 512 X X X X X X X -- -- X -- -- -- -- 2013-2018 Microchip Technology Inc. X -- DS80000574G-page 13 PIC32MX330/350/370/430/450/470 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS60001185G): No clarifications to report at this time. 2013-2018 Microchip Technology Inc. DS80000574G-page 14 PIC32MX330/350/370/430/450/470 APPENDIX A: REVISION HISTORY Rev A Document (4/2013) Initial release of this document; issued for revision A0 silicon. Includes silicon issues 1 (ADC), 2 (Clock), 3 (Reserved), 4 (I/O), 5 (5V Tolerant I/O Pins), 6 (Non-5V Tolerant I/O Pins), 7 (I2C), 8 (JTAG), and 9 (Watchdog Timer). Rev B Document (6/2013) Updated the silicon revision to Rev. A1 and added the PIC32MX350/430/450 devices. Added silicon issues 10 (Debug), 11 (USB), and 12 (I/O Port). Updated silicon issue 3 (Reserved). Rev C Document (10/2013) Added the 512 KB (PIC32MX370/470). Flash memory devices Updated silicon issue 1 (ADC). Added silicon 14 (Timer1). issues 13 (Flash Memory) and Rev D Document (6/2014) Added Data Sheet Clarification 1 (Packaging) and 2 (Power-Down Current (IPD)). Rev E Document (2/2015) The document was updated for silicon revision B0 devices: * 128 KB devices were moved from Table 1 to Table 2. * Added separate 128 KB row to Affected Silicon Revisions tables. Added silicon issues 15 (UART), 16 (UART), 17 (CTMU), 18 (ADC), 19 (HVD), and 20 (Power-Saving Modes), 21 (Flash Memory), 22 (Flash Memory), and 23 (Flash Memory). Deleted silicon issue 3 (CTMU). Rev F Document (6/2015) Deleted Data Sheet Clarification 1 (Packaging). Added Data Sheet Clarification 1 (Power-Down Current (IPD)). Updated Table 31-7. Rev G Document (6/2018) Added issue 24 (I/O Pins). Removed Data Sheet Clarification 1 (Power-Down Current IPD). Added TABLE 3: "Silicon DEVREV Values For Devices With 256 KB Flash Memory" to reflect updates for the 256 Flash Memory. 2013-2018 Microchip Technology Inc. DS80000574G-page 15 Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3223-4 == ISO/TS 16949 == 2013-2018 Microchip Technology Inc. DS80000574G-page 16 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 DS80000574G-page 17 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Ra'anana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7289-7561 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 2013-2018 Microchip Technology Inc. 10/25/17