TOSHIBA TC58256FT TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M x 8BITS) CMOS NAND E2PROM DESCRIPTION The TC58256 is a single 3.3-V 256-Mbit (276,648,128) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E?PROM) organized as 528 bytes X 32 pages X 2048 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes x 32 pages). The TC58256 is a serial-type memory device which utilizes the I/O pins for both address and data input / output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non- volatile memory data storage. FEATURES @ Organization @ Power supply Memory cell array 528 K 64K X 8 Vec =3.8V+03V Register 528 X 8 e Access time Page size 528 bytes Cell array-register 25 vs max Block size (16K + 512) bytes Serial Read cycle 50 ns min @ Modes @ Operating current Read, Reset, Auto Page Program Read (50-ns cycle) 10 mA typ. Auto Block Erase, Status Read Program (avg.) 10 mA typ. @ Mode control Erase (avg.) 10 mA typ. Serial input/output Standby 100 vA Command control @ Packages TC58256FT : TSOP [ 48-P-1220-0.50 (Weight: 0.53 typ.) PIN ASSIGNMENT (TOP VIEW) PIN NAMES N Ned 2 O a ENC VO1 to8 | VO Port a3 46 4p CE i NCE i a5 BNC cE Chip Enable Ncg 5 44 pVO8 WE Write Enable GNDY 6 43 p07 RBO 7 42 Hl/O6 RE Read Enable Rey 8 10 pie CLE Command Latch Enable Ncq 10 39 BNC ALE Address Latch Enable Ncq 11 3g Nc - Veco 12 37 p vec WP Write Protect Ves ta 30 Ene RB Ready/Busy NcCq 15 34 HNC GND Ground input CLEG 16 33 BNC ALEY 17 32 pl/o4 Vec Power Supply WEY 18 31 Bl/O3 Wed 19 30 plo2 Vs5 Ground Ncq 20 29 bl/Ol Ncq 21 28 Nc NCQ 22 27 BNC NC 23 26 BNC NC 24 25 HNC 000707EBA2 @ TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Handbook etc.. @ The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 2000-09-22 1/33TOSHIBA TC58256FT BLOCK DIAGRAM Vee Vcc GND ? 79 v V7 vv 401 O<>} vO K Address register | >| Column buffer to : control Ke (A > Column decoder 08 O>} Circuit >| Command register eo Data register 4 Lt | | Sense amp a | vy sY cE O_> B B : WIR d|: CLE O>} a flo e|: ALEO>] Logic > Control d & y $ Memory WE c control circuit f d d g : cell array _ : RE O> 8 6|h |: WP o> g 2 |: A A RB O R/B HV generator ABSOLUTE MAXIMUM RATINGS SYMBOL ITEM RATING UNIT Vec Power Supply Voltage -0.6 to 4.6 Vv Vin Input Voltage -0.6 to 4.6 Vv Viio Input /Output Voltage -0.6 V~V..+ 0.3 V(E4.6 V) Vv Pp Power Dissipation 0.3 Ww TSoLDER Soldering Temperature (10s) 260 c Tstg Storage Temperature -55 to 150 C Topr Operating Temperature 0 to 70 C CAPACITANCE *(Ta = 25C, f = 1 MHz) SYMBOL PARAMETER CONDITION MIN MAX UNIT Cin Input Vin = OV - 10 pF Cout Output Vout = 0V - 10 pF * This parameter is periodically sampled and is not tested for every device. 2000-09-22 2/33TOSHIBA TC58256FT VALID BLOCKS ") SYMBOL PARAMETER MIN TYP. MAX UNIT Nve Number of Valid Blocks 2008 - 2048 Blocks (1) The TC58256 occasionally contains unusable blocks. Refer to Application Note (14) toward the end of this document. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT Vec Power Supply Voltage 3.0 3.3 3.6 Vv Vin High Level Input Voltage 2.0 - Veco +0.3 Vv VIL Low Level Input Voltage -0.3* - 0.8 Vv * -2V (pulse width = 20 ns) DC CHARACTERISTICS (Ta = 0 to 70C, Vcc = 3.3V + 0.3V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT lit Input Leakage Current Vin = OV to Ver - - +10 vA ILo Output Leakage Current Vout = 0.4V to Vec - - +10 pA lecoi Operating Current (Serial Read) CE = Vi, lour = OMA, trycle = 50 ns - 10 30 mA leco3 Operating Current (Command Input) teycle = 50 ns - 10 30 mA lecoa Operating Current (Data Input) teycle = 50 ns - 10 30 mA lecos Operating Current (Address Input) teycle = 50 ns - 10 30 mA leco7 Programming Current - - 10 30 mA Iccos Erasing Current - - 10 30 mA lees Standby Current CE = Vin - - 1 mA lecs2 Standby Current CE = Vec - 0.2V - - 100 pA Vou High Level Output Voltage lou = -400 pA 2.4 - - Vv VoL Low Level Output Voltage lo. = 2.1mMA - - 0.4 Vv lo. (R/B) | Output Current of R/B Pin VoL = 0.4V - 8 - mA 2000-09-22 3/33TOSHIBA TC58256FT AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70C, Vcc = 3.3V + 0.3V) SYMBOL PARAMETER MIN MAX UNIT NOTES teis CLE Setup Time 0 - ns teLH CLE Hold Time 10 - ns tes CE Setup Time 0 - ns tcH CE Hold Time 10 - ns twe Write Pulse Width 25 - ns tats ALE Setup Time 0 - ns tay ALE Hold Time 10 - ns tos Data Setup Time 20 - ns toy Data Hold Time 10 - ns twe Write Cycle Time 50 - ns twu WE-High Hold Time 15 - ns tww WP High to WE Low 100 - ns ter Ready-to-RE Falling Edge 20 - ns trp Read Pulse Width 35 - ns tre Read Cycle Time 50 - ns tREA RE Access Time (Serial Data Access) - 35 ns tcEH CE-High Time for Last Address in Serial Read Cycle 100 - ns (2) treaip | RE Access Time (ID Read) - 35 ns tou Data Output Hold Time 10 - ns truz RE-High-to-Output-High Impedance - 30 ns tcnz CE-High-to-Output-High Impedance - 20 ns tREH RE-High Hold Time 15 - ns tir Output-High-Impedance-to-RE Rising Edge 0 - ns trsto RE Access Time (Status Read) - 35 ns testo CE Access Time (Status Read) - 45 ns trow RE High to WE Low 0 - ns twue WE High to CE Low 30 - ns twHr WE High to RE Low 30 - ns tari ALE Low to RE Low (ID Read) 100 - ns tcr CE Low to RE Low (ID Read) 100 - ns tr Memory Cell Array to Starting Address - 25 us twe WE High to Busy - 200 ns tar2 ALE Low to RE Low (Read Cycle) 50 - ns trp RE Last Clock Rising Edge to Busy (in Sequential Read) - 200 ns tcry CE High to Ready (When interrupted by CE in Read Mode) - 600 + tr (R/B) ns (1) test Device Reset Time (Read/Program/Erase) - 6/10/500 us AC TEST CONDITIONS Input level : 24V/04V Input pulse rise and fall time : 3ns Input comparison level : 15V/15V Output data comparison level >: Lb5V/15V Output load : 1LTTL+Cy (100 pF) 2000-09-22 4/33TOSHIBA TC58256FT Note: (1) CE High to Ready time depends on the pull-up resistor tied to the R/B pin. (Refer to Application Note(7) toward the end of this document.) (2) Sequentral Read is terminated when tcry is grater than or equal to 100ns. If the RE to CE delay is less than 30 ns, R/B signal stays Ready. tcey = 100 ns * *: Vin or Vit RE VL MY Vf : 0 to 30ns > Busy signal is not output. 525 526 527 R/B \ | Busy PROGRAMMING AND ERASING CHARACTERISTICS (Ta = 0 to 70C, Vcc = 3.3V + 0.3V) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES tproc Average Programming Time 200 1000 pS N Number of Programming Cycles on Same Page 10 (1) tBERASE Block Erasing Time 3 4 ms P/E Number of Program/Erase Cycles 2.5 105 (2) (1) Refer to Application Note 12 toward the end of this document. (2) Refer to Application Note 15 toward the end of this document. 2000-09-22 5/33TOSHIBA TC58256FT TIMING DIAGRAMS Latch Timing Diagram for Command/Address /Data [ CLE ALE | ce E Setup Time Hold Time WE / tps tbH 1/01 to 8 SY . iy | 2 Vin or Vit Command Input Cycle Timing Diagram CLE teLs tet \ cs tcH we \ y tals tay ALE Wi f tos toy 01 to 8 2 VW; : Vin or Vit 2000-09-22 6/33TOSHIBA TC58256FT Address Input Cycle Timing Diagram CLE Ups teLs tes twe twe twu twH twe twe twe WE \ / \ / \ / tas tALH ALE os >| ton tos | ton tos || tou to ZA, A0to?7 Wik 0% WY A17 to 24 V \ UY Vin or Vit Data Input Cycle Timing Diagram teLH CLE L tats twe twH a ZL, twe twe twe tos | toy tos tos | toa toy d 01 to 8 DinO Wy Dint Diy 527 WZ 1 rh, \ tii > Vin or Vit 2000-09-22 7/33TOSHIBA Serial Read Cycle Timing Diagram tre TC58256FT tre tREH RE \ / \ LS LY RE tou tou <> tREA tREA tou | trHz trHz [<> [<> tRHz V/O1 to & trr R/B Status Read Cycle Timing Diagram CLE teLs A tcLH tes CE \ i) t twe Lt testo WE i f twuc tcuz tou RE ti t 25] ton trHz yores { om | ae RB / * 70H represents the hexadecimal number 70. : Vin or ViL 2000-09-22 8/33TOSHIBA TC58256FT Read Cycle (1) Timing Diagram CLE teLs teLH PA BAD A twe wz \ + \ f \ f_, LI . \_] I < > tcry TALS TALH tar2 ALE 4 GN Ll | IK A twe tre tre tal x \ tps toy \ tos tp ts toy tos toy teen vor QOH A0 to Ad to A17 to Dout Dout Dout to 8 AZ A16 A24 | N N+1 N+2 Column address N* re, R/B x t / : Vin or Vit Read Cycle (1) Timing Diagram: When Interrupted by CE CLE tcLH teLs | tes Pp ADA Z m~ LF Ck LA NL tye tals taLH ; tar2 tou ALE / want twe trr tre taLH RE \ / tps tou _tos tp tps tou tos | toy trea nee 701 00H AO to AQ to Al7 t Dout Dout Dout to 8 A7 A16 A24 | N N+1 N+2 Column address N* R/B N / \ j * Read operation using 00H command N: 0 to 255 > Vin or Vit 2000-09-22 9/33TOSHIBA Read Cycle (2) Timing Diagram CLE nil m ters teLH Dh Lb TC58256FT a J WE y l t we NY P\ SS \ f tats twe 1 tar2 >| taLH / ALE ] tALH tre RE tps tps _TV IVS tbH tby tre tREA /01 Ad to W AI to WAI7 to \ D (Dour) to 8 O1H AT A16 A24 our OUT Dout Column address 2564+M 256+M+4+1 527 N* R/B y * Read Operating using 01H command N:0 to 255 > Vin or Vit Read Cycle (3) Timing Diagram CLE tes ton 1 tes tcH |p ce / WHEN D D WE Y / t Ly tats twe tar2 T tay y ALE j Li taLH tre RE tps tos a aa tou tbH tre tREA 01 AO to AY to A17 to\ Column address 512+M 512+M+1 527 N* R/B y * Read Operating using 01H command N:0 to 15 > Vin or Vit 2000-09-22 10/33TOSHIBA Sequential Read (1) Timing Diagram CLE / \ 72 TC58256FT 22 nan Hy" OOH We TINE YE 75 to nF Column address N q Page tr tR address M Page M Page M+1 access access Sequential Read (2) Timing Diagram y Column address N VIN 22 2 22 22 22 22 2 22 2 22 :Viq or Vit LOU \ wan ty Cr GY TMA BV AE SF aa \__4 L Bey { 0 {1X2 527) 256 256 256 Page + + + tr address N N+1 N+2 Page M Page M +1 access access : Vin or Vit 2000-09-22 11/33TOSHIBA TC58256FT Sequential Read (3) Timing Diagram CLE / \ 2 22 2 22 2] 2 22 > 3 > > + 7 * BoE GE | a L/ vol ZI son YZ INS TOY BS 19 WATT nnn. eilann.et 4a IX A24 Ff tT Zi to 8 Ls Vt TT 7 WE EE Column Page tr 512 512 512 th 512-513 514 address address N oNS1 Na2 N M R/B \ \ Page M Page M+1 access access : Vin or Vit 2000-09-22 12/33TOSHIBA TC58256FT Auto-Program Operation Timing Diagram ters CLE ALE tps 01 AO to WA9 to WAI7 to 70H Status to 8 > Vin or Vit : Do not input data while data is being output. Auto Block Erase Timing Diagram CLE ters WE tBERASE ALE RE 01 Al7 to to 8 A24 R/B Auto Block Erase Erase Start Status Read Setup command command command > Vin or Vit : Do not input data while data is being output. 2000-09-22 13/33TOSHIBA TC58256FT ID Read Operation Timing Diagram taLH << ter tALH cH t a ARI ALE k RE N tos toy vor 90H { oo ) 98H 75H to 8 \ / tReAID tREAID Address input Maker code Device code > Vin or Vit 2000-09-22 14/33TOSHIBA TC58256FT PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode TCS8256FT command into the internal command register. The command is latched Ne into the command register from the I/O port on the rising edge of the WE CT! 06 48 PAC : : : : NC 2 47 A signal while CLE is High. neq 3 46 HNC Nc Address Latch Enable: ALE Ned . a E08 The ALE signal is used to control loading of either address information SN 4 6 3 Pee or input data into the internal address/data register. REG 8 41 Al/O5 Address information is latched on the rising edge of WE if ALE is High. ced 9 40 HNC Input data is latched if ALE is Low. NCY 10 39 BNC __. NCq 11 38 BNC Chip Enable: CE Vec4 12 37 AVcc , . a= . Ves 4 13 36 BVss The device goes into a low-power Standby mode when CE goes High Ncy 14 35 BNC during a Read_ operation. The CE signal is ignored when device is in NCY 15 34 PNG Busy state (R/B = L), such as during a Program or Erase operation, and CLE] 16 33 P VOA will not enter Standby mode even if the CE input goes High. The CE EL 18 31 b1/03 signal must stay Low during the Read mode Busy state to ensure that wed 19 30 Hl/O2 memory array data is correctly transferred to the data register. Ncq 20 29 H ve! NCQ 1 a] Write Enable: WE NCq 22 27 BNC _ N The WE signal is used to control the acquisition of data from the VO ncg 24 25 BNC port. a Figure 1. Pinout Read Enable: RE The RE signal controls serial data output. Data is available taza after the falling edge of RE. The internal column address counter is also incremented (Address= Address + 1) on this falling edge. TY/O Port: 1/01 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: R/B The R/B output signal is used to indicate the operating condition of the device. The R/B signal is in Busy state (R/B = L) during the Program, Erase and Read operations and will return to Ready state (R/B = H) after completion of the operation. The output buffer for this signal is an open drain. 2000-09-22 15/33TOSHIBA TC58256FT Schematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. 4 pages I 65536 I = 2048 block 81/0 | Figure 2. Schematic Cell Layout Table 1. Addressing > 32pages = 1 block A page consists of 528 bytes in which 512 bytes are used for main memory storage and 16 bytes are for redundancy or for other uses. lpage = 528 bytes lblock = 528 bytes X 32 pages = (16K + 512) bytes Capacity = 528 bytes X 32 pages X 2048 blocks An address is read in via the I/O port over three consecutive clock cycles, as shown in Table 1. AO to A7: Column address AQ9 to A24: Page address /08 07 06 /O5 04 03 1/Q2 V/O1 First cycle A7 A6 AS A4 A3 A2 Al AO Second cycle A16 A15 Al4 Ai13 A12 All A10 AQ Third cycle A24 A23 A22 A21 A20 A119 A18 A117 { A14 to A24: Block address ) \ AQ to A13: NAND address in block *: A8 is automatically set to Low or High by a OOH command or a 01H command. Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE, WE, RE and WP signals, as shown in Table 2. Table 2. Logic Table CLE ALE CE WE RE WP Command Input H L L LA H x Data Input L L L LA H * Address Input L H L LAK H * Serial Data Output L L L H NT * During Programming (Busy) * * * * * H During Erasing (Busy) * * * * * H Program, Erase Inhibit * * * * * L H: Vin, Lt Vin *: Vin or Vit 2000-09-22 16/33TOSHIBA TC58256FT Table 3. Command table (HEX) First Cycle Second Cycle Acceptable while Busy Serial Data Input 80 - Read Mode (1) 00 - Read Mode (2) 01 - Read Mode (3) 50 - Reset FF - O Auto Program 10 - Auto Block Erase 60 DO Status Read 70 - O ID Read 90 - HEX data bit assignment (Example) Serial data input: 80H ~ ~ ~ ~ Lilofofofofololfo} VO8S 7 6 5 4 3 2 VOI Once the device has been set to Read mode by a 00H, 01H or 50H command, additional Read commands are not needed for sequential page Read operations. Table 4 shows the operation states for Read mode. Table 4. Read mode operation states CLE ALE CE WE RE 01 TO 1/08 Power Output Select L L L H L Data output Active Output Deselect L L L H H High impedance Active Standby L L H H * High impedance Standby H: Vy L: Vit *: Vin or Vit 2000-09-22 17/33TOSHIBA TC58256FT DEVICE OPERATION Read Mode (1) Read mode (1) is set when a "00H" command is issued to the Command register. Refer to Figure 3 below for timing details and the block diagram. ce f[ \ e \AA LA BP we VU YW \n ALE / a A data transfer operation from the cell array to the Start-address input register starts on the rising edge of WE in the third cycle M| 527 (after the address information has been latched). The device L_ =f I > will be in Busy state during this transfer period. The CE signal must stay Low after the third address input and Select page _, during Busy state. N A Al Cell array After the transfer period the device returns to Ready ~~ ~ state. Serial data can be output synchronously with the RE clock from the start pointer designated in the address input Figure 3. Read mode (1) operation cycle. Read Mode (2) ce f[ \ ce \PARA we VV UU MW Start-address input M 296 527 The operation of the device after input of the 01H command is : the same as that of Read mode (1). If the start pointer is to be set Select page \ after column address 256, use Read mode (2). N > Cell array However, for a Sequential Read, output of the next page starts RY i RY | : J from column address 0. Figure 4. Read mode (2) operation 2000-09-22 18/33TOSHIBA TC58256FT Read Mode (8) Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra 16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527. ce [ \ ec LA A BA we Ue u Me AO to A3 512 527 [ 4 EZE 4 > Addresses bits AO to A3 are used to set the start pointer XC for the redundant memory cells, while A4 to A7 are ignored. Once a "50H" command has been issued, the pointer moves to A A the redundant cell locations and only those 16 cells can be WW w addressed, regardless of the value of the A4-to-A7 address. (An "00H" command is necessary to move the pointer back to Figure 5. Read mode (3) operation the 0-to-511 main memory cell location.) 2000-09-22 19/33TOSHIBA TC58256FT Sequential Read (1)(2)(3) This mode allows the sequential reading of pages without additional address input. Gor) SS tr SS tr SS tr Address input ___ Data output < Data output 4 <> R/B Busy Busy Busy 0 527 (01H) (50H) 512 527 (Eee (EE Sequential Read (1) Sequential Read (2) Sequential Read (3) Sequential Read modes (1) and (2) output the contents of addresses 0 to 527 as shown above, while Sequential Read mode (3) outputs the contents of the redundant address locations only. When the pointer reaches the last address, the device continues to output the data from this address ** on each RE clock signal. ** Column address 527 on the last page 2000-09-22 20/33TOSHIBA TC58256FT Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port onthe RE clock after a "70H" command input. The resulting information is outlined in Table 5. Table 5. Status output table STATUS OUTPUT 1/01 Pass / Fail Pass: 0 Fail: 1 ; vroz| Wot Used | 0 we eee Sas en on ga 1/03 Not Used 0 1/04 Not Used 0 1/05 Not Used 0 1/06 Not Used 0 1/07 Ready / Busy Ready: 1 Busy: 0 1/08 Write Protect Protect: 0 Not Protected: 1 An application example with multiple devices is shown in Figure 6. CE, CE> CE3 CEy CEN +1 d d Device Device Device Device Device 1 2 3 N N+1 RE \ / \ / VO { 70H ) { ) { 70H } { ) . < Status on A status on Device 1 Device N Figure 6. Status Read timing application example System Design Note: If the R/B pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. 2000-09-22 21/33TOSHIBA TC58256FT Auto Page Program The device carries out an Automatic Page Program operation when it receives a "10H" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) 80 { } NY Data input Program command Status Read command Data input command Address input 0 to 527 rs | Data input Program Reading & verification 7 The data is transferred (programmed) from the register to the Selected selected page on the rising edge of WE following input of the page "10H" command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is Figure 7. Auto Page Pragram operation reached. / R/B automatically returns to Ready after completion of the operation. Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command "DOH" which follows the Erase Setup command "60H". This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. Ox] om 60 DO 70 ,, Fail Block address Erase Start Status Read input: 2 cycles command command R/B Busy | 2000-09-22 22/33TOSHIBA TC58256FT Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The address and data registers are set as follows after a Reset: - Address Register: All "0" - Data Register: All "1" - Operation Mode: Wait state The response to an "FFH" Reset command input during the various device operations is as follows: + When a Reset (FFH) command is input during programming C80 ) {10 ) ( FF ) { 00 } NJ NEY Na Register set Internal Vpp Of R/B . << <_>. trst (max 10 ys) | Figure 8. + When a Reset (FFH) command is input during erasing 007 FF 00 Internal erase fe Register set . voltage : : _ i test (max 500 YS) R/B \ Figure 9. When _a Reset (FFH) command is input during a Read operation a | __| trst (max 6 ys) | Figure 10. * When a Status Read command (70H) is input after a Reset { 70 _ . : |/Ostatus: Pass/Fail Pass _ Ready / Busy > Ready R/B | However, the following operation is prohibited. If the following operation is executed, correct resetting of the address and data register cannot be guaranteed. Ci > C70) 1/Ostatus: Ready/Busy > Busy R/B \ ; | Figure 11. (FF) * When two or more Reset commands are input in succession (1) (2) (3) {10 ) { FF ) { FF ) (FF) The second command is invalid, but the third CF) command is Figure 12. 2000-09-22 23/33TOSHIBA TC58256FT ID Read The TC58V64FT/DC contains ID codes which identify the device type and the manufacturer. The ID codes can be read out under the following timing conditions: CLE | \ CE WE ALE RE tREAID vo 90H 00 98H ID Read command Address Maker code 00 75H Device code For the specifications of the access times treaip, tcr and tar; refer to the AC Characteristics. Figure 13. ID Read timing Table 6. Code table 08 O07 706 VO5 1/04 03 V/O2 01 Hex Data Maker code 1 0 0 1 1 0 0 0 98H Device code 0 1 1 1 0 1 0 1 75H 2000-09-22 24/33TOSHIBA APPLICATION NOTES AND COMMENTS (1) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. TC58256FT (2) Restriction of command while Busy state During Busy state, do not input any command except 70H and FFH. (3) Pointer control for "00H", "01H" and "50H" The device has three Read modes which set the destination of the pointer. destination of the pointer, and Figure 14 is a block diagram of their operations. Table 7 shows the . : . 0 255 256 511512 527 Table 7. Pointer Destination A B c Read Made Command Pointer Jad oo To) ee TTI _ J (1) 00H 0 to 255 \ [ / (2) 01H 256 to 511 (3) 50H 512 to 527 00H > 01H > Pointer control 50H > Figure 14. Pointer control The pointer is set to region A by the "00H" command, to region B by the "01H" command, and to region C by the "50H" command. (Example) The "00H" command must be input to set the pointer back to region A when the pointer is pointing to region C. 00H (50H) Address Start point Address Start point Address = Start point A area A area C area 30H (00H } LS ) ae Address Start point Address Start point Address Start point C area C area A area O1H KY Address Start point Address Start point B area A area To program region C only, set the start point to region C using the 50H command. (fOr) Con) 10H 50H ) _--__ " Address DIN 1 Programming region C only Start point C area (irr) Con) 01H VS n-__ Address DIN 1 Programming regions B and C Start point B area Figure 15. Example of How to Set the Pointer 2000-09-22 25/33TOSHIBA TC58256FT (4) Acceptable commands after Serial Input command "80H" Once the Serial Input command "80H" has been input, do not input any command other than the Program Execution command "10H" or the Reset command "FFH". C80 ) CE we L--FLILrlei KY Address input R/B i Figure 16. If a command other than "10H" or "FFH" is input, the Program operation is not performed. Ceo) Ox) Co) \ For this operation the "FFH" command is Command Other Programming cannot be executed. needed. than "10H" or "FFH" (5) Status Read during a Read operation [A] Command Coo) ce \_S\ we LY \ Q A RE Status Read LT LIV Address N - command input Status Read Status output Figure 17. The device status can be read out by inputting the Status Read command "70H" in Read mode. Once the device has been set to Status Read mode by a "70H" command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command "00H" is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary . (6) Auto programming failure nn Fail non nn 80 10 70 vO 80 10 Address Data Address Data M input N input 80 If the programming result for page address M is Fail, do not try to program the page to address N in another block. Because the previous input data has been lost, the same input sequence of 80H command, address and data is necessary. Figure 18. 2000-09-22 26/33TOSHIBA TC58256FT (7) R/B: termination for the Ready/Busy pin (R/B) A pull-up resistor needs to be used for termination because the R/B buffer consists of an open drain circuit. Vec Vv . \ " se R : : : Devi : 1. B OVS : evice -: RE usy 5 fi 4 I cL : ae Vec=3.3V Vss 1.5 ws Ta=25C 7 1590Ns C_ = 100 pF Figure 19. t + P t, 1.0 4s 10 ns tt . . . 0.5 ys 51ns This data may vary from device to device. i We recommend that you use this data as a | | | reference when selecting a resistor value. 0 1kQ 2kQ 3kQ 4kQ R (8) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on. ower on } P f FF } Reset Figure 20. (9) Power-on/off sequence: The WP signal is useful for protecting against data corruption at power-on/off. The following timing sequence is necessary: 3.0V._: 28V 74: ov a Dont : : care CE, WE, RE CLE, ALE Dot Vin : Vit ViL RAP _______ Operation : A Figure 21. Power-on/off Sequence 2000-09-22 27/33TOSHIBA TC58256FT (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming we ]|_J Lf fat N I oa DIN rn 80 } { 10 ) WP D> I RB <>! | tww 100 ns min Disable Programming I DIN rf 5 rN WP | ' I I! L R/B ey tww 100 ns min Enable Erasing WE | | I os, DIN : 60 } WP I 1 RB I> tww 100 ns min Disable Erasing we 1_| OL OL | I ao DIN 4 60 } ,_ I WP 1 R/B es tww 100 ns min 2000-09-22 28/33TOSHIBA TC58256FT (11) When four address cycles are input Although the device may read in a fourth address, it is ignored inside the chip. Read operation 4 OOH, 01H or 50H Address input R/B \ Internal read operation starts when WE goes High in the third cycle. Ignored Figure 22. Program operation ALE / \ yo {}{H{_ XX) HHH Noone fe neat Address input Data input Ignored Figure 23. 2000-09-22 29/33TOSHIBA TC58256FT (12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 10 segments. Each segment can be programmed individually as follows: First programming Data Pattern 1 Second programming Data f Pattern2 Tenth programming Data pattern 10 Data Result Data Pattern?) || rete tte ttt teen ee entree tenner reer eee ewan eee tee Data Pattern 10 Pattern 2 Figure 24. Note: The input data for unprogrammed or previously programmed page segments must be "1" (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all "1"). (13) Note regarding the RE signal The internal column address counter is incremented synchronously with the RE clock in Read mode. Therefore, once the device has been set to Read mode by a "OOH", "01H" or "50H" command, the internal column address counter is incremented by the RE clock independently of the address input timing. If the RE clock input pulses start before the address input, and the pointer reaches the last column address, an internal read operation (array register) will occur and the device will enter Busy state. (Refer to Figure 25.) Address input 00H /01H/ Figure 25. Hence the RE clock input must start after the address input. 2000-09-22 30/33TOSHIBA TC58256FT (14) Invalid blocks (bad blocks) The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad and do not use these bad blocks. Bad Block > Bad Block Figure 26. Read Check | Block No. = Block No. + 1 Pass No At the time of shipment, all data bytes in a Valid Block are FFh. For Bad Blocks, all bytes are not in the FFh state. Please dont perform erase operation to Bad Blocks. Check if the device has any bad blocks after installation into the system. Figure 27 shows the test flow for bad block detection. Bad Blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the Bit line by the Select gate. The number of valid blocks at the time of shipment is as follows: MIN TYP. MAX UNIT Valid (Good) Blocks 2008 - 2048 Block Read Check : to verify if any pages in the block contains data other than FF(Hex) Block No= 1 Bad Block *1 = 2048 Yes Test End Block No. *1 : No erase operation is allowed to bad blocks. Figure 27. 2000-09-22 31/33TOSHIBA TC58256FT (15) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase > Block Replacement Page Programming Failure Status Read after Program > Block Replacement Single Bit* Programming Failure (1) Block Verify after Program - Retry "439" (2) ECC @ECC : Error Correction Code Hamming Code etc. Example: 1-bit correction & 2-bit detection @ Block Replacement Program Error occurs When an error hoppens in Block A, try to Buffer memory reprogram the data into another (Block B) by \ Block A loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using another \ Block B appropriate scheme). ) Figure 28. Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). 2000-09-22 32/33TOSHIBA TC58256FT PACKAGE DIMENSIONS @ Plastic TSOP TSOP I 48 P12200.50 Unit: mm 1 48 eo oS Oo FI SN A Oo} - s 315 | ail a J amit e) I ss 25 af 4 = + 18.440.1 b 1.0+0.1 | || 0.1+0.05 | 20.040.2 S t.2max | | wo wo oO OQ 7 8 / Sh JA if TL Fy (te i oO _ 0.50.1 2000-09-22 33/33