Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 LM5111 Dual 5-A Compound Gate Driver 1 Features 3 Description * * The LM5111 Dual Gate Driver replaces industry standard gate drivers with improved peak output current and efficiency. Each compound output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 5-A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Undervoltage lockout protection is also provided. The drivers can be operated in parallel with inputs and outputs connected to double the drive current capability. This device is available in the SOIC package or the thermally enhanced MSOPPowerPAD package. 1 * * * * * * * * * Independently Drives Two N-Channel MOSFETs Compound CMOS and Bipolar Outputs Reduce Output Current Variation 5-A Sink and 3-A Source Current Capability Two Channels can be Connected in Parallel to Double the Drive Current Independent Inputs (TTL Compatible) Fast Propagation Times (25 ns Typical) Fast Rise and Fall Times (14 ns and 12 ns Rise and Fall, Respectively, With 2-nF Load) Available in Dual Noninverting, Dual Inverting and Combination Configurations Supply Rail Undervoltage Lockout Protection (UVLO) LM5111-4 UVLO Configured to Drive PFET through OUT_A and NFET through OUT_B Pin Compatible With Industry Standard Gate Drivers Device Information(1) PART NUMBER LM5111 PACKAGE SOIC (8) BODY SIZE (NOM) 5.00 mm x 6.00 mm MSOP-PowerPAD (8) 3.00 mm x 4.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications * * * Synchronous Rectifier Gate Drivers Switch-mode Power Supply Gate Driver Solenoid and Motor Drivers Simplified Application Diagram LM5111 INA INB 1 N/C N/C 8 2 INA OUTA 7 3 VEE VCC 6 4 INB OUTB 5 0.1 F 1.0 F Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Options....................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagram ......................................... 9 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 10 9 Application and Implementation ........................ 11 9.1 Application Information............................................ 11 9.2 Typical Application ................................................. 11 10 Power Supply Recommendations ..................... 13 10.1 Bias Supply Voltage.............................................. 13 11 Layout................................................................... 13 11.1 Layout Guidelines ................................................. 13 11.2 Layout Example .................................................... 14 11.3 Thermal Considerations ........................................ 14 12 Device and Documentation Support ................. 17 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 17 13 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (March 2013) to Revision H * Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table, Recommended Operating Conditions table, Thermal Information table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 Changes from Revision F (March 2013) to Revision G * 2 Page Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 16 Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 5 Device Options Table 1. Configuration Table PART NUMBER "A" OUTPUT CONFIGURATION "B" OUTPUT CONFIGURATION PACKAGE LM5111-1M/-1MX/-1MY/-1MYX Noninverting (Low in UVLO) Noninverting (Low in UVLO) SOIC, MSOP-PowerPAD LM5111-2M/-2MX/-2MY/-2MYX Inverting (Low in UVLO) Inverting (Low in UVLO) SOIC, MSOP-PowerPAD LM5111-3M/-3MX/-3MY/-3MYX Inverting (Low in UVLO) Noninverting (Low in UVLO) SOIC, MSOP-PowerPAD LM5111-4M/-4MX/-4MY/-4MYX Inverting (High in UVLO) Noninverting (Low in UVLO) SOIC, MSOP-PowerPAD 6 Pin Configuration and Functions D and DGN Package 8-Pin SOIC and MSOP-PowerPAD Top View NC IN_A VEE IN_B 1 8 2 7 3 6 4 5 NC OUT A VCC OUT_B Pin Functions PIN NAME NO. I/O DESCRIPTION IN_A 2 I `A' side control input. TTL compatible thresholds. IN_B 4 I `B' side control input. TTL compatible thresholds. OUT_A. 7 O Output for the `A' side driver. Voltage swing of this output is from VCC to VEE. The output stage is capable of sourcing 3 A and sinking 5 A. OUT_B 5 O Output for the `B' side driver. Voltage swing of this output is from VCC to VEE. The output stage is capable of sourcing 3 A and sinking 5 A. VCC 6 -- Positive output supply. Locally decouple to VEE. VEE 3 -- Ground reference for both inputs and outputs. Connect to power ground. NC 1, 8 -- No Connection -- It is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PC board to aid thermal dissipation. Exposed Pad (1) (1) Only available with the MSOP-PowerPAD package. Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 3 LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings see (1) (2) MIN MAX UNIT VCC to VEE -0.3 15 V IN to VEE -0.3 Maximum junction temperature, TJ(max) -55 Storage temperature, Tstg (1) (2) 15 V 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 7.2 ESD Ratings V(ESD) (1) Electrostatic discharge VALUE UNIT 2000 V Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TJ NOM Operating junction temperature MAX UNIT 125 C 7.4 Thermal Information LM5111 THERMAL METRIC (1) D (SOIC) DGN (MSOP-PowerPAD) UNIT 8 PINS 8 PINS RJA Junction-to-ambient thermal resistance 112.2 50.7 C/W RJC(top) Junction-to-case (top) thermal resistance 54.6 56.6 C/W RJB Junction-to-board thermal resistance 53.1 35.9 C/W JT Junction-to-top characterization parameter 9.4 5.3 C/W JB Junction-to-board characterization parameter 52.5 35.6 C/W RJC(bot) Junction-to-case (bottom) thermal resistance N/A 4.4 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 7.5 Electrical Characteristics TJ = -40C to +125C, VCC = 12 V, VEE = 0 V, No Load on OUT_A or OUT_B, unless otherwise specified. PARAMETER TEST CONDITIONS MIN VCC operating range VCC-VEE 3.5 VCCR VCC undervoltage lockout (rising) VCC-VEE 2.3 VCCH VCC undervoltage lockout hysteresis ICC VCC supply current (ICC) TYP MAX 2.9 3.5 UNIT 14 V V 230 mV IN_A = IN_B = 0 V (5111-1) 1 2 IN_A = IN_B = VCC (5111-2) 1 2 IN_A = VCC, IN_B = 0 V (5111-3) 1 2 mA CONTROL INPUTS VIH Logic high VIL Logic low VthH High threshold 1.3 VthL Low threshold 0.8 HYS Input hysteresis IIL Input current low IIH Input current high 2.2 V 0.8 V 1.75 2.2 V 1.35 2 V 400 mV IN_A=IN_B=VCC (5111-1-2-3) -1 0.1 1 IN_B=VCC (5111-3) 10 18 25 IN_A=IN_B=VCC (5111-2) -1 0.1 1 IN_A=IN_B=VCC (5111-1) 10 18 25 IN_A=VCC (5111-3) -1 0.1 1 A OUTPUT DRIVERS ROH Output resistance high IOUT = -10 mA (1) 30 50 ROL Output resistance low IOUT = + 10 mA (1) 1.4 2.5 ISource Peak source current OUTA/OUTB = VCC/2, 200-ns Pulsed Current 3 A ISink Peak sink current OUTA/OUTB = VCC/2, 200-ns Pulsed Current 5 A LATCHUP PROTECTION AEC - Q100, method 004 TJ = 150C 500 SOIC Package 170 mA THERMAL RESISTANCE JA Junction to ambient, 0 LFPM air flow JC Junction to case (1) MSOP-PowerPAD Package C/W 60 SOIC Package 70 MSOP-PowerPAD Package 4.7 C/W The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and Bipolar devices. 7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td1 Propagation delay time low to high, IN rising (IN to OUT) CLOAD = 2 nF (1) 25 40 ns td2 Propagation delay time high to low, IN falling (IN to OUT) CLOAD = 2 nF (1) 25 40 ns tr Rise time CLOAD = 2 nF (1) 14 25 ns tf Fall time CLOAD = 2 nF (1) 12 25 ns (1) See Figure 1 and Figure 2. Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 5 LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 www.ti.com 50% 50% INPUT tD2 tD1 OUTPUT 90% 10% tr tf Figure 1. Inverting 50% 50% INPUT tD1 tD2 90% OUTPUT 10% tr tf Figure 2. Noninverting 6 Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 7.7 Typical Characteristics 100 1000 TA = 25C 10 VCC = 12V VCC = 10V VCC = 5V 1 f = 500kHz SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VCC = 15V 100 10 f = 100kHz 1 TA = 25C f = 10kHz CL = 2200pF 0.1 100 0.1 1 10 100 1000 10k 1k CAPACITIVE LOAD (pF) FREQUENCY (kHz) Figure 4. Supply Current vs Capacitive Load Figure 3. Supply Current vs Frequency 20 20 TA = 25C VCC = 12V CL = 2200pF 18 18 16 16 CL = 2200pF TIME (ns) TIME (ns) tr tr 14 14 tf tf 12 12 10 10 4 5 6 7 8 9 10 11 12 13 14 15 16 -75 -50 -25 0 25 50 75 100 125 150 175 SUPPLY VOLTAGE (V) TEMPERATURE (C) Figure 5. Rise and Fall Time vs Supply Voltage Figure 6. Rise and Fall Time vs Temperature 50 32.5 TA = 25C TA = 25C VCC = 12V CL = 2200pF 30 40 tr 20 tD2 TIME (ns) TIME (ns) 27.5 30 tf 25 22.5 tD1 10 20 17.5 0 100 1k CAPACITIVE LOAD (pF) 10k 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) Figure 7. Rise and Fall Time vs Capacitive Load Figure 8. Delay Time vs Supply Voltage Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 7 LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 www.ti.com Typical Characteristics (continued) 32.5 3.25 VCC = 12V CL = 2200pF IOUT = 10mA 2.75 tD2 25 tD1 45 2.25 1.75 35 ROH (:) ROH ROL (:) TIME (ns) 27.5 55 ROL 22.5 1.25 20 25 15 0.75 17.5 -75 -50 -25 0 0 25 50 75 100 125 150 175 9 12 15 18 Figure 10. RDSON vs Supply Voltage 3.100 UVLO THRESHOLDS (V) 6 SUPPLY VOLTAGE (V) TEMPERATURE (C) Figure 9. Delay Time vs Temperature 0.450 VCCR 2.800 2.500 3 VCCF 0.390 0.330 2.200 0.270 VCCH 1.900 1.600 -75 -50 -25 0 HYSTERESIS (V) 30 65 TA = 25C 0.210 0.150 25 50 75 100 125 150 175 TEMPERATURE (C) Figure 11. UVLO Thresholds and Hysteresis vs Temperature 8 Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 8 Detailed Description 8.1 Overview LM5111 dual gate driver consists of two independent and identical driver channels with TTL compatible logic inputs and high current totem-pole outputs that source or sink current to drive MOSFET gates. The driver output consist of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical threshold region of the MOSFET VGS while the MOS devices provide rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin. The control inputs of the drivers are high impedance CMOS buffers with TTL compatible threshold voltages. The LM5111 pinout was designed for compatibility with industry standard gate drivers in single supply gate driver applications. The input stage of each driver should be driven by a signal with a short rise and fall time. Slow rising and falling input signals, although not harmful to the driver, may result in the output switching repeatedly at a high frequency. 8.2 Functional Block Diagram VCC UVLO VEE OUT_A IN_A VEE VCC IN_B OUT_B VEE Copyright (c) 2016, Texas Instruments Incorporated Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 9 LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 www.ti.com 8.3 Feature Description 8.3.1 Undervoltage Lockout An undervoltage lockout (UVLO) circuit is included in the LM5111, which senses the voltage difference between VCC and the chip ground pin, VEE. When the VCC to VEE voltage difference falls below 2.8 V both driver channels are disabled. The UVLO hysteresis prevents chattering during brown-out conditions and the driver resumes normal operation when the VCC to VEE differential voltage exceeds approximately 3 V. The LM5111-1, -2, and -3 devices hold both outputs in the low state in the UVLO condition. The LM5111-4 is distinguished from the LM5111-3 by the active high output state of OUT_A during UVLO. When VCC is less than the UVLO threshold voltage, OUT_A of the LM5111-4 will be locked in the high state while OUT_B will be disabled in the low state. This configuration allows the LM5111-4 to drive a PFET through OUT_A and an NFET through OUT_B with both FETs safely turned off during UVLO. 8.3.2 Output Stage The two driver channels of the LM5111 are designed as identical cells. Transistor matching inherent to integrated circuit manufacturing ensures that the AC and DC peformance of the channels are nearly identical. Closely matched propagation delays allow the dual driver to be operated as a single with inputs and output pins connected. The drive current capability in parallel operation is precisely 2x the drive of an individual channel. Small differences in switching speed between the driver channels will produce a transient current (shoot-through) in the output stage when two output pins are connected to drive a single load. Differences in input thresholds between the driver channels will also produce a transient current (shoot-through) in the output stage. Fast transition input signals are especially important while operating in a parallel configuration. The efficiency loss for parallel operation has been characterized at various loads, supply voltages and operating frequencies. The power dissipation in the LM5111 increases be less than 1% relative to the dual driver configuration when operated as a single driver with inputs/ outputs connected. 8.4 Device Functional Modes Table 2. Input/output Logic Table LM5111-1M LM5111-3M/LM5111-4M IN B OUT A OUT B IN A IN B OUT A OUT B IN A IN B OUT A OUT B L L L L L L H H L L H L H L H L H L H H L L H H H L H L H L L H H L L L H H H H H H L L H H L H L L L L L/H L/L In UVLO 10 LM5111-2M IN A In UVLO Submit Documentation Feedback In UVLO Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information High-frequency power supplies often require high-speed, high-current drivers such as the LM5111 family. A leading application is the need to provide a high-power buffer stage between the PWM output of the control IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is used to drive the power-device gates through a drive transformer. Synchronous rectification supplies are also needed to simultaneously drive multiple devices which presents an extremely large load to the control circuitry. Driver ICs are used when use of the primary PWM regulator IC to directly drive the switching devices for one or more reasons is not feasible. The PWMIC does not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases, there may be a desire to minimize the effect of high-frequency switching noise by placing the high current driver physically close to the load. Also, newer ICs that target the highest operating frequencies do not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCCx732x. Finally, the control IC is under thermal stress due to power dissipation, and an external driver helps by moving the heat from the controller to an external package. 9.2 Typical Application LM5111 INA INB 1 N/C N/C 8 2 INA OUTA 7 3 VEE VCC 6 4 INB OUTB 5 0.1 F 1.0 F Copyright (c) 2016, Texas Instruments Incorporated Figure 12. LM5111 Driving Two Independent MOSFETs 9.2.1 Design Requirements To select the proper device from the LM5111 family, TI recommends first checking the appropriate logic for the outputs. LM5111 has dual inverting outputs; dual noninverting outputs; inverting channel A and noninverting channel B. Refer to operating modes to select which driver from the family is required in a given application. Moreover, some design considerations must be evaluated first in order to make the most appropriate selection. Among these considerations are VCC and power dissipation. Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 11 LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure 9.2.2.1 VCC Although quiescent VCC current is very low, total supply current will be higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated using Equation 1. IOUT = Qg x f where * f is frequency (1) For the best high-speed circuit performance, two VCC bypass capacitors are recommended to prevent noise problems. The use of surface mount components is highly recommended. A 0.1-F ceramic capacitor should be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1 F and above) with relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels in the driver application. 9.2.3 Application Curves 100 1000 TA = 25C 10 VCC = 12V VCC = 10V VCC = 5V 1 f = 500kHz SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VCC = 15V 100 10 f = 100kHz 1 TA = 25C f = 10kHz CL = 2200pF 0.1 1 10 100 0.1 100 1000 Figure 13. Supply Current vs Frequency 12 1k 10k CAPACITIVE LOAD (pF) FREQUENCY (kHz) Figure 14. Supply Current vs Capacitive Load Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 10 Power Supply Recommendations 10.1 Bias Supply Voltage The recommended bias supply voltage range for LM5111 is from 3.5 V to 14 V. The upper end of this range is driven by the 15-V absolute maximum voltage rating of the VCC. TI recommends keeping proper margin to allow for transient voltage spikes. A local bypass capacitor must be placed between the VCC and VEE pins, and this capacitor must be placed as close to the device as possible. TI recommends a low ESR, ceramic surface mount capacitor. TI recommends using 2 capacitors across VCC and VEE: a 100-nF ceramic surface-mount capacitor for high frequency filtering placed very close to VCC and VEE pin, and another surface-mount capacitor, 220 nF to 10 F, for IC bias requirements. 11 Layout 11.1 Layout Guidelines Attention must be given to board layout when using LM5111. Some important considerations include: * A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support high peak currents being drawn from VCC during turnon of the MOSFET. * Proper grounding is crucial. The drivers need a very low impedance path for current return to ground avoiding inductive loops. The two paths for returning current to ground are a) between LM5111 VEE pin and the ground of the circuit that controls the driver inputs, b) between LM5111 VEE pin and the source of the power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the LM5111. A good method is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface. * With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the LM5111. * The LM5111 footprint is compatible with other industry standard drivers including the TC4426/27/28 and UCC27323/4/5. * If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either VEE or VCC to avoid spurious output signals. Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 13 LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 www.ti.com 11.2 Layout Example Power Stage Current U1 Output Loop of Driver 1: N/C 8: N/C 2: N/C INA INA 7: OUTA 3: VEE N/C VEE 4: N/C INB INB VEE Bias Loop 6: VCC Q1 4 R4 3 5: OUTB R3 C2 (Bypass Capacitor) Figure 15. Layout 11.3 Thermal Considerations The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum TJ of IC components in worst case operating conditions. The junction temperature is estimated based on the power dissipated in the IC and the junction to ambient thermal resistance JA for the IC package in the application board and environment. The JA is not a given constant for the package and depends on the printed circuit board design and the operating environment. 11.3.1 Drive Power Requirement Calculations in LM5111 The LM5111 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to switch the MOSFET gate very quickly for operation at high frequencies. 14 Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 Thermal Considerations (continued) VGATE VHIGH Q1 RG VTRIG CIN Q2 Figure 16. Driver Output Stage and Load The schematic above shows a conceptual diagram of the LM5111 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. RG is the gate resistance of the external MOSFET, and CIN is the equivalent gate capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected. The equivalent gate capacitance is a difficult parameter to measure since it is the combination of CGS (gate to source capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capacitances are not constants and vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge QG in coulombs. QG combines the charge required by CGS and CGD for a given gate drive voltage VGATE. Assuming negligible gate resistance, the total power dissipated in the MOSFET driver due to gate charge is approximated by PDRIVER = VGATE x QG x FSW where * FSW = switching frequency of the MOSFET (2) For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12 V. The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching frequency of 300 kHz and VGATE of 12 V is equal to PDRIVER = 12 V x 30 nC x 300 kHz = 0.108 W. (3) If both channels of the LM5111 are operating at equal frequency with equivalent loads, the total losses will be twice as this value which is 0.216 W. In addition to the above gate charge power dissipation, transient power is dissipated in the driver during output transitions. When either output of the LM5111 changes state, current will flow from VCC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and Under-voltage lockout sections. Characterization of the LM5111 provides accurate estimates of the transient and quiescent power dissipation components. At 300-kHz switching frequency and 30-nC load used in the example, the transient power will be 8 mW. The 1-mA nominal quiescent current and 12-V VGATE supply produce a 12-mW typical quiescent power. Therefore the total power dissipation PD = 0.216 + 0.008 + 0.012 = 0.236 W. (4) We know that the junction temperature is given by TJ = PD x JA + TA (5) Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 15 LM5111 SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 www.ti.com Thermal Considerations (continued) Or the rise in temperature is given by TRISE = TJ - TA = PD x JA (6) For SOIC package, JA is estimated as 170C/W for the conditions of natural convection. For MSOP-PowerPAD, JA is typically 60C/W. Therefore for SOIC TRISE is equal to TRISE = 0.236 x 170 = 40.1C (7) 11.3.2 Continuous Current Rating of LM5111 The LM5111 can deliver pulsed source/sink currents of 3 A and 5 A to capacitive loads. In applications requiring continuous load current (resistive or inductive loads), package power dissipation, limits the LM5111 current capability far below the 5-A sink and 3-A source capability. Rated continuous current can be estimated both when sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be calculated as: ISINK (MAX) := TJ(MAX) - TA TJA * RDS (ON) where * RDS(on) is the on resistance of lower MOSFET in the output stage of LM5111 (8) Consider TJ(max) of 125C and JA of 170C/W for an SO-8 package under the condition of natural convection and no air flow. If the ambient temperature (TA) is 60C, and the RDS(on) of the LM5111 output at TJ(max) is 2.5 , this equation yields ISINK(max) of 391 mA which is much smaller than 5-A peak pulsed currents. Similarly, the maximum continuous source current can be calculated as TJ(MAX) - TA ISOURCE (MAX) := TJA * VDIODE where * VDIODE is the voltage drop across hybrid output stage which varies over temperature and can be assumed to be about 1.1 V at TJ(max) of 125C (9) Assuming the same parameters as above, this equation yields ISOURCE(max) of 347 mA. 16 Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300H - JULY 2004 - REVISED SEPTEMBER 2016 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2004-2016, Texas Instruments Incorporated Product Folder Links: LM5111 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM5111-1M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5111 -1M LM5111-1MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5111 -1M LM5111-1MY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM SJKB LM5111-1MYX/NOPB ACTIVE HVSSOP DGN 8 3500 RoHS & Green SN Level-1-260C-UNLIM SJKB LM5111-2M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5111 -2M LM5111-2MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5111 -2M LM5111-2MY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM SJLB LM5111-2MYX/NOPB ACTIVE HVSSOP DGN 8 3500 RoHS & Green SN Level-1-260C-UNLIM SJLB LM5111-3MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM LM5111-4M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM LM5111-4MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM LM5111-4MY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5111 -3M 5111 -4M -40 to 125 5111 -4M SSYB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5111-1MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-1MY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-1MYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-2MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-2MY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-2MYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-3MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-4MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-4MY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5111-1MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5111-1MY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0 LM5111-1MYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0 LM5111-2MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5111-2MY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0 LM5111-2MYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0 LM5111-3MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5111-4MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5111-4MY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE TM DGN0008A PowerPAD VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 TYP 4.75 A 0.1 C SEATING PLANE PIN 1 INDEX AREA 6X 0.65 8 1 2X 3.1 2.9 NOTE 3 1.95 4 5 8X B 3.1 2.9 NOTE 4 0.38 0.25 0.13 C A B 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 2.0 1.7 9 1.1 MAX 8 1 0 -8 0.15 0.05 0.7 0.4 DETAIL A A 20 1.88 1.58 TYPICAL 4218836/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com EXAMPLE BOARD LAYOUT TM DGN0008A PowerPAD VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.88) SOLDER MASK DEFINED PAD SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) NOTE 9 SYMM 9 (2) (1.22) 6X (0.65) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.05 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4218836/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN TM DGN0008A PowerPAD VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.88) BASED ON 0.125 THICK STENCIL SYMM (R0.05) TYP 8X (1.4) 8X (0.45) 8 1 SYMM (2) BASED ON 0.125 THICK STENCIL 6X (0.65) 5 4 METAL COVERED BY SOLDER MASK (4.4) SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.15 0.175 2.10 X 2.24 1.88 X 2.00 (SHOWN) 1.72 X 1.83 1.59 X 1.69 4218836/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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