TL/F/10649
100370 Low Power Universal Demultiplexer/Decoder
June 1992
100370
Low Power Universal Demultiplexer/Decoder
General Description
The 100370 universal demultiplexer/decoder functions as
either a dual 1-of-4 decoder or as a single 1-of-8 decoder,
depending on the signal applied to the Mode Control (M)
input. In the dual mode, each half has a pair of active-LOW
Enable (E) inputs. Pin assignments for the E inputs are such
that in the 1-of-8 mode they can easily be tied together in
pairs to provide two active-LOW enables (E1a to E1b,E
2a to
E2b). Signals applied to auxiliary inputs Ha,H
band Hcdeter-
mine whether the outputs are active HIGH or active LOW. In
the dual 1-of-4 mode the Address inputs are A0a,A
1a and
A0b,A
1b with A2a unused (i.e., left open, tied to VEE or with
LOW signal applied). In the 1-of-8 mode, the Address inputs
are A0a,A
1a,A
2a with A0b and A1b LOW or open. All inputs
have 50 kXpulldown resistors.
Features
Y35% power reduction of the 100170
Y2000V ESD protection
YPin/function compatible with 100170
YVoltage compensated operating range eb
4.2V to
b5.7V
Logic Symbols
Single 1-of-8 Application
TL/F/10649–1
Dual 1-of-4 Application
TL/F/10649–4
Pin Names Description
Ana,A
nb Address Inputs
Ena,E
nb Enable Inputs
M Mode Control Input
HaZ0–Z3(Z0a–Z3a)
Polarity Select Input
HbZ4–Z7(Z0b–Z3b)
Polarity Select Input
HcCommon Polarity
Select Input
Z0–Z7Single 1-of-8
Data Outputs
Zna,Z
nb Dual 1-of-4
Data Outputs
Connection Diagrams
24-Pin DIP
TL/F/10649–2
28-Pin PCC
TL/F/10649–5
24-Pin Quad Cerpak
TL/F/10649–3
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Logic Diagram
Note: (Zn) for 1-of-4 applications. TL/F/10649–6
Truth Tables
Dual 1-of-4 Mode (M eA2a eHceLOW)
Inputs Active HIGH Outputs Active LOW Outputs
(Haand HbInputs HIGH) (Haand HbInputs LOW)
E1a E2a A1a A0a Z0a Z1a Z2a Z3a Z0a Z1a Z2a Z3a
E1b E2b A1b A0b Z0b Z1b Z2b Z3b Z0b Z1b Z2b Z3b
HXXXLLLLHHHH
XHXXLLLLHHHH
L L L LHLLL LHHH
L L L HLHLLHLHH
LLHLLLHLHHLH
L L H H L L LHHHH L
Single 1-of-8 Mode (M eHIGH; A0b eA1b eHaeHbeLOW)
Inputs Active HIGH Outputs*
(HcInput HIGH)
E1E2A2a A1a A0a Z0Z1Z2Z3Z4Z5Z6Z7
HX X X X LLLLLLLL
XH X X X LLLLLLLL
LL L L L HLLLLLLL
LL L L H LHLLLLLL
LL L H L LLHLLLLL
LL L H H LLLHLLLL
LL H L L LLLLHLLL
LL H L H LLLLLHLL
LL H H L LLLLLLHL
LL H H H LLLLLLLH
H
e
HIGH Voltage Level
LeLOW Voltage Level
XeDon’t Care
*for HceLOW, output states are complemented
E1eE1a and E1b wired; E2eE22a and E2b wired
2
Absolute Maximum Ratings
Above which the useful life may be impaired. (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature (TSTG)b65§Ctoa
150§C
Maximum Junction Temperature (TJ)
Ceramic a175§C
Plastic a150§C
VEE Pin Potential to Ground Pin b7.0V to a0.5V
Input Voltage (DC) VEE to a0.5V
Output Current (DC Output HIGH) b50 mA
ESD (Note 2) t2000V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Recommended Operating
Conditions
Case Temperature (TC)
Commercial 0§Ctoa
85§C
Industrial b40§Ctoa
85§C
Military b55§Ctoa
125§C
Supply Voltage (VEE)b5.7V to b4.2V
Commercial Version
DC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND, TCe0§Ctoa
85§C (Note 3)
Symbol Parameter Min Typ Max Units Conditions
VOH Output HIGH Voltage b1025 b955 b870 mV VIN eVIH (Max) Loading with
VOL Output LOW Voltage b1830 b1705 b1620 mV or VIL (Min) 50Xto b2.0V
VOHC Output HIGH Voltage b1035 mV VIN eVIH (Min) Loading with
VOLC Output LOW Voltage b1610 mV or VIL (Max) 50Xto b2.0V
VIH Input HIGH Voltage b1165 b870 mV Guaranteed HIGH Signal for All Inputs
VIL Input LOW Voltage b1830 b1475 mV Guaranteed LOW Signal for All Inputs
IIL Input LOW Current 0.50 mAV
IN eVIL (Min)
IIH Input HIGH Current 240 mAV
IN eVIH (Max)
IEE Power Supply Current b95 b50 mA Inputs Open
Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise
immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to
guarantee operation under ‘‘worst case’’ conditions.
3
Commercial Version (Continued)
Ceramic Dual-In-Line Package AC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND
Symbol Parameter TCe0§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
tPLH Propagation Delay 0.75 1.85 0.75 1.85 0.85 2.05 ns
tPHL Ena,E
nb to Output
tPLH Propagation Delay 0.75 2.20 0.75 2.20 0.75 2.30 ns
tPHL Ana,A
nb to Output
tPLH Propagation Delay 0.75 2.20 0.75 2.20 0.75 2.20 ns
Figures 1
and
2
tPHL Ha,H
b
,H
cto Output
tPLH Propagation Delay 1.10 2.70 1.10 2.70 1.10 3.00 ns
tPHL M to Output
tTLH Transition Time 0.40 1.30 0.40 1.30 0.40 1.30 ns
tTHL 20% to 80%, 80% to 20%
PCC and Cerpak AC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND
Symbol Parameter TCe0§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
tPLH Propagation Delay 0.75 1.65 0.75 1.65 0.85 1.85 ns
tPHL Ena,E
nb to Output
tPLH Propagation Delay 0.75 2.00 0.75 2.00 0.75 2.10 ns
tPHL Ana,A
nb to Output
tPLH Propagation Delay 0.75 2.00 0.75 2.00 0.75 2.00 ns
Figures 1
and
2
tPHL Ha,H
b
,H
cto Output
tPLH Propagation Delay 1.10 2.50 1.10 2.50 1.10 2.80 ns
tPHL M to Output
tTLH Transition Time 0.40 1.20 0.40 1.20 0.40 1.20 ns
tTHL 20% to 80%, 80% to 20%
4
Industrial Version
PCC DC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND, TCeb
40§Ctoa
85§C (Note 3)
Symbol Parameter TCeb
40§CT
C
e
0
§
Ctoa
85§CUnits Conditions
Min Typ Min Max
VOH Output HIGH Voltage b1085 b870 b1025 b870 mV VIN eVIH (Max) Loading with
VOL Output LOW Voltage b1830 b1575 b1830 b1620 mV or VIL (Min) 50Xto b2.0V
VOHC Output HIGH Voltage b1095 b1035 mV VIN eVIH (Min) Loading with
VOLC Output LOW Voltage b1565 b1610 mV or VIL (Max) 50Xto b2.0V
VIH Input HIGH Voltage b1170 b870 b1165 b870 mV Guaranteed HIGH Signal
for All Inputs
VIL Input LOW Voltage b1830 b1480 b1830 b1475 mV Guaranteed LOW Signal
for All Inputs
IIL Input LOW Current 0.50 0.50 mAV
IN eVIL (Min)
IIH Input HIGH Current 300 240 mAV
IN eVIH (Max)
IEE Power Supply Current b95 b50 b95 b50 mA Inputs Open
Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise
immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to
guarantee operation under ‘‘worst case’’ conditions.
PCC AC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND
Symbol Parameter TCeb
40§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
tPLH Propagation Delay 0.75 1.65 0.75 1.65 0.85 1.85 ns
tPHL Ena,E
nb to Output
tPLH Propagation Delay 0.65 2.00 0.75 2.00 0.75 2.10 ns
tPHL Ana,A
nb to Output
tPLH Propagation Delay 0.70 2.00 0.75 2.00 0.75 2.00 ns
Figures 1
and
2
tPHL Ha,H
b
,H
cto Output
tPLH Propagation Delay 1.10 2.50 1.10 2.50 1.10 2.80 ns
tPHL M to Output
tTLH Transition Time 0.40 1.30 0.40 1.20 0.40 1.20 ns
tTHL 20% to 80%, 80% to 20%
5
Military VersionÐPreliminary
DC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND, TCeb
55§Ctoa
125§C
Symbol Parameter Min Max Units TCConditions Notes
b1025 b870 mV 0§Cto
V
OH Output HIGH Voltage a125§C
b1085 b870 mV b55§CV
IN eVIH (Max) Loading with 1, 2, 3
b1830 b1620 mV 0§Cto or VIL (Min) 50Xto b2.0V
VOL Output LOW Voltage a125§C
b1830 b1555 mV b55§C
b1035 mV 0§Cto
V
OHC Output HIGH Voltage a125§C
b1085 mV b55§CV
IN eVIH (Min) Loading with 1, 2, 3
b1610 mV 0§Cto or VIL (Max) 50Xto b2.0V
VOLC Output LOW Voltage a125§C
b1555 mV b55§C
VIH Input HIGH Voltage b1165 b870 mV b55§C to Guaranteed HIGH Signal for 1, 2, 3, 4
a125§C All Inputs
VIL Input LOW Voltage b1830 b1475 mV b55§C to Guaranteed LOW Signal for 1, 2, 3, 4
a125§C All Inputs
IIL Input LOW Current 0.50 mAb55§Cto V
EE eb
4.2V 1, 2, 3
a125§CV
IN eVIL (Min)
IIH Input HIGH Current
Hc,A
0a,A
1a,A
2a 310 mA0§Cto
All Others 250 a125§C
VEE eb
5.7V 1, 2, 3
Hc,A
0a,A
1a,A
2a 465 mAb55§CVIN eVIH (Max)
All Others 350
IEE Power Supply Current b110 b70 mA b55§Cto Inputs Open 1, 2, 3
a125§C
Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C, then testing immedi-
ately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be considered a
worst case condition at cold temperatures.
Note 2: Screen tested 100% on each device at b55§C, a25§C, and a125§C, Subgroups 1, 2, 3, 7, and 8.
Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b55§C, a25§C, and a125§C, Subgroups A1, 2, 3, 7, and 8.
Note 4: Guaranteed by applying specific input condition and testing VOH/VOL.
6
Military VersionÐPreliminary (Continued)
AC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND
Symbol Parameter TCeb
55§CT
C
ea
25§CT
C
ea
125§CUnits Conditions Notes
Min Max Min Max Min Max
tPLH Propagation Delay 0.90 2.30 0.90 2.20 0.90 2.30 ns
tPHL Ena,E
nb to Output
tPLH Propagation Delay 1.00 2.80 1.00 2.70 1.00 2.90 ns
tPHL Ana,A
nb to Output 1, 2, 3
tPLH Propagation Delay 1.00 3.00 1.00 2.90 1.00 3.00 ns
Figures 1
and
2
tPHL Ha,H
b
,H
cto Output
tPLH Propagation Delay 1.50 3.90 1.60 3.80 1.60 3.90 ns
tPHL M to Output
tTLH Transition Time 0.45 1.70 0.45 1.70 0.45 1.80 ns 4
tTHL 20% to 80%, 80% to 20%
Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing
immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be
considered a worst case condition at cold temperatures.
Note 2: Screen tested 100% on each device at a25§C, temperature only, Subgroup A9.
Note 3: Sample tested (Method 5005, Table I) on each Mfg. lot at a25§C, Subgroup A9, and at a125§C, and b55§C Temp., Subgroups A10 and A11.
Note 4: Not tested at a25§C, a125§C and b55§C Temperature (design characterization data).
Test Circuit
TL/F/10649–7
FIGURE 1. AC Test Circuit
Notes:
VCC,V
CCA ea
2V, VEE eb
2.5V
L1 and L2 eequal length 50Ximpedance lines
RTe50Xterminator internal to scope
Decoupling 0.1 mF from GND to VCC and VEE
All unused outputs are loaded with 50Xto GND
CLeFixture and stray capacitance s3pF
Pin numbers shown are for flatpak; for DIP see logic symbol
7
Switching Waveforms
TL/F/10649–8
FIGURE 2. Propagation Delay and Transition Times
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
100370 D C QB
Device Number (basic) Special Variations
QB eMilitary grade device with
Package Code enivronmental and burn-in
DeCeramic DIP processing
FeQuad Cerpak
QePlastic Leaded Chip Carrier (PCC) Temperature Range
CeCommercial (0§Ctoa
85§C)
IeIndustrial (b40§Ctoa
85§C)
(PCC Only)
MeMilitary (b55§Ctoa
125§C)
8
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J24E
28-Lead Plastic Chip Carrier (Q)
NS Package Number V28A
9
Physical Dimensions inches (millimeters) (Continued)
24-Lead Ceramic Flatpak (F)
NS Package Number W24B
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failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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