es f\ | | Features * 1.0 Drawn Gate Length High-performance CMOS Gate Arrays * All ATL Gate Arrays are Specifled from 3.0 Volts to 5.5 Volts, for Standard and Low Voltage Applications Design Translation of Existing ASIC Designs Provide for Easy Alternate Sourcing with Equivalent or Improved Per*ormance * EPLD/FPGA Conversions to ATL Gate Array, Severai EPLD and FPGA can be Combined Into a Single Gate Array. * ATL C Version, Fine Pad Pitch Gate Arrays are ideal for High V/O, Low Gate Count Designs (Commercial, industrial Only) * ATL Gate Arrays can be Suppiled Compliant to MIL-STD-883 * Improved Product Testability Using Serial Scan, Boundary Scan, JTAG and Bullt-in-self-test Description The high-performance ATL Series CMOS gate arrays employ 1.0 p1-drawn, double- level metal, Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced manufacturing facility. The arrays utilize an enhanced channelless architecture which results in greater than 50 percent usable gates. Atmel's flexible design system uses industry design standards and is compatible with popular CAD/CAE software and hardware packages. The customer can Start designing with the ATL series today using existing CAD/CAE tools. AINET ATL Series Gate Arrays ATL4 ATL10 ATL20 ATL40 ATL60 ATL75 ATL100 ATL130 ATL160 ATL7C ATL10C ATL15C ATL20C ATL35C ATL55C ATL75C 8-3AMES ATL Array Organization Device Maximum Routable Max Pin Max 1/011) Gatel2) Number Gates Gates Count Pins Speed ATL4 4,100 2,600 68 60 375 ps ATL10 10,000 6,500 124 116 375 ps ATL20 22,000 12,000 144 136 375 ps ATL40 40,000 22,000 180 168 375 ps ATL60 57,000 30,000 224 208 375 ps ATL75 72,000 38,000 256 236 375 ps ATL100 95,000 50,000 292 262 375 ps ATL130 131,000 67,000 338 308 375 ps ATL160 157,000 80,000 360 320 375 ps ATL C Array Organization - Fine Pad Pitch Device Maximum Routable Max Pin Max VO(1) Gate(2) Number Gates Gates Count Pins Speed ATL7C 7,000 4,000 100 92 375 ps ATLi0C 10,000 6,000 120 112 375 ps ATL15C 15,000 8,000 144 136 375 ps ATL20C 22,000 12,000 160 152 375 ps ATL35C 35,000 18,000 208 192 375 ps ATL55C 55,000 29,000 256 236 375 ps ATL75C 75,000 39,000 304 280 375 ps Notes: 1. Absolute maximum VO pins is maximum pin count minus 8. Additional power and ground pins are assumed to be required to support simultaneous switching outputs as pin count increases. 2. Nominal 2 input nand gate with a fan out of 2 ATL Design Design Systems Supported Atmel supports the major CAE/CAD software systems with complete macro cell libraries (symbols, timing and function), as well as utilities for checking the netlist and accurate pre-route delay simulations. Atmel uses Cadences Verilog-XL as our golden simulator. The following design systems are supported: Cadence Valid Mentor Dazix Racal-Redac Viewlogic Synopsys Design Flow While Atmel provides four options for implementing a gate array design, they all have the same flow. Data base acceptance is the first milestone. This is when Atmel receives and accepts the complete design data base. Preliminary design review is where the performance of the design is set based on the Cadence simulation. Final design review is the last review of the design before making masks. The back annotation data is incorporated into the simulations. After final design review masks are released and prototypes in ceramic packages are delivered. 8-4 ATL eeses f\ | 1 ATL Gate Array Design Flow Customer e] Amol co Dect synese FPGAIEPLD fe Atmel Atmel and Verification Atmel ee Customer > . . Atmei Prvetend vertcaton Atmel Customer > _ Atmel Customer ~_} Prototype Delivery t- Atmel Design Options Schematic Capture Schematic capture and simulation are performed by the customer using an Atmel supplied macro cell library. The customer can also receive complete back annotation delay data for post-route simulation. VHDL Verilog-HDL Atmel can accept Register Transfer level (RTL) designs for VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDL format. Atmel fully supports Synopsys for VHDL simula- tion as well as synthesis. Design via VHDL or Verilog- HDL is the preferred method of performing a gate array design. ASIC Design Translation Atmel has successfully translated dozens of existing de- signs from most major ASIC vendors (LSI Logic, Oki, NEC, Fujitsu and others) into our ATL series gate arrays. These designs have been optimized for speed, gate count, modified to add logic or memory, or replicated for a pin- for-pin compatible, drop-in replacement. FPGA and EPLD Conversions Atmel has successfully translated existing FPGA/EPLD designs from most major vendors (Xilinx, Actel, Altera, AMD & Atmel) into our ATL series gate arrays. The design can be optimized for speed or power consumption, modified to add logic or memory or replicated fora pin-for- pin compatible, drop-in replacement. Atmel frequently combines several devices onto a single gate array. &5ATL Series Celi Library Atmels ATL series gate arrays use cells from an accurately modeled and highly flexible library. The cell library contains over 120 hard-wired data path elements and has been characterized via extensive SPICE modeling at the transistor level and verified through measurements made on fabricated test arrays. Characterization has been performed over the military temperature and voltage ranges, to ensure that the simulation accurately predicts the performance of the finished product. Atmel is continually expanding the ATL series cell library with both soft and hard macros. Check with your sales representative for the most recent additions. Cell Guide Buffers and inverters 1x Buffer 1x Inverter 2x Buffer Dual 1x Inverter 2x Buffer with Enable Quad 1x Inverter 2x Buffer with Enable Low Quad Tri-state Inverter 3x Buffer 2x Inverter 4x Buffer Dual 2x inverter 8x Buffer 2x Tri-state inverter 12x Buffer 3x Inverter 16x Buffer - 4x Inverter Delay Buffer 2.0 ns &x Inverter Delay Buffer 3.5 ns 10x Inverter Delay Buffer 8.0 ns AND, NAND, OR, NOR Gates 2 input AND 2 input NOR 2 input AND with High Drive Dual 2 input NOR 3 input AND 2 input NOR with High Drive 3 input AND with High Drive 3 input NOR 4 input AND 3 input NOR with High Drive 4 input AND with High Drive 4 input NOR 5 input AND 4 input NOR with High Drive 2 input NAND 5 input NOR Dual 2-input NAND 8 input NOR 2 input NAND with High Drive 16 input NOR with High Drive 3 input NAND 2 input OR 3 input NAND with High Drive 2 input OR with High Drive 4 input NAND 3 input OR 4 input NAND with High Drive 3 input OR with High Drive 5 input NAND 4 input OR 5 input NAND with High Drive 4 input OR with High Drive 6 input NAND 6 input NAND with High Drive 8 input NAND 8 input NAND with High Drive 8-6 AV qsCell Guide Multiplexers 2:1 MUX 2:1 MUX with High Drive inverting 2:1 MUX w/o Buffered inputs inverting 2:1 MUX w/o Buffered Inputs, High Drive 2:1 MUX with Enable Low Quad 2:1 MUX with Enable Quad 2:1 MUX Inverting 3:1 MUX w/o Buffered Inputs Inverting 3:1 MUX w/o Buffered Inputs, High Drive 4:1 MUX 4:1 MUX w/o Buffered Inputs 4:1 MUX w/o Buffered inputs, High Drive 5:1 MUX with High Drive 8:1 MUX 8:1 MUX with Enable Low 8:1 MUX High Drive AND/OR, OR/AND Gates 3 input AND OR INVERT 3 input AND OR INVERT with High Drive 4 input AND OR INVERT 4 input AND OR INVERT with High Drive 6 input AND OR INVERT 6 input AND OR INVERT with High Drive 3 input OR AND INVERT 3 input OR AND INVERT with High Drive 4 input OR AND INVERT 4 input OR AND INVERT with High Drive 8 input OR AND INVERT 4 input OR AND INVERT with 2 inputs to AND Exclusive OR/NOR Gates 1 bit Adder 1 bit Adder with Buffered Outputs 7 input Carry Lookahead 2 input Exclusive OR 2 input Exclusive OR with High Drive 2 input Exclusive NOR 2 input Exclusive NOR with High Drive Decoders 2:4 Decoder 3:8 Decoder with Low Enable 2:4 Decoder with Low Enable Flip-flops/Latches D Flip-flop LATCH D Flip-flop with Clear/Preset D Flip-flop with Clear D Flip-flop with High Drive D Flip-flop with Reset D Flip-flop with Set D Flip-flop with Set/Reset JK Flip-flop JK Flip-flop with Clear/Preset JK Flip-flop with Clear LATCH with Complementary Outputs LATCH with Inverted Gate Signal QUAD LATBG with Common Gate Signal LATCH with High Drive QUAD Inverting LATCH LATCH with Reset LATCH with Set LATCH with Set and Reset F 8-7AE} Cell Guide Scan Cells Set-scan Register Set-scan Register with Set Set-scan Register with Clear and Preset Set-scan Register with Set and Reset Set-scan Register with Reset VO Options Input, Output, Bidirectional, Tristate Output, Internal Clock Driver and Oscillator Output Drive Value Programmable from 2 mA to 24 mA in 2 mA increments with Slew Rate Control GMOS or TTL Operation Schmitt Trigger (Bidirectional, Input) Testable NAND Gate on input (Bidirectional, Input) inverting and Non-inverting Input Buffers (Bidirectional, Input) Pullup Resistor - 10K Q to 310K Q Pulldown Resistor - 3.5K Q to 108.5K Q 74XX Series Soft Macros 24 cells available HDL Macros - Available In Verilog-HDL or VHDL Simulation Models Function Group Available Celis adder 37 alu 29 baud rate generator 3 comparator 18 counter 27 fifo 56 incrementor/decrementor 60 mux 7 Parity/error correction 15 scan 31 shifter 9 multipliers 10 8-8 A eeCMOS/TTL Input Interface Characteristics Interface Logic High Logic Low Switchpoint CMOS 3.5 V Minimum 1.5 V Maximum Vaq/2 Typical TTL 2.0 V Minimum 0.8 V Maximum 1.4 V Typicai Absolute Maximum Ratings* Operating Temperature ............ -55C to +125C Storage Temperature ..............0e0 -65C to +150C Voltage on Any Pin with Respect to Ground ........0.....0. -2.0 Vto +7.0 Vi Maximum Operating Voltage .............ccsceseeneees 6.0V 5.0 Volt DC Characteristics *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: 1. Minimum voltage is -0.6 V de which may undershoot to -2.0 V for pulses of less than 20 ns. Maximum output pin voltage is Vag + 0.75 V de which may overshoot to +7.0 V for pulses of less than 20 ns. Applicable over recommended operating range from Ty = -55C to +125C, Vag = 4.5 V to 5.5 V (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units lig Input Leakage High Vin = Vda, Vag = 5.5 V 01 10 pA Iie Input Leakage Low (no pull-up) Vin = Vss, Vag = 5.5 V -10 .01 pA 40K pull-up Vin = Vss, Veg = 5.5 V -325 -160 -40 pA loz Output Leakage (no puil-up) Vin = Vag oF Vss, Vag = 5.5 V -10 O01 10 pA los Output Short Circuit Current Vad = 5.5 V, Vout = Vag 10 50 100 mA (3 x Buffer)@) Vad =5.5V, Vour=Vss --100 -50 -10 mA Vir TTL Input Low Voltage 0.8 Vv Vit CMOS input Low Voltage 0.3 x Vag Vv Vin TTL Input High Voltage 2.0 Vv Vin CMOS Input High Voltage 0.7 x Vag Vv Vr TTL Switching Threshold Vag = 5.0 V, 25C 1.4 Vv CMOS Switching Threshoid Vad = 5.0 V, 25C 2.4 Vv Vor Output Low Voltage lou = as rated 0.2 0.4 Vv Output buffer has Vag = 4.5 V 12 stages of drive capability with 2 mA Io, per stage. Vou Output High Voltage loH = as rated 0.7xVag 4.2 Vv Output buffer has Vag = 4.5 V 12 stages of drive capability with -2 mA Ioy per stage. Note: 2. This is the specification for the 3 x Output Buffer. Output short circuit current for other outputs will scale accordingly. Not more than one output shorted at a time, for a maximum of one second, is allowed. AIMED 8-9ie 3.3 Volt DC Characteristics Applicable over recommended operating range from Tg = -55C to +125C, Vgg = 3.0 V to 3.6 V (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units hin Input Leakage High Vin = Vag, Vad = 3.6 V 01 10 pA lit Input Leakage Low (no pull-up) Vin = Vss, Vag = 3.6 V -10 .01 pA 40K pull-up Vin = Vss, Vdd = 3.6 V -200 =-60 -10 pA loz Output Leakage (no pull-up) Vin = Vag or Vss, Vag = 3.6 V -10 01 10 pA los Output Short Circuit Current Vag = 3.6 V, Vout = Vad 5 25 60 mA (3 x Buffer)@ Vag = 3.6 V. Vout = Vss -60 -25 5 mA Vit CMOS Input Low Voltage 0.3 x Vag Vv Vin CMOS Input High Voltage 0.7 x Vag Vv Vr CMOS Switching Threshold Vad = 3.3 V, 25C 15 Vv VoL Output Low Voltage lo_ = as rated 0.4 Vv Output buffer has Vag = 3.0 V 12 stages of drive capability with 1 mA Io: per stage. Vou Output High Voltage lon = as rated 0.7 x Vag Vv Output buffer has Vag = 3.0 V 12 stages of drive capability with -1 MA lox per stage. Note: 2. This is the specification for the 3 x Output Buffer. Output short circuit current for other outputs will scale accordingly. Not more than one output shorted at a time, for a maximum of one second, is allowed. VO Buffer DC Characteristics Symbol Parameter Test Condition Min Typ Max Units Cin Capacitance Input Buffer (Die) .0V,3.3V 2.4 pF Cout Capacitance Output Buffer (Die) .0V,3.3V 5.6 pF Cyo Capacitance Bi-Directional 5.0V,3.3V 6.6 pF Schmitt Trigger V+ TTL Positive Threshold 25C, 5.0 V 1.8 2.0 Vv CMOS Positive Threshold 25C, 5.0 V 3.2 3.5 Vv V- TTL Negative Threshold 26C, 5.0 V 0.6 0.8 Vv CMOS Negative Threshold 25C, 5.0 V 1.0 1.2 Vv AV TTL Hysteresis 26C, 5.0 V 0.4 1.0 CMOS Hysteresis 25C, 5.0 V 1.0 2.0 V+ CMOS Positive Threshoid 25C, 3.3 V 2.2 2.3 Vv V- CMOS Negative Threshold 25C, 3.3 V 65 0.9 Vv AV CMOS Hystersis 25C, 3.3 V 65 1.3 /O Buffers * Programmable output drive The ATL series input/output ring contains the I/O buffer (2 to 24 mA Io, -2 to -24 mA Ion for 5.0 V circuitry capable of sourcing and sinking currents up to 1to 12 MAI 91, -1 to -12 mA Iog for 3.3 V) 24 mA, and responds to CMOS or TTL logic levels. I/O * 3000 volts ESD protection * Built-in configurable test logic 8-10 locations on this ring can accommodate bidirectional cells. AVL cj _AC Characteristics Delay vs Vag Delay vs Fanout 700 5 2 600 aS 5 ez 5004 P= = 7 2 q 2 , : 400 1 ~ 5 ' 1 L a eae : | o J A 200 = a 4 3 05 | rere 400 4 ] oo 04 ol 30 33 36 45 50 55 3 4 3 16 Volts Fanout = 3.3 Volts Vag + 3.3 Volts Vag ~@ 5.0 Volts Vag ~@ 5.0 Volts Vag NAND2 - 2 input NAND NAND2 - 2 input NAND Temp = 25C Temp = 25C FO 2 Delay vs Temperature Output Buffer vs Load 800 7 ; 700 64 & 600 o 4 / > & 57 & 500 > 3 8 3 7 / oy g 400 a 45 A V4 a 4 L 300 37 74 200 24 400 4 a 1 = 0 J -55 25 125 0-4 10 25 50 100 Temperature (C) 3.3 Voks V Capacitive Load (pF) x ons = a + 3.3 Volts Vag 5.0 Volts V, -@ 5.0 Volts Vag NAND2 - 2 input NAND FO=2 PDO4 - Output Buffer 8 mA Temp = 25C ee ANMEL 611AIMEL Design for Testability. Atmel supports a full range of Design-for-Test improve- ment techniques which reduce design and prototype debug time, production test time, and board & system test time. These techniques can also improve system level test and diagnostic capability. The ATL arrays support the Joint Test Action Group GTAG) boundary scan architecture. The required soft and hard macros to implement IEEE 1149.1 compliant architec- ture are available in our macro cell library. Use of JTAG allows for scan testing with only 4-5 additional pins re- quired. Atmel can also provide automatic high fault coverage test pattern generation (ATPG) via Synopsys Test Compiler. By following a set of design rules, Test Compiler can automatically insert the scan cells and generate test vectors providing greater than 95% fault coverage. This is the easiest and least expensive method for designing testability into a gate array design. Advanced Packaging Atmel supports a wide variety of standard packages for the ATL series, but also offers its ATL series gate arrays in packages that are custom designed to maintain the performance obtained in the silicon. All of Atmel's standard packages have been characterized for thermal and electrical performance. When a standard package cant meet a customer's needs, Atmel's package design center can develop a package to precisely fit the application. The company has delivered custom-designed packages in a wide variety of configurations, including multichip modules and Tape Automated Bonding (TAB) packages. Atmel's domestic packaging facility manufactures commercial, industrial, Class B and modified Class S level product. Packaging Options Package Type Pin Count TOFP 44, 48, 64, 80, 100, 144, 160, 208, 240, 248, 304 POQFP 44, 64, 68, 80, 100, 120, 128, 132, 136, 144, 160, 184, 208, 232, 256, 304 PLCC 28, 44, 68, 84 PPGA 68, 84, 100, 120, 132, 144, 180, 224 CPGA 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 256, 299, 391 COFP 64, 68, 84, 132, 160, 224, 340 cLec 44, 52, 84, 132, 148, 196 TAB 68, 100, 120, 128, 144, 160, 180, 208, 224, 256, 292, 304, 338, 360 8-12 AD EiATL Military Product Flow Chart MIL-STD-883 Class B Water Fabrication Wafer Sort Electrical Test Saw, Die Attach and Wire Boad yo internal Visual Mathod 2010 *Y SPC, QC Monitors Condition 8 Mechanical Tests Method 2011 ead Method 2019 Seal and Topside Mark Enviroameats! Preconditioning Temperature Cycling Mothod 1010 Condition C Constant Acceleration Mathod 2001 Condition E Fine and Gross Loak Mothod 1014 Pre Bura-ia Electrical Screeniag ' a On ) | 100% Final Electrical Scrooniag PDA=5% at 425C 55C, 125C 100% Extereal Visual Mathod 2009 Group A sad B Inspoction Method 5005 Review Groups C aad D Quality Conformance Inspection Documentation OA Pre-Ship Inspection Actel, Altera, AMD, Cadence, DAZIX, Fujitsu, LSI Logic, Mentor, NEC, Oki, Racal-Redac, Synopsys, Valid, Verilog-XL, Viewlogic, and Xilinx may be registered trademarks of others. AIMEL o138-14