SEMICONDUCTOR
4-69
Features
• Advanced 0.8 micron CMOS Technology
• Pin Compatible With Bipolar FAST™ Series at a
Higher Speed and Lower Power Consumption
•25Ω Series Resistor on All Outputs
(CD74FCT2374T, CD74FCT2574T only)
• TTL Input and Output Levels
• Low Ground Bounce Outputs
• Extremely Low Static Power
• Hysteresis on All Inputs
Description
These devices are 8-bit wide octal registers designed with
eight D-type flip-flops with a buffered common clock and
buffered three-state outputs. When output enable (OE) is
LOW, the outputs are enabled. When OE is HIGH, the out-
puts are in the high impedance state. Input data meeting the
setup and hold time requirements of the D inputs is trans-
ferred to the O outputs on the LOW-to-HIGH transition of the
clock input.
All CD74FCT2574T devices have a built-in 25Ω series resis-
tor on all outputs to reduce noise due to reflections, thus
eliminating the need for an external terminating resistor.
Ordering Information
PART NUMBER
TEMP.
RANGE
(oC) PACKAGE PKG.
NO.
CD74FCT374ATM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT374ATQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT374CTM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT374CTQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT374DTM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT374DTQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT374TM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT374TQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT534ATM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT534ATQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT534CTM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT534CTQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT534DTM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT534DTQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT534TM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT534TQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT574ATM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT574ATQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT574CTM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT574CTQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT574DTM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT574DTQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT574TM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT574TQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT2374ATM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT2374ATQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT2374CTM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT2374CTQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT2374TM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT2374TQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT2574ATM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT2574ATQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT2574CTM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT2574CTQM -40 to 85 20 Ld QSOP M20.15-P
CD74FCT2574TM -40 to 85 20 Ld SOIC M20.3-P
CD74FCT2574TQM -40 to 85 20 Ld QSOP M20.15-P
NO TE: When ordering, use the entire part number . Add the suffix 96
to obtain the variant in the tape and reel.
December 1996
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996
CD74FCT374T, CD74FCT534T,
CD74FCT574T, CD74FCT2374T,
CD74FCT2574T
Fast CMOS Octal D Registers (Three-State)
File Number 4171.2
4-70
Pinouts
Functional Block Diagrams
CD74FCT374T, CD74FCT2374T, CD74FCT574, CD74FCT2574T
CD74FCT534T
CD74FCT374T, CD74FCT2374T
(QSOP, SOIC)
TOP VIEW
CD74FCT534T
(QSOP, SOIC)
TOP VIEW
CD74FCT574T, CD74FCT2574T
(QSOP, SOIC)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
O0
D0
D1
O1
O2
D3
D2
O3
GND
VCC
D7
D6
O6
O7
O5
D5
D4
O4
CP 11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
O0
D0
D1
O1
O2
D3
D2
O3
GND
VCC
D7
D6
O6
O7
O5
D5
D4
O4
CP 11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
VCC
O1
O2
O3
O0
O4
O5
O6
O7
CP
O0
D0
CP
OE
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
O0
D0
CP
OE
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
DQDQDQDQDQDQDQDQ
CP CP CP CP CP CP CP CP
CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T
4-71
TRUTH TABLE (NOTE 1)
FUNCTION
INPUTS OUTPUTS INTERNAL
OE CP DNONQN
CD74FCT534T
High-Z H L X Z NC
HHXZNC
Load Register L ↑LHL
L↑HLH
H↑LZL
H↑HZH
CD74FCT374T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T
FUNCTION OE CP DNONQN
High-Z H L X Z NC
HHXZNC
Load Register L ↑LLH
L↑HHL
H↑LZH
H↑HZL
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance
NC = No Change
↑ = LOW-to-HIGH Transition
Pin Descriptions
PIN NAME DESCRIPTION
OE Output Enable Input (Active LOW)
CP Clock Pulse for the register. Enters data on
LOW-to-HIGH transition
D0-D7Data Inputs
O0-O7Three-State Outputs (True)
O0-O7Three-State Outputs (Inverted)
GND Ground
VCC Power
CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T
4-72
Absolute Maximum Ratings Thermal Information
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120mA
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage to Ground Potential
Inputs and VCC Only . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Supply Voltage to Ground Potential
Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Thermal Resistance (Typical, Note 2) θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYMBOL (NOTE 3)
TEST CONDITIONS MIN (NOTE 4)
TYP MAX UNITS
DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40oC to 85oC, VCC = 5.0V ±5%
Output HIGH Voltage VOH VCC = Min, VIN = VIH or VIL IOH = -15.0mA 2.4 3.0 - V
Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 64mA - 0.3 0.50 V
Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 12mA
(25Ω Series) - 0.3 0.50 V
Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 - - V
Input LOW Voltage VIL Guaranteed Logic LOW Level - - 0.8 V
Input HIGH Current IIH VCC = Max VIN = VCC --1µA
Input LOW Current IIL VCC = Max VIN = GND - - -1 µA
High Impedance
Output Current IOZH VCC = Max VOUT = 2.7V - - 1 µA
IOZL VOUT = 0.5V - - -1 µA
Clamp Diode Voltage VIK VCC = Min, IIN = -18mA - -0.7 -1.2 V
Short Circuit Current IOS VCC = Max (Note 5),
VOUT = GND -60 -120 - mA
Power Down Disable IOFF VCC = GND, VOUT = 4.5V - - 100 µA
Input Hysteresis VH- 200 - mV
CAPACITANCE TA = 25oC, f = 1MHz
Input Capacitance
(Note 6) CIN VIN = 0V - 6 10 pF
Output Capacitance
(Note 6) COUT VOUT = 0V - 8 12 pF
POWER SUPPLY SPECIFICATIONS
Quiescent Power
Supply Current ICC VCC = Max VIN = GND or VCC - 0.1 500 µA
Supply Current per
Input at TTL HIGH ∆ICC VCC = Max VIN = 3.4V
(Note 7) - 0.5 2.0 mA
Supply Current per
Input per MHz
(Note 8)
ICCD VCC = Max, Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND - 0.15 0.25 mA/
MHz
Total Power Supply
Current (Note 10) ICVCC = Max, Outputs Open
fCP = 10MHz, 50% Duty Cycle
OE = GND
fI = 5MHz, One Bit toggling
VIN = VCC
VIN = GND - 1.5 3.5
(Note 9) mA
VIN = 3.4V
VIN = GND - 2.0 5.5
(Note 9) mA
VCC = Max, Outputs Open
fCP = 10MHz, 50% Duty Cycle
OE = GND
fI = 2.5MHz, Eight Bits toggling
VIN = VCC
VIN = GND - 3.5 7.3
(Note 9) mA
VIN = 3.4V
VIN = GND - 6.0 16.3
(Note 9) mA
CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T
4-73
Switching Specifications Over Operating Range
PARAMETER SYMBOL
(NOTE 11)
TEST
CONDITIONS
T ATCTDT
UNITS
(NOTE 12)
MIN MAX (NOTE 12)
MIN MAX (NOTE 12)
MIN MAX (NOTE 12)
MIN MAX
CD74FCT374T, CD74FCT534T, CD74FCT2374T
Propagation Delay
CP to ONtPLH,
tPHL CL = 50pF
RL = 500Ω2.0 10.0 2.0 6.5 2.0 5.2 2.0 4.5 ns
Output Enable Time
OE to ONtPZH,
tPZL 1.5 12.5 1.5 6.5 1.5 5.5 1.5 5.5 ns
Output Disable Time
(Note 13)
OE to ON
tPHZ,
tPLZ 1.5 8.0 1.5 5.5 1.5 5.0 1.5 5.0 ns
Setup Time HIGH or
LOW, DN to CP tSU 2.0 - 2.0 - 2.0 - 2.0 - ns
Hold Time HIGH or
LOW, DN to CP tH1.5 - 1.5 - 1.5 - 1.0 - ns
CP Pulse Width
(Note 13)
HIGH or LOW
tW7.0 - 5.0 - 5.0 - 3.0 - ns
CD74FCT574T, CD74FCT2574T
Propagation Delay
CP to ONtPLH,
tPHL CL = 50pF
RL = 500Ω2.0 8.5 2.0 6.5 2.0 5.2 2.0 4.5 ns
Output Enable Time
OE to ONtPZH,
tPZL 1.5 10.0 1.5 6.5 1.5 5.5 1.5 5.5 ns
Output Disable Time
(Note 13)
OE to ON
tPHZ,
tPLZ 1.5 6.5 1.5 5.5 1.5 5.0 1.5 5.0 ns
Setup Time HIGH or
LOW, DN to CP tSU 2.0 - 2.0 - 2.0 - 2.0 - ns
Hold Time HIGH or
LOW, DN to CP tH1.5 - 1.5 - 1.5 - 1.0 - ns
CP Pulse Width
(Note 13)
HIGH or LOW
tW7.0 - 5.0 - 5.0 - 3.0 - ns
NOTES:
3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.
4. Typical values are at VCC = 5.0V, 25oC ambient and maximum loading.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
6. This parameter is determined by device characterization but is not production tested.
7. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
8. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
9. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
10. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
11. See test circuit and wave forms.
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. This parameter is guaranteed but not production tested.
CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T
4-74
CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T
Test Circuits and Waveforms
NOTE:
14. Pulse Generator for All Pulses: Rate ≤1.0MHz; ZOUT ≤50Ω;
tf, tr≤ 2.5ns. FIGURE 1. TEST CIRCUIT
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING FIGURE 3. PULSE WIDTH
FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY
DUT
PULSE
GENERATOR
RTCL
50pF
VCC
VOUT
7.0V
500Ω
VIN
500Ω
SWITCH POSITION
TEST SWITCH
tPLZ, tPZL Closed
tPHZ, tPZH, tPLH, tPHL Open
DEFINITIONS:
CL = Load capacitance, includes jig and probe capacitance.
RT = Termination resistance, should be equal to Z OUT of the
Pulse Generator.
3V
1.5V
0V
DATA INPUT
TIMING INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS CONTROL
PRESET, CLEAR,
CLOCK ENABLE, ETC.
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
tSU
tREM
tH
tSU tH
PRESET, CLEAR, ETC. tW
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
3V
1.5V
0V
CONTROL INPUT
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH SWITCH
OPEN
tPZL 3.5V
1.5V
1.5V
0V
tPLZ
tPHZ
tPZH
0V
3.5V
0.3V
0.3V
VOL
VOH
SWITCH
CLOSED
ENABLE DISABLE
1.5V
3V
0V
1.5V
3V
0V
tPLH
SAME PHASE
INPUT TRANSITION
tPHL
tPLH tPHL
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT 1.5V
VOH
VOL
