S E M I C O N D U C T O R December 1996 CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T Fast CMOS Octal D Registers (Three-State) Features Ordering Information * Advanced 0.8 micron CMOS Technology PART NUMBER TEMP. RANGE (oC) CD74FCT374ATM -40 to 85 20 Ld SOIC M20.3-P CD74FCT374ATQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT374CTM -40 to 85 20 Ld SOIC M20.3-P * TTL Input and Output Levels CD74FCT374CTQM -40 to 85 20 Ld QSOP M20.15-P * Low Ground Bounce Outputs CD74FCT374DTM -40 to 85 20 Ld SOIC M20.3-P * Extremely Low Static Power CD74FCT374DTQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT374TM -40 to 85 20 Ld SOIC M20.3-P CD74FCT374TQM -40 to 85 20 Ld QSOP M20.15-P Description CD74FCT534ATM -40 to 85 20 Ld SOIC M20.3-P These devices are 8-bit wide octal registers designed with eight D-type flip-flops with a buffered common clock and buffered three-state outputs. When output enable (OE) is LOW, the outputs are enabled. When OE is HIGH, the outputs are in the high impedance state. Input data meeting the setup and hold time requirements of the D inputs is transferred to the O outputs on the LOW-to-HIGH transition of the clock input. CD74FCT534ATQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT534CTM -40 to 85 20 Ld SOIC M20.3-P CD74FCT534CTQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT534DTM -40 to 85 20 Ld SOIC M20.3-P CD74FCT534DTQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT534TM -40 to 85 20 Ld SOIC M20.3-P CD74FCT534TQM -40 to 85 20 Ld QSOP M20.15-P All CD74FCT2574T devices have a built-in 25 series resistor on all outputs to reduce noise due to reflections, thus eliminating the need for an external terminating resistor. CD74FCT574ATM -40 to 85 20 Ld SOIC M20.3-P CD74FCT574ATQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT574CTM -40 to 85 20 Ld SOIC M20.3-P CD74FCT574CTQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT574DTM -40 to 85 20 Ld SOIC M20.3-P CD74FCT574DTQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT574TM -40 to 85 20 Ld SOIC M20.3-P CD74FCT574TQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT2374ATM -40 to 85 20 Ld SOIC M20.3-P CD74FCT2374ATQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT2374CTM -40 to 85 20 Ld SOIC M20.3-P CD74FCT2374CTQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT2374TM -40 to 85 20 Ld SOIC M20.3-P CD74FCT2374TQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT2574ATM -40 to 85 20 Ld SOIC M20.3-P CD74FCT2574ATQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT2574CTM -40 to 85 20 Ld SOIC M20.3-P CD74FCT2574CTQM -40 to 85 20 Ld QSOP M20.15-P CD74FCT2574TM -40 to 85 20 Ld SOIC M20.3-P CD74FCT2574TQM -40 to 85 20 Ld QSOP M20.15-P * Pin Compatible With Bipolar FASTTM Series at a Higher Speed and Lower Power Consumption * 25 Series Resistor on All Outputs (CD74FCT2374T, CD74FCT2574T only) * Hysteresis on All Inputs PKG. NO. PACKAGE NOTE: When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1996 4-69 File Number 4171.2 CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T Pinouts CD74FCT374T, CD74FCT2374T (QSOP, SOIC) TOP VIEW CD74FCT534T (QSOP, SOIC) TOP VIEW CD74FCT574T, CD74FCT2574T (QSOP, SOIC) TOP VIEW OE 1 20 VCC OE 1 20 VCC OE 1 O0 2 19 O7 O0 2 19 O7 D0 2 19 O0 D0 3 18 D7 D0 3 18 D7 D1 3 18 O1 20 VCC D1 4 17 D6 D1 4 17 D6 D2 4 17 O2 O1 5 16 O6 O1 5 16 O6 D3 5 16 O3 O2 6 15 O5 O2 6 15 O5 D4 6 15 O4 D2 7 14 D5 D2 7 14 D5 D5 7 14 O5 D3 8 13 D4 D3 8 13 D4 D6 8 13 O6 O3 9 12 O4 O3 9 12 O4 D7 9 12 O7 GND 10 11 CP GND 10 11 CP GND 10 11 CP Functional Block Diagrams CD74FCT374T, CD74FCT2374T, CD74FCT574, CD74FCT2574T D0 D1 D2 D D CP Q CP Q D3 D CP Q D4 D5 D6 D7 D D D D D CP Q CP Q CP Q CP Q CP Q CP OE O0 O1 O2 O3 O4 O5 O6 O7 CD74FCT534T D0 D1 D Q D2 D CP Q D3 D CP Q D4 D CP Q D5 D CP Q D6 D CP Q D7 D CP Q D CP Q CP CP OE O0 O1 O2 O3 4-70 O4 O5 O6 O7 CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T TRUTH TABLE (NOTE 1) INPUTS FUNCTION OUTPUTS INTERNAL OE CP DN ON QN H L X Z NC H H X Z NC L L H L CD74FCT534T High-Z Load Register L H L H H L Z L H H Z H CD74FCT374T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T FUNCTION High-Z Load Register OE CP DN ON QN H L X Z NC H H X Z NC L L L H L H H L H L Z H H H Z L NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care Z = High Impedance NC = No Change = LOW-to-HIGH Transition Pin Descriptions PIN NAME DESCRIPTION OE Output Enable Input (Active LOW) CP Clock Pulse for the register. Enters data on LOW-to-HIGH transition D0-D7 Data Inputs O0-O7 Three-State Outputs (True) O0-O7 Three-State Outputs (Inverted) GND Ground VCC Power 4-71 CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T Absolute Maximum Ratings Thermal Information DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120mA Thermal Resistance (Typical, Note 2) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage to Ground Potential Inputs and VCC Only . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Supply Voltage to Ground Potential Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER (NOTE 3) TEST CONDITIONS SYMBOL MIN (NOTE 4) TYP MAX UNITS DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40oC to 85oC, VCC = 5.0V 5% Output HIGH Voltage VOH VCC = Min, VIN = VIH or VIL IOH = -15.0mA 2.4 3.0 - V Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 64mA - 0.3 0.50 V Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 12mA (25 Series) - 0.3 0.50 V Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 - - V Input LOW Voltage VIL Guaranteed Logic LOW Level - - 0.8 V Input HIGH Current IIH VCC = Max VIN = VCC - - 1 A Input LOW Current IIL VCC = Max VIN = GND - - -1 A IOZH VCC = Max VOUT = 2.7V - - 1 A A High Impedance Output Current IOZL VOUT = 0.5V Clamp Diode Voltage VIK VCC = Min, IIN = -18mA Short Circuit Current IOS VCC = Max (Note 5), VOUT = GND Power Down Disable IOFF VCC = GND, VOUT = 4.5V Input Hysteresis - - -1 - -0.7 -1.2 V -60 -120 - mA - - 100 A - 200 - mV VIN = 0V - 6 10 pF VOUT = 0V - 8 12 pF VH CAPACITANCE TA = 25oC, f = 1MHz Input Capacitance (Note 6) Output Capacitance (Note 6) CIN COUT POWER SUPPLY SPECIFICATIONS ICC VCC = Max VIN = GND or VCC - 0.1 500 A Supply Current per Input at TTL HIGH ICC VCC = Max VIN = 3.4V (Note 7) - 0.5 2.0 mA Supply Current per Input per MHz (Note 8) ICCD VCC = Max, Outputs Open OE = GND One Input Toggling 50% Duty Cycle VIN = VCC VIN = GND - 0.15 0.25 mA/ MHz Total Power Supply Current (Note 10) IC VCC = Max, Outputs Open fCP = 10MHz, 50% Duty Cycle OE = GND fI = 5MHz, One Bit toggling VIN = VCC VIN = GND - 1.5 3.5 (Note 9) mA VIN = 3.4V VIN = GND - 2.0 5.5 (Note 9) mA VIN = VCC VIN = GND - 3.5 7.3 (Note 9) mA VIN = 3.4V VIN = GND - 6.0 16.3 (Note 9) mA Quiescent Power Supply Current VCC = Max, Outputs Open fCP = 10MHz, 50% Duty Cycle OE = GND fI = 2.5MHz, Eight Bits toggling 4-72 CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T Switching Specifications Over Operating Range PARAMETER T AT CT DT (NOTE 11) TEST (NOTE 12) (NOTE 12) (NOTE 12) (NOTE 12) SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX UNITS CD74FCT374T, CD74FCT534T, CD74FCT2374T Propagation Delay CP to ON tPLH, tPHL Output Enable Time OE to ON CL = 50pF RL = 500 2.0 10.0 2.0 6.5 2.0 5.2 2.0 4.5 ns tPZH, tPZL 1.5 12.5 1.5 6.5 1.5 5.5 1.5 5.5 ns Output Disable Time (Note 13) OE to ON tPHZ, tPLZ 1.5 8.0 1.5 5.5 1.5 5.0 1.5 5.0 ns Setup Time HIGH or LOW, DN to CP tSU 2.0 - 2.0 - 2.0 - 2.0 - ns Hold Time HIGH or LOW, DN to CP tH 1.5 - 1.5 - 1.5 - 1.0 - ns CP Pulse Width (Note 13) HIGH or LOW tW 7.0 - 5.0 - 5.0 - 3.0 - ns 2.0 8.5 2.0 6.5 2.0 5.2 2.0 4.5 ns CD74FCT574T, CD74FCT2574T Propagation Delay CP to ON tPLH, tPHL Output Enable Time OE to ON tPZH, tPZL 1.5 10.0 1.5 6.5 1.5 5.5 1.5 5.5 ns Output Disable Time (Note 13) OE to ON tPHZ, tPLZ 1.5 6.5 1.5 5.5 1.5 5.0 1.5 5.0 ns Setup Time HIGH or LOW, DN to CP tSU 2.0 - 2.0 - 2.0 - 2.0 - ns Hold Time HIGH or LOW, DN to CP tH 1.5 - 1.5 - 1.5 - 1.0 - ns CP Pulse Width (Note 13) HIGH or LOW tW 7.0 - 5.0 - 5.0 - 3.0 - ns CL = 50pF RL = 500 NOTES: 3. 4. 5. 6. 7. 8. 9. 10. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type. Typical values are at VCC = 5.0V, 25oC ambient and maximum loading. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. This parameter is determined by device characterization but is not production tested. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 11. See test circuit and wave forms. 12. Minimum limits are guaranteed but not tested on Propagation Delays. 13. This parameter is guaranteed but not production tested. 4-73 CD74FCT374T, CD74FCT534T, CD74FCT574T, CD74FCT2374T, CD74FCT2574T Test Circuits and Waveforms VCC SWITCH POSITION 7.0V 500 PULSE GENERATOR VOUT VIN DUT 50pF CL RT TEST SWITCH tPLZ, tPZL Closed tPHZ, tPZH, tPLH, tPHL Open DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. 500 NOTE: 14. Pulse Generator for All Pulses: Rate 1.0MHz; ZOUT 50; tf, tr 2.5ns. FIGURE 1. TEST CIRCUIT 3V 1.5V 0V DATA INPUT tSU tH 3V 1.5V 0V TIMING INPUT ASYNCHRONOUS CONTROL PRESET, CLEAR, ETC. tREM SYNCHRONOUS CONTROL PRESET, CLEAR, CLOCK ENABLE, ETC. 3V 1.5V 0V tSU 3V 1.5V 0V tH FIGURE 2. SETUP, HOLD, AND RELEASE TIMING ENABLE LOW-HIGH-LOW PULSE 1.5V tW HIGH-LOW-HIGH PULSE 1.5V FIGURE 3. PULSE WIDTH DISABLE 3V 3V SAME PHASE INPUT TRANSITION 1.5V CONTROL INPUT 0V tPLZ tPZL tPLH 3.5V OUTPUT NORMALLY LOW SWITCH CLOSED OUTPUT NORMALLY HIGH SWITCH OPEN tPHL 3.5V VOH 1.5V 0.3V tPZH 1.5V tPHZ 0.3V 1.5V VOL OUTPUT VOL tPLH VOH tPHL 3V 1.5V 0V 0V OPPOSITE PHASE INPUT TRANSITION 0V 1.5V 0V FIGURE 5. PROPAGATION DELAY FIGURE 4. ENABLE AND DISABLE TIMING 4-74