© 2011–2013 Freescale Semiconducto r, Inc.
Freescale Semiconductor
Data Sheet Document Number: MSC8157E
Rev. 2, 12/2013
MSC8157E
• Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP
core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,
unified 512 Kbyte L2 cache configurable as M2 memory in
64 Kbyte increments, memory management unit (MMU),
extended programmable interrupt controller (EPIC), two
general-purpose 32-bit timers, debug and profiling support,
low-power Wait, Stop, and power-down processing modes, and
ECC/EDC support.
• Chip-level arbitration and switching system (CLASS) that
provides full fabric non-blocking arbitration between the cores
and other initiators and the M2 memory, shared M3 memory,
DDR SRAM controller, device configuration control and status
registers, MAPLE-B, and other targets.
• 3072 Kbyte 128-bit wide M3 memory, 2048 Kbytes of which can
be turned off to save power.
• 96 Kbyte boot ROM.
• Three input clocks (one global and two differential).
• Six PLLs (three global, two Serial RapidIO, one DDR PLLs).
• Second generation Multi-Accelerator Platform Engine for
Baseband (MAPLE-B2) with a second generation programmable
system interface (PSIF2); Tu rbo encoding and decoding; Viterbi
decoding; FFT/iFFT and DFT/iDFT processing; downlink chip
rate processing; CRC processing and insertion; equalization
processing and matrix inversion; uplink batch and fast processing.
Some MAPLE-B2 processors can be disabled when not required
to reduce overall power consumption.
• Security Engine (SEC) optimized to process all the algorithms
associated with IPSe c, IKE, SSL/TLS, 3GPP, and LTE using 4
crypto-channels with multi-command descriptor chains,
integrated controll er for as s ignment of the eight execution units
(PKEU, DEU, AESU, AFEU, MDEU, KEU, SNOW, and the
random number generator (RNG), and XOR engine to accelerate
parity checking for RAID storage applications.
• One DDR controllers with up to a 667 MHz clock (1333 MHz
data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in
up to four banks (two per controller) and support for DDR3.
• DMA controller with 32 unidirectional channels supporting 16
memory-to-memory channe ls with up to 1024 buffer descriptors
per channel, and programmable priority, buffe r , and multiplexing
configuration. It is optimized for DDR SDRAM.
• High-speed serial interface with a 10-lane SerDes PHY that
supports two Serial RapidIO interfaces, one PCI Express
interface, six CPRI lanes, and two SGMII interfaces
(multiplexed). The Serial RapidIO interfaces support x1/x2/x4
operation up to 5 Gbaud with an enhanced messaging unit
(eMSG) and two DMA units. The PCI Express controller supports
32- and 64-bit addressing, x1/x2/x4 link. The six CPRI controllers
can support six lanes up to 6.144 Gbaud.
• QUICC Engine technology subsystem with dual RISC
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction
RAM, supporting two communication con trollers for two Gigabit
Ethernet interfaces (RGMII or SGMII), to offload scheduling
tasks from the DSP cores, and an SPI.
• I/O Interrupt Concentrator consolida te s a ll chi p maskable
interrupt and non-maskable interrupt sources and routes then to
INT_OUT/CP_TX_INT, NMI_OUT/CP_RX_INT, and the cores.
• UART that permits full-duplex operation with a bit rate of up to
6.25 Mbps.
• T wo general-purpose 3 2-bit timers for R T OS support per SC3850
core, four timer module s with four 16-bit fully programmable
timers, two timer modules with four 32-bit fully programmable
timers; and eight software watchdog timers (SWT).
• Eight programmable hardware semaphores.
• Up to 32 virtual interrupts and a virtual NMI asserted by simple
write access.
•I
2C interface.
• Up to 32 GPIO ports, sixteen of which can be configured as
external interrupts.
• Boot interface options include Ethernet, Serial RapidI O interface,
I2C, and SPI.
• Supports IEEE Std. 1149.6 JTAG interface
• Low power CMOS design, with low-power standby and
power-down modes, and op timized power-management circuitry .
• 45 nm SOI CMOS technology.
Six-Core Digital Signal
Processor with Security