PIC16C554-04/P - Microchip Technology



1998 Microchip Technology Inc.

Preliminary

DS40143C-page 1

Devices included in this data sheet:

Referred to collectively as PIC16C55X.

• PIC16C554

• PIC16C558

High Performance RISC CPU:

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for

program branches which are two-cycle

• Operating speed:

- DC - 20 MHz clock input

- DC - 200 ns instruction cycle

• Interrupt capability

• 16 special function hardware registers

• 8-level deep hardware stack

• Direct, Indirect and Relative addressing modes

Peripheral Features:

• 13 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

Device Program

Memory Data

Memory

PIC16C554 512 80

PIC16C558 2K 128

Pin Diagram

Special Microcontroller Features (cont’d)

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Serial in-circuit programming (via two pins)

• Four user programmable ID locations

CMOS Technology:

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range

- 2.5V to 5.5V

• Commercial, industrial and extended tempera-

ture range

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

- 15

A typical @ 3.0V, 32 kHz

- < 1.0

A typical standby current @ 3.0V

RA1

RA0

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

OSC1/CLKIN

RA2

RA3

MCLR/ VPP

VSS

RB0/INT

RB1

RB2

RB3

RA4/T0CKI

RA1

RA0

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

OSC1/CLKIN

RA2

RA3

MCLR/ VPP

VSS

RB0/INT

RB1

RB2

RA4/T0CKI

PIC16C55X

RB3RB3

VDD

PDIP, SOIC, Windowed CERDIP

SSOP

•1

PIC16C55X

EPROM-Based 8-Bit CMOS Microcontrollers

PIC16C55X

DS40143C-page 2

Preliminary



1998 Microchip Technology Inc.

Device Differences

Note 1:

If you change from this device to another device, please verify oscillator characteristics in your application.

Device Voltage

Range Oscillator Process

Technology

(Microns)

PIC16C554 2.5 - 5.5 See Note 1 0.9

PIC16C558 2.5 - 5.5 See Note 1 0.9



1998 Microchip Technology Inc.

Preliminary

DS40143C-page 3

PIC16C55X

Table of Contents

1.0 General Description......................................................................................................................................................................5

2.0 PIC16C55X Device Varieties .......................................................................................................................................................7

3.0 Architectural Overview .................................................................................................................................................................9

4.0 Memory Organization................................................................................................................................................................ 13

5.0 I/O Ports.................................................................................................................................................................................... 23

6.0 Timer0 Module .......................................................................................................................................................................... 29

7.0 Special Features of the CPU..................................................................................................................................................... 35

8.0 Instruction Set Summary........................................................................................................................................................... 51

9.0 Development Support................................................................................................................................................................ 63

10.0 Electrical Specifications............................................................................................................................................................. 69

11.0 Packaging Information............................................................................................................................................................... 81

Appendix A: Enhancements............................................................................................................................................................ 87

Appendix B: Compatibility............................................................................................................................................................... 87

INDEX.................................................................................................................................................................................................. 89

PIC16C55X Product Identification System .......................................................................................................................................... 93

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended

workarounds. As de vice/documentation issues become kno wn to us, we will pub lish an errata sheet. The errata will specify the revi-

sion of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales ofﬁce (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277

When contacting a sales ofﬁce or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure

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We appreciate your assistance in making this a better document.

PIC16C55X

DS40143C-page 4

Preliminary



1998 Microchip Technology Inc.

NOTES:



1998 Microchip Technology Inc.

Preliminary

DS40143C-page 5

PIC16C55X

1.0 GENERAL DESCRIPTION

The PIC16C55X are 18 and 20-Pin EPROM-based

members of the versatile PIC16CXX family of lo w-cost,

high-performance, CMOS, fully-static, 8-bit

microcontrollers.

All PICmicro

microcontrollers employ an advanced

RISC architecture. The PIC16C55X have enhanced

core features, eight-le vel deep stack, and multiple inter-

nal and external interrupt sources. The separate

instruction and data buses of the Harvard architecture

allow a 14-bit wide instruction word with the separate

8-bit wide data. The two-stage instruction pipeline

allows all instructions to execute in a single-cycle,

except for program branches (which require two

cycles). A total of 35 instructions (reduced instruction

set) are av ailable. Additionally, a large register set gives

some of the architectural innov ations used to achie v e a

very high performance.

PIC16C55X microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

The PIC16C554 has 80 bytes of RAM. The PIC16C558

has 128 bytes of RAM. Each de vice has 13 I/O pins and

an 8-bit timer/counter with an 8-bit programmab le pres-

caler.

PIC16C55X devices have special features to reduce

external components, thus reducing cost, enhancing

system reliability and reducing power consumption.

There are f our oscillator options, of which the single pin

RC oscillator provides a low-cost solution, the LP

oscillator minimizes power consumption, XT is a

standard crystal, and the HS is f or High Speed crystals.

The SLEEP (power-down) mode offers power saving.

The user can wake up the chip from SLEEP through

several external and internal interrupts and reset.

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software

lock-up.

A UV-erasable CERDIP-packaged version is ideal for

code development while the cost-effective One-Time

Programmable (OTP) version is suitable for production

in any volume.

Table 1-1 shows the features of the PIC16C55X

mid-range microcontroller families.

A simpliﬁed block diagram of the PIC16C55X is sho wn

in Figure 3-1.

The PIC16C55X series ﬁt perfectly in applications

ranging from motor control to low-power remote sen-

sors. The EPROM technology makes customization of

application programs (detection levels, pulse genera-

tion, timers, etc.) extremely fast and convenient. The

small footprint packages make this microcontroller

series perfect f or all applications with space limitations .

Low-cost, low-power, high-performance, ease of use

and I/O ﬂexibility make the PIC16C55X very versatile.

1.1 Family and Upward Compatibility

Those users familiar with the PIC16C5X family of

microcontrollers will realize that this is an enhanced

version of the PIC16C5X architecture. Please refer to

Appendix A for a detailed list of enhancements. Code

written for PIC16C5X can be easily ported to

PIC16C55X family of devices (Appendix B).

The PIC16C55X f amily ﬁlls the niche for users w anting

to migrate up from the PIC16C5X family and not need-

ing various peripheral f eatures of other members of the

PIC16XX mid-range microcontroller family.

1.2 Development Support

The PIC16C55X family is suppor ted by a full-featured

macro assembler, a software simulator, an in-circuit

emulator, a low-cost development programmer and a

full-featured programmer. A “C” compiler and fuzzy

logic support tools are also available.

PIC16C55X

DS40143C-page 6

Preliminary



1998 Microchip Technology Inc.

TABLE 1-1: PIC16C55X FAMILY OF DEVICES

PIC16C554 PIC16C558

Clock

Maximum Frequency of Operation (MHz) 20 20

Memory

EPROM Program Memory (x14 words) 512 2K

Data Memory (bytes) 80 128

Peripherals

Timer Module(s) TMR0 TMR0

Features

Interrupt Sources 3 3

I/O Pins 13 13

Voltage Range (Volts) 2.5-5.5 2.5-5.5

Brown-out Reset — —

Packages 18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

All PICmicro

Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high

I/O current capability. All PIC16C55X Family devices use serial programming with clock pin RB6 and data pin RB7.



1998 Microchip Technology Inc.

Preliminary

DS40143C-page 7

PIC16C55X

2.0 PIC16C55X DEVICE VARIETIES

A variety of frequency ranges and pac kaging options are

available. Depending on application and production

requirements the proper device option can be selected

using the information in the PIC16C55X Product

Identiﬁcation System section at the end of this data

sheet. When placing orders, please use this page of the

data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in CERDIP package

is optimal for prototype development and pilot

programs. This version can be erased and

reprogrammed to any of the oscillator modes.

Microchip's PICSTART



and PROMATE



programmers both support programming of the

PIC16C55X.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the ﬂexibility for frequent code

updates and small volume applications. In addition to

the program memory, the conﬁguration bits must also

be programmed.

2.3 Quick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code pat-

terns have stabilized. The devices are identical to the

OTP devices but with all EPROM locations and conﬁg-

uration options already programmed by the factory.

Certain code and prototype veriﬁcation procedures

apply before production shipments are available.

Please contact your Microchip Technology sales ofﬁce

for more details.

2.4 Serialized

Quick-Turnaround-Production

(SQTP

) Devices

Microchip offers a unique programming service where

a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

PIC16C55X

DS40143C-page 8

Preliminary



1998 Microchip Technology Inc.

NOTES:



1998 Microchip Technology Inc.

Preliminary

DS40143C-page 9

PIC16C55X

3.0 ARCHITECTURAL OVERVIEW

The high perf ormance of the PIC16C55X family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16C55X uses a Harvard architecture, in

which, program and data are accessed from separate

memories using separate busses. This improves

bandwidth over traditional von Neumann architecture

where program and data are fetched from the same

memory. Separating progr am and data memory further

allows instructions to be sized differently than 8-bit

wide data words. Instruction opcodes are 14-bits wide

making it possible to have all single word instructions.

A 14-bit wide program memory access bus fetches a

14-bit instruction in a single cycle. A tw o-stage pipeline

overlaps fetch and execution of instructions.

Consequently, all instructions (35) execute in a sin-

gle-cycle (200 ns @ 20 MHz) except for program

branches. The table belo w lists the memory (EEPROM

and ROM).

The PIC16C554 addresses 512 x 14 on-chip program

memory. The PIC16C558 addresses 2K x 14 program

memory. All program memory is internal.

The PIC16C55X can directly or indirectly address its

registers including the program counter are mapped

into the data memory. The PIC16C55X have an

orthogonal (symmetrical) instruction set that makes it

possible to carry out any operation on any register

using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make program-

ming with the PIC16C55X simple yet efﬁcient. In addi-

tion, the learning curve is reduced signiﬁcantly.

Device Program

Memory Data

Memory

PIC16C554 512 80

PIC16C558 2K 128

The PIC16C55X devices contain an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register). The other operand is a ﬁle register or an

immediate constant. In single oper and instructions, the

operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register . The C and DC bits

operate as a Borrow and Digit Borrow out bit,

respectively, in subtraction. See the

SUBLW

and

SUBWF

instructions for examples.

A simpliﬁed block diagram is shown in Figure 3-1, with

a description of the device pins in Table 3-1.

PIC16C55X

DS40143C-page 10

Preliminary



1998 Microchip Technology Inc.

FIGURE 3-1: BLOCK DIAGRAM

Note 1: Higher order bits are from the status register.

Device Program

Memory Data Memory

(RAM)

PIC16C554

PIC16C558 512 x 14

2K x 14 80 x 8

128 x 8

EPROM

Program

Memory

2K x 14

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

128 x 8

Direct Addr 7

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS Timer0

PORTA

PORTB

RA1

RA4/T0CKI

RB0/INT

RB7:RB1

RAM Addr(1)

RA0

RA2

RA3

512 x 14

to 80 x 8 to



1998 Microchip Technology Inc.

Preliminary

DS40143C-page 11

PIC16C55X

TABLE 3-1: PIC16C55X PINOUT DESCRIPTION

Name

DIP

SOIC

Pin #

SSOP

Pin # I/O/P

Type Buffer

Type

Description

OSC1/CLKIN 16 18 I ST/CMOS Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator

in crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

MCLR/V

4 4 I/P ST Master clear (reset) input/programming voltage input.

This pin is an active low reset to the device.

RA0 17 19 I/O ST Bi-directional I/O port

RA1 18 20 I/O ST Bi-directional I/O port

RA2 1 1 I/O ST Bi-directional I/O port

RA3 2 2 I/O ST Bi-directional I/O port

RA4/T0CKI 3 3 I/O ST Bi-directional I/O port or external clock input for TMR0.

Output is open drain type.

RB0/INT 6 7 I/O TTL/ST

(1)

Bi-directional I/O port can be software programmed for

internal weak pull-up. RB0/INT can also be selected as

an external interrupt pin.

RB1 7 8 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up.

RB2 8 9 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up.

RB3 9 10 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up.

RB4 10 11 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up. Interrupt on change pin.

RB5 11 12 I/O TTL Bi-directional I/O port can be software programmed for

internal weak pull-up. Interrupt on change pin.

RB6 12 13 I/O TTL/ST

(2)

Bi-directional I/O port can be software programmed for

internal weak pull-up. Interrupt on change pin. Serial pro-

gramming clock.

RB7 13 14 I/O TTL/ST

(2)

Bi-directional I/O port can be software programmed for

internal weak pull-up. Interrupt on change pin. Serial pro-

gramming data.

5 5,6 P — Ground reference for logic and I/O pins.

14 15,16 P — Positive supply for logic and I/O pins.

Legend: O = output I/O = input/output P = power

— = Not used I = Input ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

PIC16C55X

DS40143C-page 12

Preliminary



1998 Microchip Technology Inc.

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution ﬂow are shown in Figure 3-2.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instr uction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instr uction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g.,

GOTO

)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the e xecution cycle , the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1



1998 Microchip Technology Inc.

Preliminary

DS40143C-page 13

PIC16C55X

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C55X has a 13-bit prog ram counter capab le

of addressing an 8K x 14 program memory space. Only

the ﬁrst 512 x 14 (0000h - 01FFh) for the PIC16C554

and 2K x 14 (0000h - 07FFh) for the PIC16C558 are

physically implemented. Accessing a location above

these boundaries will cause a wrap-around within the

ﬁrst 512 x 14 space PIC16C554 or 2K x 14 space

PIC16C558. The reset v ector is at 0000h and the inter-

rupt vector is at 0004h (Figure 4-1, Figure 4-2).

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16C554

PC<12:0>

000h

0004

0005

01FFh

0200h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16C558

4.2 Data Memory Organization

The data memory (Figure 4-3 and Figure 4-4) is

partitioned into two Banks which contain the general

purpose registers and the special function registers.

Bank 0 is selected when the RP0 bit (STATUS <5>) is

cleared. Bank 1 is selected when the RP0 bit is set.

The Special Function Registers are located in the ﬁrst

32 locations of each Bank. Register locations 20-6Fh

(Bank0) on the PIC16C554 and 20-7Fh (Bank0) and

A0-BFh (Bank1) on the PIC16C558 are general pur-

pose registers implemented as static RAM. Some spe-

cial purpose registers are mapped in Bank 1.

4.2.1 GENERAL PURPOSE REGISTER FILE

The register ﬁle is organized as 80 x 8 in the

PIC16C554 and 128 x 8 in the PIC16C558. Each can

be accessed either directly or indirectly through the File

Select Register , FSR (Section 4.4).

PC<12:0>

000h

0004

0005

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

PIC16C55X

DS40143C-page 14 Preliminary  1998 Microchip Technology Inc.

FIGURE 4-3: DATA MEMORY MAP FOR

THE PIC16C554

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

6Fh

70h

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

File

Address

FIGURE 4-4: DATA MEMORY MAP FOR

THE PIC16C558

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

BFh

C0h

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

File

Address

General

Purpose

 1998 Microchip Technology Inc. Preliminary DS40143C-page 15

PIC16C55X

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (Table 4-1). These

registers are static RAM.

The special function registers can be classiﬁed into two

sets (core and peripheral). The special function regis-

ters associated with the “core” functions are described

in this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature.

TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C55X

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Reset

Value on

all other

resets(1)

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical

01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu

02h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000

03h STATUS IRP(2) RP1(2) RP0 TO PD Z DC C 0001 1xxx 000q quuu

04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

07h Unimplemented — —

08h Unimplemented — —

09h Unimplemented — —

0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

0Bh INTCON GIE (3) T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch Unimplemented — —

0Dh-1Eh Unimplemented — —

1Fh Unimplemented — —

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000

83h STATUS — — RP0 TO PD Z DC C 0001 1xxx 000q quuu

84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

87h Unimplemented — —

88h Unimplemented — —

89h Unimplemented — —

8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

8Bh INTCON GIE (3) T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

8Ch Unimplemented — —

8Dh Unimplemented — —

8Eh PCON — — — — — — POR — ---- --0- ---- --u-

8Fh-9Eh Unimplemented — —

9Fh Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR reset and Watchdog Timer reset during normal operation.

Note 2: IRP & RP1bits are reserved, always maintain these bits clear.

Note 3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear.

PIC16C55X

DS40143C-page 16 Preliminary  1998 Microchip Technology Inc.

4.2.2.1 STATUS REGISTER

The STATUS register, shown in Figure 4-5, contains

the arithmetic status of the ALU, the RESET status and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Further more, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as the destination may be different

than intended.

For example, CLRF STATUS will clear the upper-three

bits and set the Z bit. This lea ves the status register as

000uu1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions be used to alter the STA-

TUS register because these instructions do not affect

any status bits . For other instructions, not affecting any

status bits, see the “Instruction Set Summary”.

Note 1: The IRP and RP1 bits (STATUS<7:6>)

are not used by the PIC16C55X and

should be programmed as ’0'. Use of

these bits as general purpose R/W bits is

NOT recommended, since this may

affect upward compatibility with future

products.

Note 2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

FIGURE 4-5: STATUS REGISTER (ADDRESS 03H OR 83H)

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit

- n = Value at POR reset

- x = Unknown at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

The IRP bit is reserved on the PIC16C55X, always maintain this bit clear.

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C55X, always maintain this bit clear.

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most signiﬁcant bit of the result occurred

0 = No carry-out from the most signiﬁcant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of

the source register.

 1998 Microchip Technology Inc. Preliminary DS40143C-page 17

PIC16C55X

4.2.2.2 OPTION REGISTER

The OPTION register is a readable and writable

the TMR0/WDT prescaler, the external RB0/INT

interrupt, TMR0 and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT

(PSA = 1).

FIGURE 4-6: OPTION REGISTER (ADDRESS 81H)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16C55X

DS40143C-page 18 Preliminary  1998 Microchip Technology Inc.

4.2.2.3 INTCON REGISTER

The INTCON register is a readable and writable

for all interrupt sources.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

FIGURE 4-7: INTCON REGISTER (ADDRESS 0BH OR 8BH)

R/W-0 Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE — T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit

- n = Value at POR reset

- x = Unknown at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6: — = Reserved for future use. Always maintain this bit clear.

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software)

0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

 1998 Microchip Technology Inc. Preliminary DS40143C-page 19

PIC16C55X

4.2.2.4 PCON REGISTER

The PCON register contains ﬂag bits to differentiate

between a Po wer-on Reset, an e xternal MCLR reset or

WDT reset. See Section 7.3 and Section 7.4 for

detailed reset operation.

FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — POR — R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0'

bit 1: POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = Power-on Reset occurred

bit 0: Unimplemented: Read as '0'

PIC16C55X

DS40143C-page 20 Preliminary  1998 Microchip Technology Inc.

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register . The high bits (PC<12:8>) are not directly

readable or writable and come from PCLATH. On any

reset, the PC is cleared. Figure 4-9 shows the two

situations f or the loading of the PC. The upper e xample in

the ﬁgure shows ho w the PC is loaded on a write to PCL

(PCLATH<4:0> → PCH). The lower e xample in Figure 4-9

shows how the PC is loaded during a CALL or GOTO

instruction (PCLATH<4:3> → PCH).

FIGURE 4-9: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an

offset to the program counter (ADDWF PCL). When

doing a table read using a computed GOTO method,

care should be e x ercised if the tab le location crosses a

PCL memory boundary (each 256 byte bloc k). Ref er to

the application note

“Implementing a Table Read"

(AN556).

PC 12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode <10:0>

PC 12 11 10 0

PCLATH<4:3>

PCH PCL

8 7

PCLATH

PCH PCL

PCL as

Destination

4.3.2 STACK

The PIC16C55X family has an 8 level deep x 13-bit

wide hardware stack (Figure 4-1 and Figure 4-2). The

stack space is not part of either program or data space

and the stack pointer is not readable or writable. The

PC is PUSHed onto the stack when a CALL instruction

is executed or an interrupt causes a branch. The stack

is POP ed in the e vent of a RETURN, RETLW or a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The stack oper ates as a circular buff er . This means that

after the stack has been PUSHed eight times , the ninth

push ov erwrites the v alue that w as stored from the ﬁrst

push. The tenth push overwrites the second push (and

so on).

Note 1: There are no STATUS bits to indicate

stack overﬂow or stack underﬂow

conditions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions, or vectoring to an interrupt

address.

 1998 Microchip Technology Inc. Preliminary DS40143C-page 21

PIC16C55X

4.4 Indirect Addressing, INDF and FSR

Registers

The INDF register is not a ph ysical register . Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses data pointed to by the ﬁle select register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a

no-operation (although status bits ma y be aff ected). An

effective 9-bit address is obtained b y concatenating the

8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 4-10. However, IRP is not used in the

PIC16C55X.

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

EXT clrf INDF ;clear INDF register

incf FSR ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no clear next

;yes continue

CONTINUE:

FIGURE 4-10: DIRECT/INDIRECT ADDRESSING PIC16C55X

For memory map detail see Figure 4-3 and Figure 4-4.

Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

Data

Memory

Indirect AddressingDirect Addressing

bank select location select

(1)RP1 RP0 6 0

from opcode IRP(1) FSR register

bank select location select

00 01 10 11 00h

7Fh

00h

7Fh Bank 0 Bank 1 Bank 2 Bank 3

not used

PIC16C55X

DS40143C-page 22 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40143C-page 23

PIC16C55X

5.0 I/O PORTS

The PIC16C55X hav e tw o ports, PORTA and PORTB .

5.1 PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input

and an open drain output. Port RA4 is multiple xed with the

T0CKI clock input. All other RA port pins have Schmitt

Trigger input lev els and full CMOS output driv ers. All pins

have data direction bits (TRIS registers) which can conﬁg-

ure these pins as input or output.

A '1' in the TRISA register puts the corresponding output

driver in a hi- impedance mode. A '0' in the TRISA register

puts the contents of the output latch on the selected pin(s).

Reading the PORTA register reads the status of the pins,

whereas writing to it will wr ite to the por t latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are ﬁrst read, then this

value is modiﬁed and written to the port data latch.

FIGURE 5-1: BLOCK DIAGRAM OF

PORT PINS RA<3:0>

Note: On reset, the TRISA register is set to all inputs.

Data

bus

Q D

PortA

TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

Schmitt

input

buffer

VSS

VDD

I/O pin

Trigger

VSS

VDD

FIGURE 5-2: BLOCK DIA GRAM OF RA4 PIN

Data

bus

PORTA

TRISA

RD PORTA

Data Latch

TRISA Latch

RD TRISA

Schmitt

Trigger

input

buffer

VSS

I/O pin(1)

TMR0 clock input

Q D

VSS

PIC16C55X

DS40143C-page 24 Preliminary  1998 Microchip Technology Inc.

TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit # Buffer

Type Function

RA0 bit0 ST Bi-directional I/O port.

RA1 bit1 ST Bi-directional I/O port.

RA2 bit2 ST Bi-directional I/O port.

RA3 bit3 ST Bi-directional I/O port.

RA4/T0CKI bit4 ST Bi-directional I/O port or external clock input for TMR0. Output is open

drain type.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Value on

All Other Resets

05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu

85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: — = Unimplemented locations, read as ‘0’

x = unknown

u = unchanged

Note: Shaded bits are not used by PORTA.

 1998 Microchip Technology Inc. Preliminary DS40143C-page 25

PIC16C55X

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. A '1' in

the TRISB register puts the corresponding output driver

in a high impedance mode. A '0' in the TRISB register

puts the contents of the output latch on the selected

pin(s).

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are ﬁrst read, then

this value is modiﬁed and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up

(≈200 µA typical). A single control bit can turn on all the

pull-ups. This is done by clearing the RBPU

(OPTION<7>) bit. The weak pull-up is automatically

turned off when the port pin is conﬁgured as an output.

The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

conﬁgured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RBIF interrupt (ﬂag

latched in INTCON<0>). This interrupt can wake the

device from SLEEP. The user, in the interrupt service

routine, can clear the interrupt in the f ollo wing manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF.

A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software conﬁgurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression. (See AN552 in the

Microchip

Embedded Control Handbook

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

Note: If a change on the I/O pin should occur when the

read operation is being executed (start of the Q2

cycle), then the RBIF interrupt ﬂag may not

get set.

FIGURE 5-3: BLOCK DIAGRAM OF RB7:RB4 PINS

VSS

VDD

Data Latch

From other

RBPU(1)

VDD

I/O

Data bus

WR PortB

WR TRISB

Set RBIF

TRIS Latch

RD TRISB

RD PortB

RB7:RB4 pins

weak

pull-up

RD Port B

Latch

TTL

Input

Buffer

Note 1: TRISB = 1 enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer

RB7:RB6 in serial programming mode

VDD

VSS

Q D