ATTINY25-15SZ - MICROCHIP TECHNOLOGY

2586Q–AVR– 08 /20 13

Features

•High Performance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

•Non-volatile Program and Data Memories

– 2/4/8K Bytes of In-System Programmable Program Memory Flash

• Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes In-System Programmable EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 128/256/512 Bytes Internal SRAM

– Programming Lock for Self-Programming Flash Program and EEPROM Data Security

•Peripheral Features

– 8-bit Timer/Counter with Prescaler and Two PWM Channels

– 8-bit High Speed Timer/Counter with Separate Prescaler

• 2 High Frequency PWM Outputs with Separate Output Compare Registers

• Programmable Dead Time Generator

– USI – Universal Serial Interface with Start Condition Detector

– 10-bit ADC

• 4 Single Ended Channels

• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)

• Temperature Measurement

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

•Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

•I/O and Packages

– Six Programmable I/O Lines

– 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)

•Operating Voltage

– 1.8 - 5.5V for ATtiny25V/45V/85V

– 2.7 - 5.5V for ATtiny25/45/85

•Speed Grade

– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

•Industrial Temperature Range

•Low Power Consumption

– Active Mode:

• 1 MHz, 1.8V: 300 µA

– Power-down Mode:

• 0.1 µA at 1.8V

Atmel 8-bit AVR Microcontroller with 2/4/8K

Bytes In-System Programmable Flash

ATtiny25/V / ATtiny45/V / ATtiny85/V

Rev. 2586Q–AVR–08/2013

ATtiny25/45/85 [DATASHEET]

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1. Pin Configurations

Figure 1-1. Pinout ATtiny 25 /45/85

1.1 Pin Descriptions

1.1.1 VCC

Supply voltage.

1.1.2 GND

Ground.

1.1.3 Port B (PB5:PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Th e Port B output bu ffers

have symmetrical drive char acteristics with both high sink and source capability. As inputs, Port B pins that are

externally pulled low will source current if the pull-up resistors are ac tivated. The Port B pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3

(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4

GND

VCC

PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)

PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)

PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)

PDIP/SOIC/TSSOP

QFN/MLF

DNC

GND

DNC

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

NOTE: TSSOP only for ATtiny45/V

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3

DNC

(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4

VCC

PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)

DNC

PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)

PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)

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Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions

of Port B” on page 60.

On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility

Mode for supporting the backward compatibility with ATtiny15.

1.1.4 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock

is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 21-4

on page 165. Shorter pulses are not guaranteed to generate a reset.

The reset pi n can also be used as a (weak) I/O pin.

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2. Overview

The ATtiny25/45 /85 is a low-power CM OS 8-bit micro contr oller based on the AVR enhanced RISC architecture. By

executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1

MIPS per MHz allowing the system designer to optimize power consumptio n versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are

directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one

single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

PROGRAM

COUNTER

CALIBRATED

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH SRAM

MCU CONTROL

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTER0

SERIAL

UNIVERSAL

INTERFACE

TIMER/

COUNTER1

INSTRUCTION

DECODER

DATA DIR.

REG.PORT B

DATA REGISTER

PORT B

PROGRAMMING

LOGIC

TIMING AND

CONTROL

MCU STATUS

STATUS

ALU

PORT B DRIVERS

PB[0:5]

VCC

GND

CONTROL

LINES

8-BIT DATABUS

ADC /

ANALOG COMPARATOR

INTERRUPT

UNIT

DATA

EEPROM OSCILLATORS

RESET

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The ATtiny 25/45/85 pr ovides th e following fea tures: 2/ 4/8K bytes of In-System Programmable Flash, 128/256/512

bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one

8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal

and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and

three software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,

ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode saves the register con-

tents, disabling all chip functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the

CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash

allows the Program m emory to be re-programme d In-System through an SPI serial interface, by a conve ntional

non-volatile memory programmer or by an On-chip boot code running on the AVR core.

The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Com-

pilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.

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3. About

3.1 Resources

A comprehensive set of development tools, application notes and datasheets are available for download on

http://www.atmel.com/avr.

3.2 Code Examples

This documentatio n contains simple co de examples that briefly show how to use variou s parts of the de vice. These

code examples assume that the part spe cific header file is included before compilation. Be aware that not all C

compiler vendors include bit definitions in the header files and interrupt handlin g in C is compiler dependent.

Please confirm with the C compiler documentation for more details.

For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SB I” instru ction s must

be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined

with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map.

3.3 Capacitive Touch Sensing

Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcon-

trollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.

Touch sensing is easily added to any application by linking the QTouch Librar y and using the App lication Pro gram-

ming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to

retrieve channel information and determine the state of the touch sensor.

The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of

implementation, refer to the QTouch Library User Guide – also available from the Atmel website.

3.4 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20

years at 85°C or 10 0 ye ar s at 25 ° C.

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4. AVR CPU Core

4.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure cor-

rect program execution. The CPU must therefore be able to access memories, perform calculations, control

peripherals, and handle interrupts.

4.2 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

In order to maximize performance and pa rallelism, the AVR uses a Harvard architecture – with separate memories

and buses for program an d data. Instructions in the Program m emory are executed with a single level pip elining.

While one instruction is being executed, the next instruction is pre-fetched fro m the Program memory. This concept

enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable

Flash mem or y.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle

access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper-

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

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ands are output from the Register File, the operation is executed, and the result is stored back in the Register File

– in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –

enabling efficient address calculations. One of the these address pointers can also be used as an address pointer

for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,

described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single

to reflect information about the result of the operation.

Program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the

whole address space. Most AVR instructions have a single 16-bit word format, but there are also 32-bit

instructions.

During interrupts and subroutine calls, the return address Program Coun ter (PC) is stored on the Stack. The Stack

is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total

SRAM size and the us age of the SRAM. A ll user program s must in itialize th e SP in the Res et routine (before sub-

routines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data

SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in

the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have

priority in accordance with their Interrupt Vector positio n. The lower the Interrupt Vector address, the higher the

priority.

The I/O memory space contains 64 a ddresses for CPU periph eral functions as Con trol Registers, SPI, and other

I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Reg-

ister File, 0x20 - 0x5F.

4.3 ALU – Arithmetic Logic Unit

The high-perfo rmance AVR ALU operates in direct connection with all the 32 gen eral purpose working register s.

Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an

immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-

functions. Some implementations of the architecture also provide a powerful multiplier supporting both

signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

4.4 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This

information can be used for alte ring program flow in order to perform conditional ope rations. Note that the Status

remove the need fo r using the dedicated compar e instructions, re sulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning

from an interrupt. This must be handled by software.

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4.4.1 SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Globa l Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control

is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the inter-

rupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an

interrupt has occurred, and is set by the RETI instruction to enable subsequ ent interrupts. The I-bit can also be set

and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the oper-

ated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be

copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BC D arithmetic.

See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the Negative Fla g N and the Two’s Comp lement Overflow Flag V. See

the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Descrip-

tion” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N ind icates a negative result in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for

detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for

detailed information.

Bit 76543210

0x3F ITHSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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4.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required perfor-

mance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

Most of the instructions oper a ting on the Re gister File have direct access to all registers, and most of them are sin-

gle cycle instructions.

As shown in Figure 4-2 , each register is also assigned a Da ta memory ad dress, mappi ng them dir ectly into th e first

32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory

organization provides great flexibility in acces s of the registers, as the X-, Y- and Z-pointer registers can be set to

index any register in the file.

4.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit

address pointers for indirect addressing o f the data space. The three indire ct address registers X, Y, and Z are

defined as described in Figure 4-3.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

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Figure 4-3. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed displacement, automatic incre-

ment, and automatic decr ement (see the instruction set reference for details).

4.6 Stack Pointer

The Stack is mainly used for storing tempor ary data, for storing local variables and fo r storing return addresses

after interrupts and subr outine calls. T he Stack Pointer Register always points to the top of the Stack. Note that the

Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a

Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This

Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or inter-

rupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one

when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return

address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when

data is popped from the Sta ck with th e POP in stru ctio n, an d it is incremented by two when data is popped from the

Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit reg isters in the I/O spac e. The n umber of bits actually used is

implementation dependent. Note that the data space in some implementations of the AVR architecture is so small

that only SPL is needed. In this case, the SPH Register will not be present.

4.6.1 SPH and SPL — Stack Pointer Register

4.7 Instruction Execution Timing

This section describes the ge neral access timing concepts for in struction exec ution. The AVR CPU is driven by the

CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture

and the fast access Register File concept. This is the basic pipelini ng con cept to obtain up to 1 MIPS per MHz with

the corresponding unique results for functions per cos t, func tions per clocks, and functions per power-unit.

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

Bit 151413121110 9 8

0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

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Figure 4-4. The Parallel Instructio n F etc he s and In str uc tio n Exe cut ion s

Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using

two register operands is executed, and the result is stored back to the de st ina tio n re gis te r.

Figure 4-5. Single Cycle ALU Operation

4.8 Reset and Interrupt Handling

The AVR provides several di fferen t inter rupt sources. The se interrupts and the separate Reset Vector each have a

separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which

must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the

interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors.

The complete list of vectors is shown in “Interrupts” on page 48. T he list also determines the priority levels of the

different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next

is INT0 – the External Interrupt Request 0.

When an in terr up t occurs, the G lob a l In te rr u pt En able I- bit is cleared an d a ll in te rr up ts a re d i sa bled. T h e us er soft-

ware can write logic one to the I-bit to enab le nested interrupts. All enabled interrupts can then interrupt the current

interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For

these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt

handling routine, and har dware clears th e correspon ding Interru pt Flag. Inte rrupt Flags can a lso be cle ared by writ-

ing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding

interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the

flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit

is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is

set, and will then be executed by order of priority.

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

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The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not nec-

essarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will

not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction

before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when

returning from an int er ru pt rou tin e. This m ust be ha nd le d by softw ar e.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be

executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example

shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend-

ing interrupts, as shown in this example.

4.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock

cycles the Program Vector addre ss for the actual interr upt handlin g routine is executed. During this four clock cycle

period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and

this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction

is completed before the interrupt is served. If an interr upt occurs when the MCU is in slee p mode, the interr upt exe-

cution response time is increa sed by four cl ock cycles. This increa se comes in additio n to the start-up time from the

selected sleep mode.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

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A return from an interrup t handling routine takes four clock cycles. During the se four clock cycles, the Program

Counter (two bytes) is popped ba ck fro m the Stack, the St a ck Pointe r is increme nted by two, and the I-b it in SREG

is set.

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5. AVR Memories

This section describes the different memories in the ATtiny25/45/85. The AVR architecture ha s two main memo ry

spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM

Memory for data storage. All three memory spaces are linear and regular.

5.1 In-System Re-programmable Flash Program Memory

The ATtiny25/45/85 contains 2/4/8K bytes On-chip In-System Reprogrammable Flash memory for program stor-

age. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1024/2048/4096 x 16.

The Flash m emory has an endurance of a t least 10,000 write/erase cycles. The ATtiny25/45/85 Program Counter

(PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program memory locations. “Memory Program-

ming” on page 147 contains a detailed description on Flash data serial downloading using the SPI pi ns.

Constant tables can be allocated within the entire Program memory address space (see the LPM – Load Program

memory instruction description).

Timing diagrams for instruction fetch and execu tion are presented in “Instruction Execution Timing” on page 11.

Figure 5-1. Program Memory Map

5.2 SRAM Data Memory

Figure 5-2 shows how the ATtiny25 /4 5/ 85 SRAM M em o ry is org anize d .

The lower 224/352/607 Data memory locations address both the Register File, the I/O memory and the internal

data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O m emory, and

the last 128/256/512 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indi-

rect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the

indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-

When using register ind irect addressing modes with au tomatic pre-decrement and post-increment, the address

registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in

the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in “Gen-

eral Purpose Register File” on page 10.

0x0000

0x03FF/0x07FF/0x0FFF

Program Memory

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Figure 5-2. Data Memory Map

5.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM

access is performed in two clkCPU cycles as described in Figure 5-3.

Figure 5-3. On-chip Data SRAM Access Cycles

5.3 EEPROM Data Memory

The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a separate data

space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000

write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the

EEPROM Address Registers, the EEPROM Data Register, and the EEPROM C ontrol Register. For details see

“Serial Downloading” on page 151.

5.3.1 EEPROM Read/Write Access

The EEPROM Access Regis ter s ar e acc es sib le in the I/O sp ac e.

The write access times for the EEPROM are given in Table 5-1 on page 21. A self- timing function, however, lets

the user software detect when the next byte can b e written. If the user cod e contains instructions that wr ite the

EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on

Power-up/down. T his causes the device for some per iod of time to run at a voltage lower tha n specified as mini-

mum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid

problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to “Atomic

Byte Programming” on page 17 and “Split Byte Programming” on page 17 for details on this.

32 Registers

64 I/O Registers

Internal SRAM

(128/256/512 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0DF/0x015F/0x025F

0x0060

Data Memory

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

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When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When

the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.3.2 Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write

the address into the EEAR Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within

four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in

one operation and the total programming time is given in Ta ble 5-1 on page 21. The EEPE bit remains set until the

erase and write operations are completed. While the device is busy with programming, it is not possible to do any

other EEPROM operations.

5.3.3 Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires

short access time for some li mited per iod of time (typically if the p ower supply voltage falls). In or der to ta ke ad van-

tage of this method, it is required that the locations to be written have been erased before the write operation. But

since the erase and write operations are split, it is possible to do the erase operations when the system allows

doing time-critical operations (typically after Power-up).

5.3.4 Erase

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four

cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 5-1 on

page 21). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it

is not possible to do any other EEPROM operations.

5.3.5 Write

To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are

0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (program-

ming time is given in Table 5-1 on page 21). The EEPE bit remains set until the write operatio n completes. If the

location to be written has not been erased before write, the data that is stored must be consid ered as lost. While

the device is busy wit h pr ogr am m i ng , it is not po ssib le to do any oth e r E EPRO M op e ratio ns.

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the

requirements described in “OSCCAL – Oscillator Calibration Register” on page 31.

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The following code examples show one assembly and one C function for erase, write, or atomic write of the

EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no

interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r19) to data register

out EEDR, r19

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0<<EEPM0);

/* Set up address and data registers */

EEAR = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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The next code examples show assem bly and C functions for reading the EEPROM. The examples assume that

interrupts are controlled so that no interrupts will occur during execution of these functions.

5.3.6 Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupt ed be caus e the s upply volt age is t oo low for the CPU

and the EEPROM to operate pro per ly. These issue s are the same as for boar d leve l systems using EEPROM, and

the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write

sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute

instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by

enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the

needed detection level, an external low VCC reset protection circuit can be used. If a reset occurs while a write

operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

5.4 I/O Memory

The I/O space de fin itio n of th e ATtiny25/45/85 is show n in “Register Summary” on page 200.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

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All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the

LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers

and the I/O space. I/O Registers with in the add ress rang e 0x0 0 - 0x1F a re directly bit-a ccessible using th e SBI and

CBI instructions. In these registers, the value of single bit s can be checked by using th e SBIS and SBIC instruc-

tions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addre sse s 0 x0 0 - 0 x3F mu st b e used. When a ddr essing I/O Registers as data space using LD and ST instruc-

tions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory

addresses should never be written .

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will

only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI

and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sectio ns.

5.5 Register Description

5.5.1 EEARH – EEPROM Addr ess Register

• Bits 7:1 – Res: Reserved Bits

These bits are reserved for future use and will always read as zero.

• Bits 0 – EEAR8: EEPROM Address

This is the most significant EEPROM address bit of ATtiny85. In devices with less EEPROM, i.e.

ATtiny25/ATtiny45, this bit is reserved and will always read zero. The initial value of the EEPROM Address Regis-

ter (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed.

5.5.2 EEARL – EEPROM Address Register

• Bit 7 – EEAR7: EEPROM Address

This is the most significant EEPROM address bit of ATtiny45. In devices with less EEPROM, i.e. ATtiny25, this bit

is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and

a proper value must therefore be written before the EEPROM is accessed.

• Bits 6:0 – EEAR[6:0]: EEPROM Address

These are the (low) bits of the EEPROM Address Register. The EEPROM data bytes are addressed linearly in the

range 0...(128/256/512-1). The initial value of EEAR is undefined and a proper value must be therefore be written

before the EEPROM may be accessed.

Bit 76543210

0x1F – – – – – – –EEAR8EEARH

Read/Write RRRRRRRR/W

Initial Value0000000X/0

Bit

0x1E EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

Rear/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value XXXXXXXX

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5.5.3 EEDR – EEPROM Data Register

• Bits 7:0 – EEDR[7:0]: EEPROM Data

For the EEPROM write opera tion the EEDR Register contains the data to be written to the EEPROM in the a ddress

given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the

EEPROM at the address given by EEAR.

5.5.4 EECR – EEPROM Control Register

• Bit 7 – Res: Reser ved Bit

This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility with future AVR

devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reser ved Bit

This bit is reserved in the ATtiny25/45/85 and will always read as zero.

• Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writ-

ing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value)

or to split the Erase a nd Write operations in two different operation s. The Programming times for the diffe rent

modes are shown in Table 5-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn

bits will be reset to 0b00 unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero dis-

ables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is

ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If

EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware

clears the bit to zero after four clock cycles.

Bit 76543210

0x1D EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x1C – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

Table 5-1. EEPROM Mode Bits

EEPM1 EEPM0 Programming

Time Operation

0 0 3.4 ms Erase and Write in one operation (Atomic Operation)

0 1 1.8 ms Erase Only

1 0 1.8 ms Write Only

1 1 – Reserved for future use

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• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is

written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to

one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time

has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles

before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set

up in the EEAR Register, the EERE bit must be written to one to trigger the EEPR OM read. The EEPROM read

access takes one instruction, and the requested data is available immediate ly. When the EEPROM is read, the

CPU is halted for four cycles befor e the next instruction is executed. The user should poll the EEPE bit before start-

ing the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change

the EEAR Register.

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6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be

active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted

by using different sleep modes, as described in “Power Manage ment and Sleep Mode s” on page 34. T he clock

systems are detailed below.

Figure 6-1. Clock Distribution

6.1.1 CPU Clock – clkCPU

The CPU clock is routed to parts of the system concer ned with operation of the AVR core. Examples of such mod-

ules are the General Purpose Register F ile, the Status Register and the Data m emory holding the Stack Pointer.

Halting the CPU clock inhibits the core from performing general operations and calculations.

6.1.2 I/O Cloc k – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the

External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing

such interrupts to be detected even if the I/O clock is halted.

6.1.3 Flash Clock – clkFLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the

CPU clock.

General I/O

Modules CPU Core RAM

clk

I/O

AVR Clock

Control Unit

clk

CPU

Flash and

EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Calibrated RC

Oscillator

External Clock

ADC

clk

ADC

Crystal

Oscillator

Low-Frequency

Crystal Oscillator

System Clock

Prescaler

PLL

Oscillator

clk

PCK

clk

PCK

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6.1.4 ADC Clock – clkADC

The ADC is prov ide d with a d ed ica te d c lock domain. Th is a llows halting the CPU and I/O clocks in order to reduce

noise generated by digita l circuitry. This gives more accurate ADC conversion results.

6.1.5 Internal PLL for Fast Peripheral Cloc k Generation - clkPCK

The internal PL L in ATtiny25/45/85 generate s a clock frequency that is 8x multiplie d from a source input. By

default, the PLL uses the output of the internal, 8.0 MHz RC oscillator as source. Alternatively, if bit LSM of

PLLCSR is set the PLL will use the output of the RC oscillator divided by two. Thus the output of the PLL, the fast

peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock

source for Timer/Counter1 or as a system clock. See Figure 6-2. The frequency of the fast pe ripheral clock is

divided by two when LSM of PLLCSR is set, resulting in a clock frequency of 32 MHz. Note, that LSM can not be

set if PLLCLK is used as system clock.

Figure 6-2. PCK Clocking System.

The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will adjust the fast

peripheral clock at the same time . However, even if the RC oscillator is taken to a higher frequency than 8 MHz,

the fast peripheral clock frequency saturates at 85 MHz (worst case) and remains oscillating at the maximum fre-

quency. It should be noted that the PLL in this case is not locked any longer with the RC oscillator clock. Therefore,

it is recommended n ot to take the OSCCAL ad justments to a higher frequen cy than 8 MHz in or der to ke ep the PLL

in the correct operating r ange.

The internal PLL is enabled when:

• The PLLE bit in the register PLLCSR is set.

• The CKSEL fuse is programmed to ‘0001’.

• The CKSEL fuse is programmed to ‘0011’.

The PLLCSR bit PLOCK is set when PLL is locked.

Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.

6.1.6 Internal PLL in ATtiny15 Compatibility Mode

Since ATtiny25/45/85 is a migration device for ATtiny15 users there is an ATtiny15 compatibility mode for back-

ward compatibility. The ATtiny15 compatibility mode is selected by programming the CKSEL fuses to ‘0011’.

In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down to 6.4 MHz and the

multiplication factor of the PLL is set to 4x. See Figure 6-3. With these adjustments the clocking system is

ATtiny15-compatible and the resulting fast peripheral clock has a frequency of 25.6 MHz (same as in ATtiny15).

1/2

8 MHz

LSM

8.0 MHz

OSCILLATOR PLL

CKSEL[3:0]PLLEOSCCAL

4 MHz

1/4

LOCK

DETECTOR

PRESCALER

CLKPS[3:0]

SYSTEM

CLOCK

PLOCK

PCK

OSCILLATORS

XTAL1

XTAL2

64 / 32 MHz

8 MHz

16 MHz

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Figure 6-3. PCK Clocking System in ATtiny15 Compatibility Mode.

Note that low speed mode is not implemented in ATtiny15 compatibility mode.

6.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from

the selected source is input to the AVR clock generator, and routed to the approp riate modules.

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

2. The device is shipped with this option selected.

3. This will select ATtiny15 Compatibility Mode, where system clock is divided by four , resulting in a 1.6 MHz clock fre-

quency. For more inormation, see “Calibrated Internal Oscillator” on page 27.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from

Power-down, the se lected clock source is used to time the start-up, ensuring stable Oscillator operatio n before

instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to

reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time

part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2.

1/2

1.6 MHz

6.4 MHz

OSCILLATOR

PLL

PLLEOSCCAL

3.2 MHz

LOCK

DETECTOR

SYSTEM

CLOCK

PLOCK

PCK

25.6 MHz

1/4

Table 6-1. Device Clocking Options Select

Device Clocking Option CKSEL[3:0](1)

External Clock (see page 26) 0000

High Frequency PLL Clock (see page 26) 0001

Calibrated Internal Oscillator (see page 27) 0010(2)

Calibrated Internal Oscillator (see page 27) 0011(3)

Internal 128 kHz Oscillator (see page 28) 0100

Low-Frequency Crystal Oscillator (see page 29)0110

Crystal Oscillator / Ceramic Resonator (see page 29) 1000 – 1111

Reserved 0101, 0111

Table 6-2. Number of Watchdog Oscillator Cycles

Typ Time-out Number of Cycles

4 ms 512

64 ms 8K (8,192)

ATtiny25/45/85 [DATASHEET]

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6.2.1 External Clock

To drive the device from an extern al clock source, CLKI sh ould be drive n as shown in Figure 6-4 . To ru n the d evice

on an external clock, the CKSEL Fuses must be programmed to “00”.

Figure 6-4. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-3.

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure

stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to

unpredictable beh avior. It is required to ensure that the MCU is kept in Reset during such change s in the clock

frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency

while still ensuring stable operation. Refer to “System Clock Prescaler” on page 31 for details.

6.2.2 High Frequency PLL Clock

There is an internal PLL th at provides nominally 64 MH z clock rate locked to the RC Oscillator for the us e of the

Peripheral Timer /Counter1 and for the system clo ck sour ce. When selected as a system clock sour ce, by program-

ming the CKSEL fuses to ‘0001’, it is divided by four like shown in Table 6-4.

When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-5.

Table 6-3. Start-up Times for the External Clock Selection

SUT[1:0] Start-up T ime from

Power-down Additional Delay from

Reset Recommended Usage

00 6 CK 14CK BOD enabled

01 6 CK 14CK + 4 ms Fast rising power

10 6 CK 14CK + 64 ms Slowly rising power

11 Reserved

EXTERNAL

CLOCK

SIGNAL

CLKI

GND

Table 6-4. High Frequency PLL Clock Operating Modes

CKSEL[3:0] Nominal Frequency

0001 16 MHz

Table 6-5. Start-up Times for the High Frequency PLL Clock

SUT[1:0] Start-up T ime from

Power Down Additional Delay from

Power-On Reset (VCC = 5.0V) Recommended

usage

00 14CK + 1K (1024) CK + 4 ms 4 ms BOD enabled