FS32K148UJT0VLQT - NXP SEMICONDUCTORS

S32K1XX

S32K1xx Data Sheet

Notes

• Technical information for the S32K116 and S32K118

device families is preliminary until these devices

achieve qualification.

• Following two are the available attachments with

Datasheet:

– S32K1xx_Orderable_Part_Number_ List.xlsx

– S32K1xx_Power_Modes_Configuration.xlsx

Key Features

• Operating characteristics

– Voltage range: 2.7 V to 5.5 V

– Ambient temperature range: -40 °C to 105 °C for

HSRUN mode, -40 °C to 125 °C for RUN mode

• Arm™ Cortex-M4F/M0+ core, 32-bit CPU

– Supports up to 112 MHz frequency (HSRUN mode)

with 1.25 Dhrystone MIPS per MHz

– Arm Core based on the Armv7 Architecture and

Thumb®-2 ISA

– Integrated Digital Signal Processor (DSP)

– Configurable Nested Vectored Interrupt Controller

(NVIC)

– Single Precision Floating Point Unit (FPU)

• Clock interfaces

– 4 - 40 MHz fast external oscillator (SOSC)

– 48 MHz Fast Internal RC oscillator (FIRC)

– 8 MHz Slow Internal RC oscillator (SIRC)

– 128 kHz Low Power Oscillator (LPO)

– Up to 112 MHz (HSRUN) System Phased Lock

Loop (SPLL)

– Up to 50 MHz DC external square wave input clock

– Real Time Counter (RTC)

• Power management

– Low-power Arm Cortex-M4F/M0+ core with

excellent energy efficiency

– Power Management Controller (PMC) with multiple

power modes: HSRUN, RUN, STOP, VLPR, and

VLPS. Note: CSEc (Security) or EEPROM writes/

erase will trigger error flags in HSRUN mode (112

MHz) because this use case is not allowed to

execute simultaneously. The device will need to

switch to RUN mode (80 Mhz) to execute CSEc

(Security) or EEPROM writes/erase.

– Clock gating and low power operation supported on

specific peripherals.

• Memory and memory interfaces

– Up to 2 MB program flash memory with ECC

– 64 KB FlexNVM for data flash memory with ECC

and EEPROM emulation. Note: CSEc (Security) or

EEPROM writes/erase will trigger error flags in

HSRUN mode (112 MHz) because this use case is

not allowed to execute simultaneously. The device

will need to switch to RUN mode (80 MHz) to

execute CSEc (Security) or EEPROM writes/erase.

– Up to 256 KB SRAM with ECC

– Up to 4 KB of FlexRAM for use as SRAM or

EEPROM emulation

– Up to 4 KB Code cache to minimize performance

impact of memory access latencies

– QuadSPI with HyperBus™ support

• Mixed-signal analog

– Up to two 12-bit Analog-to-Digital Converter

(ADC) with up to 32 channel analog inputs per

module

– One Analog Comparator (CMP) with internal 8-bit

Digital to Analog Converter (DAC)

• Debug functionality

– Serial Wire JTAG Debug Port (SWJ-DP) combines

– Debug Watchpoint and Trace (DWT)

– Instrumentation Trace Macrocell (ITM)

– Test Port Interface Unit (TPIU)

– Flash Patch and Breakpoint (FPB) Unit

• Human-machine interface (HMI)

– Up to 156 GPIO pins with interrupt functionality

– Non-Maskable Interrupt (NMI)

NXP Semiconductors Document Number S32K1XX

Data Sheet: Advance Information Rev. 7, 04/2018

This document contains information on a pre-production product. Specifications

and pre-production information herein are subject to change without notice.

• Communications interfaces

– Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support

and low power availability

– Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability

– Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability

– Up to three FlexCAN modules (with optional CAN-FD support)

– FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc).

– Up to one 10/100Mbps Ethernet with IEEE1588 support and two Synchronous Audio Interface (SAI) modules.

• Safety and Security

– Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the

SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will

trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The

device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.

– 128-bit Unique Identification (ID) number

– Error-Correcting Code (ECC) on flash and SRAM memories

– System Memory Protection Unit (System MPU)

– Cyclic Redundancy Check (CRC) module

– Internal watchdog (WDOG)

– External Watchdog monitor (EWM) module

• Timing and control

– Up to eight independent 16-bit FlexTimers (FTM) modules, offering up to 64 standard channels (IC/OC/PWM)

– One 16-bit Low Power Timer (LPTMR) with flexible wake up control

– Two Programmable Delay Blocks (PDB) with flexible trigger system

– One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels

– 32-bit Real Time Counter (RTC)

• Package

– 32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA, 144-pin LQFP, 176-pin LQFP package

options

• 16 channel DMA with up to 63 request sources using DMAMUX

S32K1xx Data Sheet, Rev. 7, 04/2018

2 NXP Semiconductors

Table of Contents

1 Block diagram.................................................................................... 4

2 Feature comparison............................................................................ 5

3 Ordering information......................................................................... 7

3.1 Selecting orderable part number ...............................................7

3.2 Ordering information ................................................................8

4 General............................................................................................... 9

4.1 Absolute maximum ratings........................................................9

4.2 Voltage and current operating requirements..............................10

4.3 Thermal operating characteristics..............................................11

4.4 Power and ground pins.............................................................. 12

4.5 LVR, LVD and POR operating requirements............................14

4.6 Power mode transition operating behaviors.............................. 15

4.7 Power consumption................................................................... 16

4.8 ESD handling ratings.................................................................20

4.9 EMC radiated emissions operating behaviors........................... 20

5 I/O parameters....................................................................................21

5.1 AC electrical characteristics...................................................... 21

5.2 General AC specifications......................................................... 21

5.3 DC electrical specifications at 3.3 V Range.............................. 22

5.4 DC electrical specifications at 5.0 V Range.............................. 23

5.5 AC electrical specifications at 3.3 V range .............................. 24

5.6 AC electrical specifications at 5 V range ................................. 24

5.7 Standard input pin capacitance.................................................. 25

5.8 Device clock specifications....................................................... 25

6 Peripheral operating requirements and behaviors..............................26

6.1 System modules.........................................................................26

6.2 Clock interface modules............................................................ 26

6.2.1 External System Oscillator electrical specifications....26

6.2.2 External System Oscillator frequency specifications . 28

6.2.3 System Clock Generation (SCG) specifications..........30

6.2.3.1 Fast internal RC Oscillator (FIRC)

electrical specifications............................ 30

6.2.3.2 Slow internal RC oscillator (SIRC)

electrical specifications ........................... 30

6.2.4 Low Power Oscillator (LPO) electrical specifications

......................................................................................31

6.2.5 SPLL electrical specifications .....................................31

6.3 Memory and memory interfaces................................................31

6.3.1 Flash memory module (FTFC) electrical

specifications................................................................31

6.3.1.1 Flash timing specifications —

commands................................................ 31

6.3.1.2 Reliability specifications..........................36

6.3.2 QuadSPI AC specifications..........................................37

6.4 Analog modules.........................................................................41

6.4.1 ADC electrical specifications...................................... 41

6.4.1.1 12-bit ADC operating conditions.............41

6.4.1.2 12-bit ADC electrical characteristics....... 43

6.4.2 CMP with 8-bit DAC electrical specifications............ 45

6.5 Communication modules...........................................................49

6.5.1 LPUART electrical specifications............................... 49

6.5.2 LPSPI electrical specifications.................................... 49

6.5.3 LPI2C electrical specifications.................................... 55

6.5.4 FlexCAN electical specifications.................................56

6.5.5 SAI electrical specifications........................................ 56

6.5.6 Ethernet AC specifications.......................................... 58

6.5.7 Clockout frequency......................................................61

6.6 Debug modules.......................................................................... 61

6.6.1 SWD electrical specofications .................................... 61

6.6.2 Trace electrical specifications......................................63

6.6.3 JTAG electrical specifications..................................... 64

7 Thermal attributes.............................................................................. 67

7.1 Description.................................................................................67

7.2 Thermal characteristics..............................................................67

7.3 General notes for specifications at maximum junction

temperature................................................................................ 72

8 Dimensions.........................................................................................73

8.1 Obtaining package dimensions .................................................73

9 Pinouts................................................................................................74

9.1 Package pinouts and signal descriptions....................................74

10 Revision History.................................................................................74

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 3

1 Block diagram

Following figures show superset high level architecture block diagrams of S32K14x

series and S32K11x series respectively. Other devices within the family have a subset of

the features. See Feature comparison for chip specific values.

Mux

Trace

port

Crossbar switch (AXBS-Lite)

eDMA

DMA

MUX

Core

Peripheral bus controller

CRC

WDOG

M0 M1

DSP

NVIC

ITM

FPB

DWT

AWIC

SWJ-DP

TPIU

JTAG &

Serial Wire

Arm Cortex M4F

ICODE

DCODE

AHB-AP

PPB

System

GPIO

Mux

FPU Clock

SPLL

LPO

128 kHz

Async

512B

TCD

LPIT

LPI2C FlexIO

Flash memory

controller

Code flash

Data flash

Low Power

Timer

12-bit ADC

TRGMUX

LPUART

LPSPI

FlexCAN FlexTimer

PDB

generation

LPIT

Peripherals present

on all S32K devices

Peripherals present

on selected S32K devices

Key:

Device architectural IP

on all S32K devices

FIRC

48 MHz

ENET

SAI

SOSC

8-40 MHz

(see the "Feature Comparison"

memory memory

4-40 MHz

QuadSPI

RTC

CMP

8-bit DAC

SIRC

8 MHz

FlexRAM/

SRAM

1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from

accessing restricted memory regions. This system MPU provides memory protection at the

level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned

different access rights to each protected memory region. The Arm M4 core version in this family

does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory

accesses. In this document, the term MPU refers to NXP’s system MPU.

2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"

chapter of the S32K1xx Series Reference Manual.

section)

ERM

EWM

MCM

Lower region

Upper region

Main SRAM2

Code Cache

System MPU1

EIM

LMEM

controller

LMEM

QSPI

CSEc3

System MPU1System MPU1System MPU1

3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this

use case is not allowed to execute simultaneously. The device need to switch to RUN mode (80 MHz) to

execute CSEc (Security) or EEPROM writes/erase.

Figure 1. High-level architecture diagram for the S32K14x family

Block diagram

S32K1xx Data Sheet, Rev. 7, 04/2018

4 NXP Semiconductors

Crossbar switch (AXBS-Lite)

eDMA

DMA

MUX

SW-DP

Unified Bus

Serial Wire

AHBLite

AWIC

S0 S1

Clock

LPO

128 kHz

generation

FIRC

48 MHz

SOSC

4-40 MHz

SIRC

8 MHz

Peripheral bus controller

CRC

WDOG

LPIT

LPI2C FlexIO Low Power

Timer

12-bit ADC

TRGMUX

LPUART

LPSPI

FlexCAN FlexTimer

PDB

LPIT

RTC

CMP

8-bit DAC

ERM

CMU GPIO

M0 M2

Flash memory

controller

Data flash

memory

FlexRAM/

SRAM2

Code flash

memory

EIM

SRAM2

IO PORT

NVIC

PPB

MTB+DWT

BPU

AHB-AP

Arm Cortex M0+

Peripherals present

on all S32K devices

Peripherals present

on selected S32K devices

Key:

Device architectural IP

on all S32K devices

(see the "Feature Comparison"

1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from

accessing restricted memory regions. This system MPU provides memory protection at the

level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned

different access rights to each protected memory region. The Arm M0+ core version in this family

does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory

accesses. In this document, the term MPU refers to NXP’s system MPU.

2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"

chapter of the S32K1xx Series Reference Manual.

section)

IO PORT

CSEc

System MPU1System MPU1

Figure 2. High-level architecture diagram for the S32K11x family

2Feature comparison

The following figure summarizes the memory, peripherals and packaging options for the

S32K1xx devices. All devices which share a common package are pin-to-pin compatible.

Feature comparison

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 5

2 KB (up to 32 KB D-Flash)

EEPROM emulated by FlexRAM1

2 KB

FlexRAM (also available as system RAM)

Cache

25 KB

System RAM (including FlexRAM and MTB) 17 KB

Flash 128 KB 256 KB

2.7 - 5.5 V

Single supply voltage

HSRUN mode1

Watchdog 1x

Number of I/Os up to 43 up to 58

Memory Protection Unit (MPU)

K116 K118

Parameter

Peripheral speed

CRC module

IEEE-754 FPU

Arm® Cortex™-M0+

Core

External Watchdog Monitor (EWM)

DMA

Crossbar

capable up to ASIL-B

ISO 26262

Cryptographic Services Engine (CSEc)1

48 MHz

Frequency

up to 48 MHz

Error Correcting Code (ECC)

Low Power Timer (LPTMR)

Low Power Interrupt Timer (LPIT)

LEGEND:

Not implemented

Available on the device

1 No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when

device is running at HSRUN mode (112MHz) or VLPR mode.

2 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash.

3 4 KB (up to 512 KB D-Flash as a part of 2 MB Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB

of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.

4 Only for Boundary Scan Register

5 See Dimensions section for package drawings

Trigger mux (TRGMUX)

Real Time Counter (RTC)

FlexTimer (16-bit counter) 8 channels 2x (16)

External memory interface

1x (16)

10/100 Mbps IEEE-1588 Ethernet MAC

12-bit SAR ADC (1 Msps each)

FlexIO (8 pins configurable as UART, SPI, I2C, I2S)

Low Power I2C (LPI2C)

Low Power UART/LIN (LPUART)

(Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602)

SWD, MTB (1 KB), JTAG4

Debug & trace

NXP S32 Design Studio (GCC) + SDK,

IAR, GHS, Arm®, Lauterbach, iSystems

48-pin LQFP

64-pin LQFP

Packages5

Ecosystem

(IDE, compiler, debugger)

32-pin QFN

48-pin LQFP

FlexCAN

(CAN-FD ISO/CD 11898-1) 1x

(1x with FD)

1x 2x

Low Power SPI (LPSPI)

Serial Audio Interface (AC97, TDM, I2S)

Comparator with 8-bit DAC 1x

Programmable Delay Block (PDB) 1x

S32K11x S32K14x

K142 K144 K146 K148

SWD, JTAG (ITM, SWV, SWO)

NXP S32 Design Studio (GCC) + SDK,

IAR, GHS, Arm®, Lauterbach, iSystems

64-pin LQFP

100-pin LQFP

64-pin LQFP

100-pin LQFP

100-pin MAPBGA

64-pin LQFP

100-pin MAPBGA

100-pin LQFP

144-pin LQFP

100-pin MAPBGA

144-pin LQFP

176-pin LQFP

SWD, JTAG

(ITM, SWV,

SWO), ETM

1x (64)

2x (16) 2x (24) 2x (32)

2x 3x

1x 2x

(1x with FD) 3x

(2x with FD) 3x

(3x with FD)

(1x with FD)

2x 3x

1x (73) 1x (81)

80 MHz (RUN mode) or 112 MHz (HSRUN mode)1

Arm® Cortex™-M4F

capable up to ASIL-B

up to 112 MHz (HSRUN)

4 KB (up to 64 KB D-Flash)

4 KB

32 KB 48/64 KB 96/128 KB 192/256 KB

-40oC to +85oC / +105oC / +125oC

256 KB 512 KB 1 MB 2 MB2

2.7 - 5.5 V

up to 89 up to 128 up to 156

4x (32) 6x (48) 8x (64)

QuadSPI incl.

HyperBus™

See footnote 3

MemoryAnalog Timer

Communication

IDEs

Other System

-40oC to +85oC / +105oC / +125oC

Ambient Operation Temperature (Ta)

1x (43) 1x (45)

1x (13)

FIRC CMU

Low power modes

Figure 3. S32K1xx product series comparison

Feature comparison

S32K1xx Data Sheet, Rev. 7, 04/2018

6 NXP Semiconductors

Ordering information

3.1 Selecting orderable part number

Not all part number combinations are available. See the attachment

S32K1xx_Orderable_Part_Number_ List.xlsx attached with the Datasheet for a list of

standard orderable part numbers.

Ordering information

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 7

3.2 Ordering information

F/P S32 K 1 0 0 X Y T0 M LH R

Product status

Product type/brand

Product line

Series/Family

(including generation)

Core platform/

Performance

Memory size

Ordering option 1: Letter

Ordering option 2: Letter

Wafer Fab and

revision

Temperature

Package

Tape and Reel

Product status

P: Prototype

F: Qualified

Product type/brand

S32: Automotive 32-bit MCU

Product line

K: Arm Cortex MCUs

Series/Family

1: 1st product series

2: 2nd product series

Core platform/Performance

1: Arm Cortex M0+

4: Arm Cortex M4F

Memory size

S32K11x

2468

S32K14x 256K 512K

128K

256K

Ordering option

X: Speed

B: 48 MHz without DMA (S32K11x only)

L: 48 MHz with DMA (S32K11x only)

H: 80 MHz

U1: 112 MHz (Not valid with M temperature/125C)

Y: Optional feature

R: Max. RAM

F: CAN FD, FlexIO, max. RAM

A1: CAN FD, FlexIO, Security, max. RAM

E: Ethernet, Audio, max. RAM (S32K148 only)

J1: CAN FD, FlexIO, Security, Ethernet,

Audio, max. RAM (S32K148 only)

Wafer, Fab and revision

Fx: ATMC2

Tx: GF

XX: Flex #2

x0: 1st revision

Temperature

V: -40C to 105C

M: -40C to 125C

W: -40C to 150C2

Tape and Reel

T: Trays/Tubes

R: Tape and Reel

Package

LQFP

32 FM

Pins QFN BGA

100

144

176

1. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to

execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.

2. Not supported yet

3. Part numbers no longer offered as standard include:

Ordering Option X (M:64MHz); Ordering Option Y (N: no optional features; S: Security, max. RAM); Temperature (C: -40C to 85C)

NOTE

Not all part number combinations are available. See S32K1xx_Orderable_Part_Number_List.xlsx

attached with the Datasheet for list of standard orderable parts.

Figure 4. Ordering information

Ordering information

S32K1xx Data Sheet, Rev. 7, 04/2018

8 NXP Semiconductors

General

4.1 Absolute maximum ratings

NOTE

• Functional operating conditions appear in the DC electrical

characteristics. Absolute maximum ratings are stress

ratings only, and functional operation at the maximum

values is not guaranteed. See footnotes in the following

table for specific conditions.

• Stress beyond the listed maximum values may affect device

reliability or cause permanent damage to the device.

• All the limits defined in the datasheet specification must be

honored together and any violation to any one or more will

not guarantee desired operation.

• Unless otherwise specified, all maximum and minimum

values in the datasheet are across process, voltage, and

temperature.

Table 1. Absolute maximum ratings

Symbol Parameter Conditions1Min Max Unit

VDD22.7 V - 5. 5V input supply voltage — -0.3 5.8 3V

VREFH 3.3 V / 5.0 V ADC high reference voltage — -0.3 5.8 3V

IINJPAD_DC_ABS4Continuous DC input current (positive /

negative) that can be injected into an I/O

— -3 +3 mA

VIN_DC Continuous DC Voltage on any I/O pin

with respect to VSS

— -0.8 5.85V

IINJSUM_DC_ABS Sum of absolute value of injected currents

on all the pins (Continuous DC limit)

— — 30 mA

Tramp6ECU supply ramp rate — 0.5 V/min 500 V/ms —

Tramp_MCU7MCU supply ramp rate — 0.5 V/min 100 V/ms —

TA8Ambient temperature — -40 125 °C

TSTG Storage temperature — -55 165 °C

VIN_TRANSIENT Transient overshoot voltage allowed on

I/O pin beyond VIN_DC limit

— — 6.8 9V

1. All voltages are referred to VSS unless otherwise specified.

2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

3. 60 s lifetime – No restrictions i.e. The part can switch.

10 hours lifetime – Device in reset i.e. The part cannot switch.

General

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 9

4. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.

5. While respecting the maximum current injection limit

6. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both

maximum absolute maximum ramp rate and typical operating conditions.

7. This is the MCU supply ramp rate and the ramp rate assumes that the S32K1xx HW design guidelines in AN5426 are

followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.

8. TJ (Junction temperature)=135 °C. Assumes TA=125 °C for RUN mode

TJ (Junction temperature)=125 °C. Assumes TA=105 °C for HSRUN mode

• Assumes maximum θJA for 2s2p board. See Thermal characteristics

9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)

4.2 Voltage and current operating requirements

NOTE

Device functionality is guaranteed up to the LVR assert level,

however electrical performance of 12-bit ADC, CMP with 8-bit

DAC, IO electrical characteristics, and communication modules

electrical characteristics would be degraded when voltage drops

below 2.7 V

Table 2. Voltage and current operating requirements 1

Symbol Description Min. Max. Unit Notes

VDD2Supply voltage 2.735.5 V 4

VDD_OFF Voltage allowed to be developed on VDD

pin when it is not powered from any

external power supply source.

0 0.1 V

VDDA Analog supply voltage 2.7 5.5 V 4

VDD – VDDA VDD-to-VDDA differential voltage – 0.1 0.1 V 4

VREFH ADC reference voltage high 2.7 VDDA + 0.1 V 5

VREFL ADC reference voltage low -0.1 0.1 V

VODPU Open drain pullup voltage level VDD VDD V6

IINJPAD_DC_OP7Continuous DC input current (positive /

negative) that can be injected into an I/O

-3 +3 mA

IINJSUM_DC_OP Continuous total DC input current that can

be injected across all I/O pins such that

there's no degradation in accuracy of

analog modules: ADC and ACMP (See

section Analog Modules)

— 30 mA

1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise

stated.

2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

3. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to

operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.

4. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for

reference supply design for SAR ADC.

General

S32K1xx Data Sheet, Rev. 7, 04/2018

10 NXP Semiconductors

5. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V

6. Open drain outputs must be pulled to VDD.

7. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.

4.3 Thermal operating characteristics

Table 3. Thermal operating characteristics for 64 LQFP, 100 LQFP, and 100 MAP-BGA

packages.

Symbol Parameter Value Unit

Min. Typ. Max.

TA C-Grade Part Ambient temperature under bias −40 — 851℃

TJ C-Grade Part Junction temperature under bias −40 — 1051℃

TA V-Grade Part Ambient temperature under bias −40 — 1051℃

TJ V-Grade Part Junction temperature under bias −40 — 1251℃

TA M-Grade Part Ambient temperature under bias −40 — 1252℃

TJ M-Grade Part Junction temperature under bias −40 — 1352℃

1. Values mentioned are measured at ≤ 112 MHz in HSRUN mode.

2. Values mentioned are measured at ≤ 80 MHz in RUN mode.

General

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 11

4.4 Power and ground pins

VDD

VDDA

VREFH

VREFL

VSSA/VSS

VDD

VSS

VDD

VSS

100 LQFP

Package

VDD

VSS

VREFH/VDDA/VDD

VREFL/VSSA/VSS

32 QFN

Package

CDEC

CREF

CDEC

VSS

VDD

CDEC

VSS

VDD

144 LQFP

Package

VDD

VSS

CDEC

VDD

VSS

VDD

VSS

VDD

176 LQFP

Package

CDEC

VDD

VSS

CDEC

VSS

VDD

CDEC

VDD

VSS

CDEC

VDD

VSS

CDEC

VSS

VDD

CDEC

VDD

VDDA

VREFH

VREFL

VSS

CDEC

CREF

CDEC

VDD

VSS

CDEC

VSSA/VSS

VDD

VDDA

VREFH

VREFL

VSS

CDEC

CREF

CDEC

VDD

VSS

CDEC

VSSA/VSS

VDD

VSS

VDDA

VREFH

VREFL/VSSA/VSS

64 LQFP

Package

CREF

CDEC

VDD

CDEC

VDD

VSS

VREFH/VDDA

VREFL/VSSA/VSS

48 LQFP

Package

CREF

CDEC

VDD

CDEC

NOTE: VDD and VDDA must be shorted to a common source on PCB

Figure 5. Pinout decoupling

General

S32K1xx Data Sheet, Rev. 7, 04/2018

12 NXP Semiconductors

Table 4. Supplies decoupling capacitors 1, 2

Symbol Description Min. 3Typ. Max. Unit

CREF, 4, 5ADC reference high decoupling capacitance 70 100 — nF

CDEC5, 6, 7Recommended decoupling capacitance 70 100 — nF

1. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for

reference supply design for SAR ADC. All VSS pins should be connected to common ground at the PCB level.

2. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type).

3. Minimum recommendation is after considering component aging and tolerance.

4. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel.

5. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins.

6. Contact your local Field Applications Engineer for details on best analog routing practices.

7. The filtering used for decoupling the device supplies must comply with the following best practices rules:

• The protection/decoupling capacitors must be on the path of the trace connected to that component.

• No trace exceeding 1 mm from the protection to the trace or to the ground.

• The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm).

• The ground of the protection is connected as short as possible to the ground plane under the integrated circuit.

General

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 13

PMC

VDD

VFlash = 3.6 V nominal

VCORE = 1.2 V/1.4 V nominal

System RAM

TCD RAM

I/D Cache

EEE RAM

LV SOG

FIRC

SIRC

SPLL

VSS

SOSC

GPIO

Flash

Pads

ADC CMP

VDDA

VSSA

VREFH

VREFL

*Note: VSSA and VSS are shorted at package level

VOSC = 3.3 V nominal

Figure 6. Power diagram

4.5 LVR, LVD and POR operating requirements

Table 5. VDD supply LVR, LVD and POR operating requirements

Symbol Description Min. Typ. Max. Unit Notes

VPOR Rising and falling VDD POR detect voltage 1.1 1.6 2.0 V

VLVR LVR falling threshold (RUN, HSRUN, and

STOP modes)

2.50 2.58 2.7 V

VLVR_HYST LVR hysteresis — 45 — mV 1

VLVR_LP LVR falling threshold (VLPS/VLPR modes) 1.97 2.22 2.44 V

VLVD Falling low-voltage detect threshold 2.8 2.875 3 V

VLVD_HYST LVD hysteresis — 50 — mV 1

Table continues on the next page...

General

S32K1xx Data Sheet, Rev. 7, 04/2018

14 NXP Semiconductors

Table 5. VDD supply LVR, LVD and POR operating requirements (continued)

Symbol Description Min. Typ. Max. Unit Notes

VLVW Falling low-voltage warning threshold 4.19 4.305 4.5 V

VLVW_HYST LVW hysteresis — 75 — mV 1

VBG Bandgap voltage reference 0.97 1.00 1.03 V

1. Rising threshold is the sum of falling threshold and hysteresis voltage.

4.6 Power mode transition operating behaviors

All specifications in the following table assume this clock configuration:

• RUN Mode:

• Clock source: FIRC

• SYS_CLK/CORE_CLK = 48 MHz

• BUS_CLK = 48 MHz

• FLASH_CLK = 24 MHz

• HSRUN Mode:

• Clock source: SPLL

• SYS_CLK/CORE_CLK = 112 MHz

• BUS_CLK = 56 MHz

• FLASH_CLK = 28 MHz

• VLPR Mode:

• Clock source: SIRC

• SYS_CLK/CORE_CLK = 4 MHz

• BUS_CLK = 4 MHz

• FLASH_CLK = 1 MHz

• STOP1/STOP2 Mode:

• Clock source: FIRC

• SYS_CLK/CORE_CLK = 48 MHz

• BUS_CLK = 48 MHz

• FLASH_CLK = 24 MHz

• VLPS Mode: All clock sources disabled 1

Table 6. Power mode transition operating behaviors

Symbol Description Min. Typ. Max. Unit

tPOR After a POR event, amount of time from the point VDD

reaches 2.7 V to execution of the first instruction

across the operating temperature range of the chip.

— 325 — μs

Table continues on the next page...

1. • For S32K11x – FIRC/SOSC/FIRC/LPO

• For S32K14x – FIRC/SOSC/FIRC/LPO/SPLL

General

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 15

Table 6. Power mode transition operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit

VLPS → RUN 8 — 17 μs

STOP1 → RUN 0.07 0.075 0.08 μs

STOP2 → RUN 0.07 0.075 0.08 μs

VLPR → RUN 19 — 26 μs

VLPR → VLPS 5.1 5.7 6.5 μs

VLPS → VLPR 18.8 23 27.75 μs

RUN → Compute operation 0.72 0.75 0.77 μs

HSRUN → Compute operation 0.3 0.31 0.35 μs

RUN → STOP1 0.35 0.38 0.4 μs

RUN → STOP2 0.2 0.23 0.25 μs

RUN → VLPS 0.3 0.35 0.4 μs

RUN → VLPR 3.5 3.8 5 μs

VLPS → Asynchronous DMA Wakeup 105 110 125 μs

STOP1 → Asynchronous DMA Wakeup 1 1.1 1.3 μs

STOP2 → Asynchronous DMA Wakeup 1 1.1 1.3 μs

Pin reset → Code execution — 214 — μs

NOTE

HSRUN should only be used when frequencies in excess of 80

MHz are required. When using 80 MHz and below, RUN mode

is the recommended operating mode.

4.7 Power consumption

The following table shows the power consumption targets for the device in various mode

of operations. Attached S32K1xx_Power_Modes _Configuration.xlsx details the modes

used in gathering the power consumption data stated in the following table Table 7. For

full functionality refer to table: Module operation in available low power modes of the

Reference Manual.

General

S32K1xx Data Sheet, Rev. 7, 04/2018

16 NXP Semiconductors

Table 7. Power consumption (Typicals unless stated otherwise) 1

Chip/Device

Ambient Temperature (°C)

VLPS (μA)2, 3VLPR (mA) STOP1

(mA)

STOP2

(mA)

RUN@48

MHz (mA)

RUN@64 MHz

(mA)

RUN@80 MHz

(mA)

HSRUN@112

MHz (mA) 4

IDD/MHz (μA/MHz)5

Peripherals disabled 6

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

Peripherals enabled

S32K116 25 Typ 26 38 1.9 2.5 7 12 TBD TBD NA TBD

105 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD

Max TBD TBD TBD TBD TBD TBD TBD TBD TBD

125 Max TBD TBD TBD TBD TBD TBD TBD 40 TBD

S32K118 25 Typ 26 38 1.9 2.5 7 12 TBD TBD NA TBD

105 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD

Max TBD TBD TBD TBD TBD TBD TBD TBD TBD

125 Max TBD TBD TBD TBD TBD TBD TBD 42 TBD

S32K142 25 Typ 29 35 1.17 1.21 6.4 7.4 17.3 24.6 24.5 31.3 28.8 37.5 40.5 52.2 360

85 Typ 128 137 1.48 1.51 7 8 17.6 24.9 25 31.6 29.1 37.7 41.1 52.5 364

Max 335 360 1.87 1.89 8.6 9.4 22 28.2 26.9 33.5 32 40 44 55.6 400

105 Typ 240 257 1.58 1.61 7.6 8.3 18.3 25.7 25.5 31.9 29.8 38 41.5 53.1 373

Max 740 791 2.32 2.34 9.9 10.9 23.1 30.2 27.8 35.3 33.8 40.7 44.9 57.4 423

125 Max 1637 1694 3.1 3.21 12.7 13.7 25 32.9 30.7 38.8 36 43.8 NA 450

S32K144 25 Typ 29.8 39.1 1.48 1.50 7 7.7 19.7 26.9 25.1 33.3 30.2 39.6 43.3 55.6 378

85 Typ 150 159 1.72 1.85 7.2 8.1 20.4 27.1 26.1 33.5 30.5 40 43.9 56.1 381

Max 359 384 2.60 2.65 9.2 9.9 23.2 29.6 29.3 36.2 34.8 42.1 46.3 59.7 435

Table continues on the next page...

General

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 17

Table 7. Power consumption (Typicals unless stated otherwise) 1 (continued)

Chip/Device

Ambient Temperature (°C)

VLPS (μA)2, 3VLPR (mA) STOP1

(mA)

STOP2

(mA)

RUN@48

MHz (mA)

RUN@64 MHz

(mA)

RUN@80 MHz

(mA)

HSRUN@112

MHz (mA) 4

IDD/MHz (μA/MHz)5

Peripherals disabled 6

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

Peripherals enabled

105 Typ 256 273 1.80 2.10 7.8 8.5 20.6 27.4 26.6 33.8 31.2 40.5 44.8 57.1 390

Max 850 900 2.65 2.70 10.3 11.1 23.9 30.6 30.3 37.3 35.6 43.5 47.9 61.3 445

125 Max 1960 1998 3.18 3.25 12.9 13.8 26.9 33.6 35 40.3 38.7 46.8 NA 484

S32K146 25 Typ 37 47 1.57 1.61 8 9.2 23.4 31.4 30.5 40.2 36.2 47.6 52 68.3 452

85 Typ 207 209 1.79 1.83 8.9 10.1 24.4 32.4 31.5 41.3 37.2 48.7 53.3 69.8 465

Max 974 981 3.32 3.38 12.7 13.9 29.3 37.9 36.7 47 42.4 54.4 60.3 78 530

105 Typ 419 422 1.99 2.04 9.8 11 25.3 33.4 32.5 42.2 38.1 49.6 54.4 70.8 477

Max 2004 2017 4.06 4.13 17.1 18.3 34.1 42.6 41.3 51.4 46.9 58.8 65.7 82.8 587

125 Max 3358 3380 5.28 5.38 22.6 23.7 40.2 48.8 47.3 57.4 52.8 64.8 NA 660

S32K148725 Typ 38 54 2.17 2.20 8.5 9.6 27.6 34.9 35.5 45.3 42.1 57.7 60.3 83.3 526

85 Typ 336 357 2.30 2.35 10.1 11.1 29.1 37.0 36.8 46.6 43.4 59.9 62.9 88.7 543

Max 1660 1736 3.48 3.55 14.5 15.6 34.8 43.6 41.9 53.9 48.7 65.1 70.4 96.1 609

105 Typ 560 577 2.49 2.54 10.9 11.9 29.8 37.8 37.6 47.5 45.2 61.5 63.8 89.1 565

Max 2945 2970 4.40 4.47 18.0 19.0 38.4 46.8 44.9 55.3 51.6 66.8 73.6 97.4 645

125 Max 3990 4166 6.00 6.08 23.4 24.5 44.3 52.5 50.9 61.3 57.5 71.6 NA 719

1. Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes

VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise stated. All output pins are floating and On-chip pulldown is enabled for

all unused input pins.

General

S32K1xx Data Sheet, Rev. 7, 04/2018

18 NXP Semiconductors

2. This is an average based on the use case described in the Comparator section, whereby the analog sampling is taking place periodically, with a mechanism to only

enable the DAC as required. The numbers quoted assumes that only a single ANLCMP is active and the others are disabled

3. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.

4. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.

5. Values mentioned are measured at RUN@80 MHz with peripherals disabled.

6. With PMC_REGSC[CLKBIASDIS] set to 1. See Reference Manual for details.

7. The S32K148 data points assume that ENET/QuadSPI/SAI etc. are inactive.

General

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 19

The following table shows the power consumption targets for S32K148 in various mode

of operations measure at 3.3 V.

Table 8. Power consumption at 3.3 V

Chip/Device Ambient

Temperature

(°C)

RUN@80 MHz (mA) HSRUN@112 MHz (mA)1

Peripherals

enabled +

QSPI

Peripherals

enabled +

ENET + SAI

Peripherals

enabled +

QSPI

Peripherals

enabled +

ENET + SAI

S32K148 25 Typ 67.3 79.1 89.8 105.5

85 Typ 67.4 79.2 95.6 105.9

Max 82.5 88.2 109.7 117.4

105 Typ 68.0 79.8 96.6 106.7

Max 80.3 89.1 109.0 119.0

125 Max 83.5 94.7 NA

1. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.

4.8 ESD handling ratings

Symbol Description Min. Max. Unit Notes

VHBM Electrostatic discharge voltage, human body model − 4000 4000 V 1

VCDM Electrostatic discharge voltage, charged-device model 2

All pins except the corner pins − 500 500 V

Corner pins only − 750 750 V

ILAT Latch-up current at ambient temperature of 125 °C − 100 100 mA 3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

4.9 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

General

S32K1xx Data Sheet, Rev. 7, 04/2018

20 NXP Semiconductors

I/O parameters

5.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

Figure 7. Input signal measurement reference

5.2 General AC specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and timers.

Table 9. General switching specifications

Symbol Description Min. Max. Unit Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5 — Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, passive filter disabled) — Asynchronous path

50 — ns 3

WFRST RESET input filtered pulse — 10 ns 4

WNFRST RESET input not filtered pulse Maximum of

(100 ns, bus

clock period)

— ns 5

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in

that case.

2. The greater of synchronous and asynchronous timing must be met.

3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.

4. Maximum length of RESET pulse which will be filtered by internal filter.

5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. This number depends on bus clock

period also. For example, in VLPR mode bus clock is 4 MHz, which make clock period of 250 ns. In this case, minimum

pulse width which will cause reset is 250 ns. For faster bus clock frequencies which have clock period less than 100 ns,

the minimum pulse width not filtered will be 100 ns.

I/O parameters

S32K1xx Data Sheet, Rev. 7, 04/2018

NXP Semiconductors 21