1
File Number
1824.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRF150
40A, 100V, 0.055 Ohm, N-Channel
Power MOSFET
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly Developmental Type TA17421.
Features
40A, 100V
•r
DS(ON) = 0.055
Single Pulse Avalanche Energy Rated
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-204AE
Ordering Information
PART NUMBER PACKAGE BRAND
IRF150 TO-204AE IRF150
NOTE: When ordering, include the entire part number. G
D
S
DRAIN
(FLANGE)
SOURCE (PIN 2)
GATE (PIN 1)
Data Sheet March 1999
2
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
IRF150 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 40 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID25 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 160 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD150 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS 150 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA (Figure 10) 100 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 40 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) VGS = 10V, ID = 20A (Figures 8, 9) - 0.045 0.055
Forward Transconductance (Note 2) gfs VDS > ID(ON) x rDS(ON)MAX, ID = 20A (Figure 12) 9.0 11 - S
Turn-On Delay Time td(ON) VDD = 24V, ID20A, RG = 4.7, RL = 1.2
(Figures 17, 18) MOSFET Switching Times are
Essentially Independent of Operating Temperature
- - 35 ns
Rise Time tr- - 100 ns
Turn-Off Delay Time td(OFF) - - 125 ns
Fall Time tf- - 100 ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID = 50A, VDS = 0.8 x Rated BVDSS,
Ig(REF) = -1.5mA (Figures 14, 19, 20) Gate Charge
is Essentially Independent of Operating
Temperature
- 63 120 nC
Gate to Source Charge Qgs -27-nC
Gate to Drain “Miller” Charge Qgd -36-nC
Input Capacitance CISS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 2000 - pF
Output Capacitance COSS - 1000 - pF
Reverse Transfer Capacitance CRSS - 350 - pF
Internal Drain Inductance LDMeasured between the
Contact Screw on the
Flange that is Closer to
SourceandGate Pinsand
the Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 5.0 - nH
Internal Source Inductance LSMeasured from the
Source Lead, 6mm
(0.25in) from the Flange
and the Source Bonding
Pad
- 12.5 - nH
Thermal Impedance Junction to Case RθJC - - 0.8 oC/W
Thermal Impedance Junction to Ambient RθJA Free Air Operation - - 30 oC/W
LS
LD
G
D
S
IRF150
3
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to DrainCurrent ISD Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Diode
- - 40 A
Pulse Source to Drain Current (Note 3) ISDM - - 160 A
Diode Source to Drain Voltage (Note 2) VSD TJ = 25oC, ISD = 40A, VGS = 0V (Figure 13) - - 2.5 V
Reverse Recovery Time trr TJ = 150oC, ISD = 40A, dISD/dt = 100A/µs - 600 - ns
Reverse Recovery Charge QRR TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/µs - 3.3 - µC
NOTES:
2. Pulse test: pulse width 300µs, duty cycle 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 10V, starting TJ = 25oC, L = 170µH, RG = 50, Peak IAS = 40A. See Figures 15, 16.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
G
D
S
0 50 100 150
0
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.2
0.4
0.6
0.8
1.0
1.2
TC, CASE TEMPERATURE (oC)
50 75 10025 150
40
32
24
0
16
ID, DRAIN CURRENT (A)
8
125
1.0
0.1
10-2
10-5 10-4 10-3 0.1 1 10
t1, RECTANGULAR PULSE DURATION (s)
ZθJC, TRANSIENT THERMAL
0.01 SINGLE PULSE DUTY FACTOR: D = t1/t2
t2
PDM
t1
NOTES:
0.5
TJ = PDM x ZθJC + TC
t2
0.01
0.2
0.1
0.02
0.05
IMPEDANCE (oC/W)
IRF150
4
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
102
10
110
102
1
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V) 103
103
SINGLE PULSE
TC = 25oC
OPERATION IN THIS
REGION IS LIMITED
BY rDS(ON)
TJ = MAX RATED
10µs
100µs
1ms
DC
10ms
100ms
VDS, DRAIN TO SOURCE VOLTAGE (V)
10 20 30 40050
50
40
30
0
20
ID, DRAIN CURRENT (A)
7V
6V
VGS = 8V
5V
80µs PULSE TEST
10
9V
10V
4V
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.4 0.8 1.2 1.60 2.0
20
16
12
0
8
ID, DRAIN CURRENT (A)
80µs PULSE TEST
4
8V
6V
5V
VGS = 10V
4V
7V
9V
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
20
10
001234 8
TJ = 125oC
TJ = 25oC
5
15
25
30
TJ = -55oC
80µs PULSE TEST
VDS >I
D(ON) xr
DS(ON)MAX
567
ID, DRAIN CURRENT (A)
40 80 120
0 160
0.20
0.14
0.10
0.06
rDS(ON), DRAIN TO SOURCE
VGS = 20V
0.02
VGS = 10V
ON RESISTANCE ()
2.2
1.4
0.6
80-60 TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
1.8
1.0
0.2 0 60 120
ON RESISTANCE
-20-40 20 40 100 140
ID = 14A
VGS = 10V
IRF150
5
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves
Unless Otherwise Specified (Continued)
1.25
1.05
0.85
60
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
1.15
0.95
0.75 -20 20 100 160
BREAKDOWN VOLTAGE
0-40 40 80 120 140
ID = 250µA
010 304050
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
4000
3200
2400
1600
800
020
CRSS
CISS
COSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
ID, DRAIN CURRENT (A)
10 20 30 40050
20
16
12
0
8
gfs, TRANSCONDUCTANCE (S)
80µs PULSE TEST
4
TJ = -55oC
TJ = 25oC
TJ = 125oC
ISD, SOURCE TO DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
102
10
1.001234
TJ = 25oC
TJ = 150oC
2
Qg(TOT), TOTAL GATE CHARGE (nC)
28 56 84 1120 140
5
20
10
VGS, GATE TO SOURCE VOLTAGE (V)
VDS = 20V
15
0
ID = 40A
FOR TEST CIRCUIT,
SEE FIGURE 19
VDS = 80V
VDS = 50V
IRF150
6
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50k
VDS
S
DUT
D
G
Ig(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
IRF150
7
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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IRF150