IRF150 Data Sheet March 1999 40A, 100V, 0.055 Ohm, N-Channel Power MOSFET * 40A, 100V Formerly Developmental Type TA17421. Ordering Information PACKAGE 1824.3 Features This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number * rDS(ON) = 0.055 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol BRAND D IRF150 TO-204AE IRF150 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-204AE DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRF150 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF150 100 100 40 25 160 20 150 1.2 150 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250A (Figure 10) 100 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS , ID = 250A 2.0 - 4.0 V - - 25 A - - 250 A 40 - - A Zero Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time IGSS rDS(ON) VGS = 20V - - 100 nA VGS = 10V, ID = 20A (Figures 8, 9) - 0.045 0.055 gfs VDS > ID(ON) x rDS(ON)MAX , ID = 20A (Figure 12) 9.0 11 - S td(ON) VDD = 24V, ID 20A, RG = 4.7, RL = 1.2 (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature - - 35 ns - - 100 ns - - 125 ns - - 100 ns - 63 120 nC - 27 - nC tr Turn-Off Delay Time VDS > ID(ON) x rDS(ON)MAX , VGS = 10V td(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Qg(TOT) Qgs Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance - 36 - nC - 2000 - pF COSS - 1000 - pF CRSS - 350 - pF - 5.0 - nH - 12.5 - nH - - 0.8 oC/W - - 30 oC/W LD Internal Source Inductance VGS = 10V, ID = 50A, VDS = 0.8 x Rated BVDSS , Ig(REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature LS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Measured between the Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die Measured from the Source Lead, 6mm (0.25in) from the Flange and the Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Thermal Impedance Junction to Case RJC Thermal Impedance Junction to Ambient RJA 2 Free Air Operation IRF150 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to DrainCurrent ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS MIN TYP MAX UNITS - - 40 A - - 160 A TJ = 25oC, ISD = 40A, VGS = 0V (Figure 13) - - 2.5 V TJ = 150oC, ISD = 40A, dISD/dt = 100A/s TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/s - 600 - ns - 3.3 - C Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode D G S Diode Source to Drain Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovery Charge QRR NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 10V, starting TJ = 25oC, L = 170H, RG = 50, Peak IAS = 40A. See Figures 15, 16. Typical Performance Curves Unless Otherwise Specified 40 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 32 24 16 8 0 0 50 100 25 150 50 TC , CASE TEMPERATURE (oC) 75 100 150 125 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 IMPEDANCE (oC/W) ZJC , TRANSIENT THERMAL POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 0.1 PDM 0.1 0.05 0.02 t1 t2 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 TJ = PDM x ZJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 1 10 IRF150 Typical Performance Curves Unless Otherwise Specified (Continued) 50 10V 103 102 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 10s 100s 1ms 10 10ms TJ = MAX RATED TC = 25oC SINGLE PULSE 100ms VGS = 8V 40 30 7V 20 6V 10 5V DC 1 4V 102 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 103 0 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 50 FIGURE 5. OUTPUT CHARACTERISTICS 30 20 VGS = 10V VDS > ID(ON) x rDS(ON)MAX 80s PULSE TEST 80s PULSE TEST 25 9V 16 ID , DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 80s PULSE TEST 9V 8V 7V 12 6V 8 5V TJ = 125oC 20 TJ = 25oC 15 TJ = -55oC 10 4 5 4V 0 0 0 0.4 0.8 1.2 1.6 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 2.0 2.2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON) , DRAIN TO SOURCE ON RESISTANCE () 0.14 VGS = 10V 0.10 VGS = 20V 0 40 80 120 ID , DRAIN CURRENT (A) 160 NOTE: Heating effect of 2s is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 3 4 5 6 7 8 FIGURE 7. TRANSFER CHARACTERISTICS 0.20 0.02 2 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS 0.06 1 ID = 14A VGS = 10V 1.8 1.4 1.0 0.6 0.2 -60 -40 -20 0 20 40 60 80 100 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 140 IRF150 Typical Performance Curves 4000 ID = 250A 1.15 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 3200 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified (Continued) 1.05 0.95 2400 CISS 1600 0.85 COSS 800 CRSS 0.75 -40 -20 0 20 40 60 100 80 120 140 0 160 0 ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) TJ = -55oC TJ = 25oC TJ = 125oC 8 4 0 10 50 2 80s PULSE TEST 0 40 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 20 12 30 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 16 20 10 TJ , JUNCTION TEMPERATURE (oC) 20 30 ID , DRAIN CURRENT (A) 40 50 102 TJ = 150oC 10 TJ = 25oC 1.0 0 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 1 2 3 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE VGS , GATE TO SOURCE VOLTAGE (V) 20 ID = 40A FOR TEST CIRCUIT, SEE FIGURE 19 15 VDS = 20V VDS = 50V VDS = 80V 10 5 0 0 28 56 84 112 140 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 4 IRF150 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2F 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50k Qgd 0.3F VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF150 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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