Low Cost, 250 mA Output,
Single-Supply Amplifiers
AD8531/AD8532/AD8534
Rev. F
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FEATURES
Single-supply operation: 2.7 V to 6 V
High output current: ±250 mA
Low supply current: 750 μA/amplifier
Wide bandwidth: 3 MHz
Slew rate: 5 V/μs
No phase reversal
Low input currents
Unity gain stable
Rail-to-rail input and output
APPLICATIONS
Multimedia audio
LCD drivers
ASIC input or output amplifiers
Headphone drivers
GENERAL DESCRIPTION
The AD8531, AD8532, and AD8534 are single, dual, and quad
rail-to-rail input/output single-supply amplifiers featuring
250 mA output drive current. This high output current makes
these amplifiers excellent for driving either resistive or capacitive
loads. AC performance is very good with 3 MHz bandwidth,
5 V/μs slew rate, and low distortion. All are guaranteed to operate
from a 3 V single supply as well as a 5 V supply.
The very low input bias currents enable the AD853x to be used for
integrators, diode amplification, and other applications requiring
low input bias current. Supply current is only 750 μA per
amplifier at 5 V, allowing low current applications to control
high current loads.
Applications include audio amplification for computers, sound
ports, sound cards, and set-top boxes. The AD853x family is
very stable, and it is capable of driving heavy capacitive loads
such as those found in LCDs.
The ability to swing rail-to-rail at the inputs and outputs enables
designers to buffer CMOS DACs, ASICs, or other wide output
swing devices in single-supply systems.
The AD8531/AD8532/AD8534 are specified over the extended
industrial temperature range (−40°C to +85°C). The AD8531 is
available in 8-lead SOIC, 5-lead SC70, and 5-lead SOT-23 packages.
The AD8532 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead
TSSOP surface-mount packages. The AD8534 is available in
narrow 14-lead SOIC and 14-lead TSSOP surface-mount
packages.
PIN CONFIGURATIONS
–IN A
+IN A
V+
OUT A
V–
01099-001
1
3
2
5
4
AD8531
Figure 1. 5-Lead SC70 and 5-Lead SOT-23
(KS and RJ Suffixes)
01099-002
NC 1
–IN A 2
+IN A 3
V– 4
NC8
V+7
OUT A
6
NC5
NC = NO CONNECT
AD8531
Figure 2. 8-Lead SOIC
(R Suffix)
AD8532
1
2
3
4
–IN A
+IN A
V–
OUT A
8
7
6
5
OUT B
–IN B
+IN B
V+
01099-003
Figure 3. 8-Lead SOIC, 8-Lead TSSOP, and 8-Lead MSOP
(R, RU, and RM Suffixes)
01099-004
AD8534
O
UT A
–IN A
+IN A
V+ V–
+IN D
–IN D
OUT D
+IN B
–IN B
O
UT B OUT C
–IN C
+IN C
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Figure 4. 14-Lead SOIC and 14-Lead TSSOP
(R and RU Suffixes)
AD8531/AD8532/AD8534
Rev. F | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Short-Circuit Protection............................................................ 11
Power Dissipation....................................................................... 11
Power Calculations for Varying or Unknown Loads............. 12
Calculating Power by Measuring Ambient and Case
Temperature ................................................................................ 12
Calculating Power by Measuring Supply Current ................. 12
Input Overvoltage Protection ................................................... 12
Output Phase Reversal............................................................... 13
Capacitive Load Drive ............................................................... 13
Applications Information.............................................................. 14
High Output Current, Buffered Reference/Regulator........... 14
Single-Supply, Balanced Line Driver ....................................... 14
Single-Supply Headphone Amplifier....................................... 15
Single-Supply, 2-Way Loudspeaker Crossover Network....... 15
Direct Access Arrangement for Telephone Line Interface ... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 20
REVISION HISTORY
1/08—Rev. E to Rev. F
Changes to Layout ............................................................................ 5
Changes to Figure 12 and Figure 13............................................... 7
Changes to Figure 38...................................................................... 11
Changes to Input Overvoltage Protection Section..................... 12
Changes to Figure 43...................................................................... 14
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 20
4/05—Rev. D to Rev. E
Updated Format..................................................................Universal
Changes to Pin Configurations....................................................... 1
Changes to Table 4............................................................................ 5
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
10/02—Rev. C to Rev. D
Deleted 8-Lead PDIP (N-8) .............................................. Universal
Deleted 14-Lead PDIP (N-14) .......................................... Universal
Edits to Figure 34...............................................................................9
Updated Outline Dimensions........................................................15
8/96—Revision 0: Initial Version
AD8531/AD8532/AD8534
Rev. F | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 25 mV
−40°C ≤ TA ≤ +85°C 30 mV
Input Bias Current IB 5 50 pA
−40°C ≤ TA ≤ +85°C 60 pA
Input Offset Current IOS 1 25 pA
−40°C ≤ TA ≤ +85°C 30 pA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 3 V 38 45 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VO = 0.5 V to 2.5 V 25 V/mV
Offset Voltage Drift ΔVOS/ΔT 20 μV/°C
Bias Current Drift ΔIB/ΔT 50 fA/°C
Offset Current Drift ΔIOS/ΔT 20 fA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 10 mA 2.85 2.92 V
−40°C ≤ TA ≤ +85°C 2.8 V
Output Voltage Low VOL IL = 10 mA 60 100 mV
−40°C ≤ TA ≤ +85°C 125 mV
Output Current IOUT ±250 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 60 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 3 V to 6 V 45 55 dB
Supply Current/Amplifier ISY VO = 0 V 0.70 1 mA
−40°C ≤ TA ≤ +85°C 1.25 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 3.5 V/μs
Settling Time tSTo 0.01% 1.6 μs
Gain Bandwidth Product GBP 2.2 MHz
Phase Margin фo 70 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ 65 dB
NOISE PERFORMANCE
Voltage Noise Density enf = 1 kHz 45 nV/√Hz
f = 10 kHz 30 nV/√Hz
Current Noise Density inf = 1 kHz 0.05 pA/√Hz
AD8531/AD8532/AD8534
Rev. F | Page 4 of 20
VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 25 mV
−40°C ≤ TA ≤ +85°C 30 mV
Input Bias Current IB 5 50 pA
−40°C ≤ TA ≤ +85°C 60 pA
Input Offset Current IOS 1 25 pA
−40°C ≤ TA ≤ +85°C 30 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 38 47 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VO = 0.5 V to 4.5 V 15 80 V/mV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 20 μV/°C
Bias Current Drift ΔIB/ΔT 50 fA/°C
Offset Current Drift ΔIOS/ΔT 20 fA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 10 mA 4.9 4.94 V
−40°C ≤ TA ≤ +85°C 4.85 V
Output Voltage Low VOL IL = 10 mA 50 100 mV
−40°C ≤ TA ≤ +85°C 125 mV
Output Current IOUT ±250 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 40 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 3 V to 6 V 45 55 dB
Supply Current/Amplifier ISY VO = 0 V 0.75 1.25 mA
−40°C ≤ TA ≤ +85°C 1.75 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 5 V/μs
Full-Power Bandwidth BWp1% distortion 350 kHz
Settling Time tSTo 0.01% 1.4 μs
Gain Bandwidth Product GBP 3 MHz
Phase Margin фo 70 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ 65 dB
NOISE PERFORMANCE
Voltage Noise Density enf = 1 kHz 45 nV/√Hz
f = 10 kHz 30 nV/√Hz
Current Noise Density inf = 1 kHz 0.05 pA/√Hz
AD8531/AD8532/AD8534
Rev. F | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage (VS) 7 V
Input Voltage GND to VS
Differential Input Voltage1±6 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1 For supplies less than 6 V, the differential input voltage is equal to ±VS.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; the functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4.
Package Type θJA θJC Unit
5-Lead SC70 (KS) 376 126 °C/W
5-Lead SOT-23 (RJ) 230 146 °C/W
8-Lead SOIC (R) 158 43 °C/W
8-Lead MSOP (RM) 210 45 °C/W
8-Lead TSSOP (RU) 240 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 240 43 °C/W
R
LOAD
(Ω)
±V
OUT
2.5
2.0
1.5
1.0
0.5
0
0 20 40 60 80 100 120 140 160 180 200
01099-005
+V
OH
–V
OL
Figure 5. Output Voltage vs. Load, VS = ±2.5 V,
RLOAD Is Connected to GND (0 V)
ESD CAUTION
AD8531/AD8532/AD8534
Rev. F | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE (mV)
QUANTITY (Amplifiers)
500
400
300
200
100
–12 –10 –8 –6 –4 –2 0 2 4
01099-006
VS= 2.7V
VCM = 1.35V
TA= 25°C
Figure 6. Input Offset Voltage Distribution
INPUT OFFSET VOLTAGE (mV)
QUANTITY (Amplifiers)
500
400
300
200
100
–12 –10 –8 –6 –4 –2 0 2 4
01099-007
VS= 5V
VCM = 2.5V
TA= 25°C
Figure 7. Input Offset Voltage Distribution
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (mV)
–2
–3
–4
–5
–6
–7
–8
–35 –15 5 25 45 65 85
01099-008
V
S
= 5V
V
CM
= 2.5V
Figure 8. Input Offset Voltage vs. Temperature
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
8
7
6
5
4
3
2
–35 –15 5 25 45 65 85
01099-009
V
S
= 5V, 3V
V
CM
= V
S
/2
Figure 9. Input Bias Current vs. Temperature
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (pA)
8
7
6
5
4
3
2
01 2 34 5
01099-010
V
S
= 5V
T
A
= 25°C
Figure 10. Input Bias Current vs. Common-Mode Voltage
TEMPERATURE (°C)
INPUT OFFSET CURRENT (pA)
5
4
3
2
1
0
–1
–2
6
–35 –15 5 25 45 65 85
01099-011
VS= 5V, 3V
VCM = VS/2
Figure 11. Input Offset Current vs. Temperature
AD8531/AD8532/AD8534
Rev. F | Page 7 of 20
SOURCE
SINK
LOAD CURRENT (mA)
ΔOUTPUT VOLTAGE (mV)
1000
100
10
1
0.01
0.1
0.001 0.01 0.1 1 10 100
01099-012
V
S
= 2.7V
T
A
= 25°C
Figure 12. Output Voltage to Supply Rail vs. Load Current
LOAD CURRENT (mA)
ΔOUTPUT VOLTAGE (mV)
1000
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10 100
01099-013
V
S
= 5V
T
A
= 25°C
SINK
SOURCE
Figure 13. Output Voltage to Supply Rail vs. Load Current
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
PHASE SHIFT (Degrees)
45
90
135
180
1k 10k 100k 1M 10M 100M
01099-014
V
S
= 2.7V
R
L
= NO LOAD
T
A
= 25°C
Figure 14. Open-Loop Gain and Phase Shift vs. Frequency
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
PHASE SHIFT (Degrees)
45
90
135
180
1k 10k 100k 1M 10M 100M
01099-015
V
S
= 5V
R
L
= NO LOAD
T
A
= 25°C
Figure 15. Open-Loop Gain and Phase Shift vs. Frequency
FREQUENCY (Hz)
OUTPUT SWING (V p-p)
5
4
3
1
2
01k 10k 100k 1M 10M
01099-016
V
S
= 2.7V
T
A
= 25°C
R
L
= 2kΩ
V
IN
= 2.5V p-p
Figure 16. Closed-Loop Output Swing vs. Frequency
FREQUENCY (Hz)
OUTPUT SWING (V p-p)
5
4
3
1
2
01k 10k 100k 1M 10M
01099-017
V
S
= 5V
T
A
= 25°C
R
L
= 2kΩ
V
IN
= 4.9V p-p
Figure 17. Closed-Loop Output Swing vs. Frequency
AD8531/AD8532/AD8534
Rev. F | Page 8 of 20
LOAD CURRENT (mA)
IMPEDANCE
(
Ω)
200
160
120
80
40
180
140
100
60
20
01k 10k 100k 1M 10M 100M
01099-018
V
S
= 5V
T
A
= 25°C
A
V
= 1
A
V
= 10
Figure 18. Closed-Loop Output Impedance vs. Frequency
01099-019
MARKER 41µV/√Hz
100µV/DIV
10
0%
100
90
V
S
= 5V
A
V
= 1000
T
A
= 25°C
FREQUENCY = 1kHz
Figure 19. Voltage Noise Density vs. Frequency (1 kHz)
01099-020
MARKER 25.9µV/√Hz
200µV/DIV
10
0%
100
90
V
S
= 5V
A
V
= 1000
T
A
= 25°C
FREQUENCY = 10kHz
Figure 20. Voltage Noise Density vs. Frequency (10 kHz)
FREQUENCY (Hz)
CURRENT NOISE DENSITY (pA/√Hz)
1
0.1
0.0110 100 1k 10k 100k
01099-021
V
S
= 5V
T
A
= 25°C
Figure 21. Current Noise Density vs. Frequency
FREQUENCY (Hz)
COMMON-MODE REJECTION (dB)
110
100
90
80
70
60
50
401k 10k 100k 1M 10M
01099-022
V
S
= 5V
T
A
= 25°C
Figure 22. Common-Mode Rejection vs. Frequency
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
140
120
40
60
80
100
20
0
–20
–40
–60
100 1k 10k 100k 1M 10M
01099-023
PSSR+
PSSR–
V
S
= 2.7V
T
A
= 25°C
Figure 23. Power Supply Rejection vs. Frequency
AD8531/AD8532/AD8534
Rev. F | Page 9 of 20
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
140
120
40
60
80
100
20
0
–20
–40
–60
100 1k 10k 100k 1M 10M
01099-024
V
S
= 5V
T
A
= 25°C
PSSR+
PSSR–
Figure 24. Power Supply Rejection vs. Frequency
CAPACITANCE (pF)
SMALL SIGN
A
L OVERSHOOT (%)
50
40
30
10
20
010 100 1000 10000
01099-025
V
S
= 2.7V
T
A
= 25°C
R
L
= 2kΩ
–OS
+OS
Figure 25. Small Signal Overshoot vs. Load Capacitance
CAPACITANCE (pF)
SMALL SIGN
A
L OVERSHOOT (%)
60
50
40
30
10
20
010 100 1000 10000
01099-026
V
S
= 5V
T
A
= 25°C
R
L
= 2kΩ
–OS
+OS
Figure 26. Small Signal Overshoot vs. Load Capacitance
CAPACITANCE (pF)
SMALL SIGN
A
L OVERSHOOT (%)
50
40
30
10
20
010 100 1000 10000
01099-027
V
S
= 5V
T
A
= 25°C
R
L
= 600Ω
–OS +OS
Figure 27. Small Signal Overshoot vs. Load Capacitance
CAPACITANCE (pF)
SMALL SIGN
A
L OVERSHOOT (%)
50
40
30
10
20
010 100 1000 10000
01099-028
V
S
= 2.7V
T
A
= 25°C
R
L
= 600Ω
–OS
+OS
Figure 28. Small Signal Overshoot vs. Load Capacitance
TEMPERATURE (°C)
SUPPLY CURRENT/AMPLIFIER (mA)
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.90
–20–40 0 20 40 60 80
01099-029
V
S
= 5V
V
S
= 3V
Figure 29. Supply Current per Amplifier vs. Temperature
AD8531/AD8532/AD8534
Rev. F | Page 10 of 20
01099-033
10
0%
100
90
500ns500mV
V
S
= ±2.5V
A
V
= 1
R
L
= 2kΩ
T
A
= 25°C
SUPPLY VOLTAGE (±V)
SUPPLY CURRENT/AMPLIFIER (mA)
0.7
0.8
0.6
0.5
0.4
0.3
0.2
0.1
0
0.75 1.501.00 2.00 2.50 3.00
01099-030
T
A
= 25°C
Figure 33. Large Signal Transient Response
Figure 30. Supply Current per Amplifier vs. Supply Voltage
01099-034
10
0%
100
90
500ns500mV
V
S
= ±1.35V
A
V
= 1
R
L
= 2kΩ
T
A
= 25°C
500 ns/DIV
20mV/DI
V
0V
01099-031
V
S
= 1.35V
V
IN
= 50mV
A
V
= 1Ω
R
L
= 2kΩ
C
L
= 300pF
T
A
= 25°C
Figure 34. Large Signal Transient Response
Figure 31. Small Signal Transient Response
01099-035
10
0%
100
90
10µs
1V
1V
500ns/DIV
20mV/DI
V
0V
01099-032
V
S
= 2.5V
V
IN
= 50mV
A
V
= 1Ω
R
L
= 2kΩ
C
L
= 300pF
T
A
= 25°C
Figure 35. No Phase Reversal
Figure 32. Small Signal Transient Response
AD8531/AD8532/AD8534
Rev. F | Page 11 of 20
THEORY OF OPERATION
The AD8531/AD8532/AD8534 are all CMOS, high output
current drive, rail-to-rail input/output operational amplifiers.
Their high output current drive and stability with heavy capacitive
loads make the AD8531/AD8532/AD8534 excellent choices as
drive amplifiers for LCD panels.
Figure 36 illustrates a simplified equivalent circuit for the
AD8531/AD8532/AD8534. Like many rail-to-rail input amplifier
configurations, it comprises two differential pairs, one N-channel
(M1 to M2) and one P-channel (M3 to M4). These differential
pairs are biased by 50 μA current sources, each with a compliance
limit of approximately 0.5 V from either supply voltage rail. The
differential input voltage is then converted into a pair of
differential output currents. These differential output currents
are then combined in a compound folded-cascade second gain
stage (M5 to M9). The outputs of the second gain stage at M8
and M9 provide the gate voltage drive to the rail-to-rail output
stage. Additional signal current recombination for the output
stage is achieved using M11 to M14.
To achieve rail-to-rail output swings, the AD8531/AD8532/
AD8534 design employs a complementary, common source
output stage (M15 to M16). However, the output voltage swing
is directly dependent on the load current because the difference
between the output voltage and the supply is determined by
the AD8531/AD8532/AD8534’s output transistors on channel
resistance (see Figure 12 and Figure 13). The output stage also
exhibits voltage gain by virtue of the use of common source
amplifiers; as a result, the voltage gain of the output stage (thus,
the open-loop gain of the device) exhibits a strong dependence
on the total load resistance at the output of the AD8531/
AD8532/AD8534.
50µA 100µA 100µA 20µA
V
B2
M5
M8
M12
M15
M16
M11
OUT
M3 M4 M2
M1
IN–
IN+ V
B3
M6
M7 M10
20µA
M13
50µA
V
+
V–
M9 M14
01099-036
Figure 36. Simplified Equivalent Circuit
SHORT-CIRCUIT PROTECTION
As a result of the design of the output stage for the maximum
load current capability, the AD8531/AD8532/AD8534 do not
have any internal short-circuit protection circuitry. Direct
connection of the output of the AD8531/AD8532/AD8534 to
the positive supply in single-supply applications destroys the
device. In applications where some protection is needed, but not
at the expense of reduced output voltage headroom, a low value
resistor in series with the output, as shown in Figure 37, can be
used. The resistor, connected within the feedback loop of the
amplifier, has very little effect on the performance of the amplifier
other than limiting the maximum available output voltage
swing. For single 5 V supply applications, resistors less than
20 Ω are not recommended.
5
V
R
X
20Ω
V
OUT
V
IN
AD8532
01099-037
Figure 37. Output Short-Circuit Protection
POWER DISSIPATION
Although the AD8531/AD8532/AD8534 are capable of
providing load currents to 250 mA, the usable output load
current drive capability is limited to the maximum power
dissipation allowed by the device package used. In any
application, the absolute maximum junction temperature
for the AD8531/AD8532/AD8534 is 150°C. The maximum
junction temperature should never be exceeded because the
device could suffer premature failure. Accurately measuring
power dissipation of an integrated circuit is not always a
straightforward exercise; therefore, Figure 38 is provided
as a design aid for either setting a safe output current drive
level or selecting a heat sink for the package options available
on the AD8531/AD8532/AD8534.
TEMPERATURE (°C)
POWER DISSIPATION (W)
1.5
1.0
0.5
0
0 25 50 75 85 100
01099-038
T
J
MAX = 150°C
FREE AIR
NO HEAT SINK
TSSOP
θ
JA
= 240°C/W
SC70
θ
JA
= 376°C/W
SOIC
θ
JA
= 158°C/W
MSOP
θ
JA
= 210°C/W
SOT-23
θ
JA
= 230°C/W
Figure 38. Maximum Power Dissipation vs. Ambient Temperature
AD8531/AD8532/AD8534
Rev. F | Page 12 of 20
The thermal resistance curves were determined using the
AD8531/AD8532/AD8534 thermal resistance data for each
package and a maximum junction temperature of 150°C. The
following formula can be used to calculate the internal junction
temperature of the AD8531/AD8532/AD8534 for any application:
TJ = PDISS × θJA + TA
where:
TJ is the junction temperature.
PDISS is the power dissipation.
θJA is the package thermal resistance, junction-to-case.
TA is the ambient temperature of the circuit.
To calculate the power dissipated by the AD8531/AD8532/
AD8534, the following equation can be used:
PDISS = ILOAD × (VS − VOUT)
where:
ILOAD is the output load current.
VS is the supply voltage.
VOUT is the output voltage.
The quantity within the parentheses is the maximum voltage
developed across either output transistor. As an additional
design aid in calculating available load current from the
AD8531/AD8532/AD8534, Figure 5 illustrates the output
voltage of the AD8531/AD8532/AD8534 as a function of
load resistance.
POWER CALCULATIONS FOR VARYING OR
UNKNOWN LOADS
Often, calculating power dissipated by an integrated circuit to
determine if the device is being operated in a safe range is not
as simple as it may seem. In many cases, power cannot be directly
measured, which may be the result of irregular output waveforms
or varying loads; indirect methods of measuring power are
required.
There are two methods to calculate power dissipated by an
integrated circuit. The first can be done by measuring the
package temperature and the board temperature, and the
other is to directly measure the supply current of the circuit.
CALCULATING POWER BY MEASURING AMBIENT
AND CASE TEMPERATURE
Given the two equations for calculating junction temperature
TJ = TA + PDISS θJA
where:
TJ is the junction temperature.
TA is the ambient temperature.
θJA is the junction to ambient thermal resistance.
TJ = TC + PDISS θJA
where:
TC is the case temperature.
θJA and θJC are given in the data sheet.
The two equations can be solved for P (power)
TA + PDISS θJA = TC + PθJC
PDISS = (TA − TC)/(θJC − θJA)
Once power is determined, it is necessary to go back and calculate
the junction temperature to ensure that it has not been exceeded.
The temperature measurements should be directly on the package
and on a spot on the board that is near the package but not
touching it. Measuring the package could be difficult. A very
small bimetallic junction glued to the package can be used, or
measurement can be done using an infrared sensing device if
the spot size is small enough.
CALCULATING POWER BY MEASURING SUPPLY
CURRENT
Power can be calculated directly, knowing the supply voltage
and current. However, supply current may have a dc component
with a pulse into a capacitive load, which can make rms current
very difficult to calculate. It can be overcome by lifting the supply
pin and inserting an rms current meter into the circuit. For this
to work, be sure the current is being delivered by the supply pin
being measured. This is usually a good method in a single-supply
system; however, if the system uses dual supplies, both supplies
may need to be monitored.
INPUT OVERVOLTAGE PROTECTION
As with any semiconductor device, whenever the condition
exists for the input to exceed either supply voltage, the input
overvoltage characteristic of the device must be considered.
When an overvoltage occurs, the amplifier can be damaged,
depending on the magnitude of the applied voltage and the
magnitude of the fault current. Although not shown here, when
the input voltage exceeds either supply by more than 0.6 V, pn
junctions internal to the AD8531/AD8532/AD8534 energize,
allowing current to flow from the input to the supplies. As
illustrated in the simplified equivalent input circuit (see Figure 36),
the AD8531/AD8532/AD8534 do not have any internal current
limiting resistors; therefore, fault currents can quickly rise to
damaging levels.
This input current is not inherently damaging to the device, as
long as it is limited to 5 mA or less. For the AD8531/AD8532/
AD8534, once the input voltage exceeds the supply by more than
0.6 V, the input current quickly exceeds 5 mA. If this condition
continues to exist, an external series resistor should be added.
The size of the resistor is calculated by dividing the maximum
overvoltage by 5 mA. For example, if the input voltage could
reach 10 V, the external resistor should be (10 V/5 mA) = 2 kΩ.
This resistance should be placed in series with either or both
inputs if they are exposed to an overvoltage condition.
AD8531/AD8532/AD8534
Rev. F | Page 13 of 20
5V
R
S
5Ω
C
S
1µF
V
OUT
V
IN
100mV p-p
AD8532
01099-040
C
L
47nF
OUTPUT PHASE REVERSAL
Some operational amplifiers designed for single-supply operation
exhibit an output voltage phase reversal when their inputs are
driven beyond their useful common-mode range. The AD8531/
AD8532/AD8534 are free from reasonable input voltage range
restrictions, provided that input voltages no greater than the
supply voltage rails are applied. Although the output of the
device does not change phase, large currents can flow through
internal junctions to the supply rails, which was described in the
Input Overvoltage Protection section. Without limit, these fault
currents can easily destroy the amplifier. The technique
recommended in the Input Overvoltage Protection section
should therefore be applied in those applications where the
possibility of input voltages exceeding the supply voltages exists.
Figure 40. Snubber Network Compensates for Capacitive Loads
The first step is to determine the value of the resistor, RS. A good
starting value is 100 Ω. This value is reduced until the small signal
transient response is optimized. Next, CS is determined; 10 μF is a
good starting point. This value is reduced to the smallest value
for acceptable performance (typically, 1 μF). For the case of a
47 nF load capacitor on the AD8531/AD8532/AD8534, the
optimal snubber network is 5 Ω in series with 1 μF. The benefit
is immediately apparent, as seen in Figure 41. The top trace was
taken with a 47 nF load, and the bottom trace was taken with
the 5 Ω in series with a 1 μF snubber network in place. The
amount of overshoot and ringing is dramatically reduced. Table 5
illustrates a few sample snubber networks for large load
capacitors.
CAPACITIVE LOAD DRIVE
The AD8531/AD8532/AD8534 exhibit excellent capacitive load
driving capabilities. They can drive up to 10 nF directly, as
shown in Figure 25 through Figure 28. However, even though
the device is stable, a capacitive load does not come without a
penalty in bandwidth. As shown in Figure 39, the bandwidth is
reduced to less than 1 MHz for loads greater than 10 nF. A snubber
network on the output does not increase the bandwidth, but it
does significantly reduce the amount of overshoot for a given
capacitive load. A snubber consists of a series RC network (RS,
CS), as shown in Figure 40, connected from the output of the
device to ground. This network operates in parallel with the
load capacitor, CL, to provide phase lag compensation. The
actual value of the resistor and capacitor is best determined
empirically.
Table 5. Snubber Networks for Large Capacitive Loads
Load Capacitance (CL) Snubber Network (RS, CS)
0.47 nF 300 Ω, 0.1 μF
4.7 nF 30 Ω, 1 μF
47 nF 5 Ω, 1 μF
01099-041
10
0%
100
47nF LOAD
ONLY
SNUBBER
IN CIRCUIT
90
10µs50mV
50mV
CAPACITIVE LOAD (nF)
BANDWIDITH (MHz)
3.5
4.0
3.0
2.5
2.0
1.5
1.0
0.5
0
0.01 0.1 1 10 100
01099-039
V
S
= ±2.5V
R
L
= 1kΩ
T
A
= 25°C
Figure 41. Overshoot and Ringing Are Reduced by Adding a Snubber
Network in Parallel with the 47 nF Load
Figure 39. Unity-Gain Bandwidth vs. Capacitive Load
AD8531/AD8532/AD8534
Rev. F | Page 14 of 20
APPLICATIONS INFORMATION
HIGH OUTPUT CURRENT, BUFFERED
REFERENCE/REGULATOR
Many applications require stable voltage outputs relatively close
in potential to an unregulated input source. This low dropout
type of reference/regulator is readily implemented with a rail-
to-rail output op amp and is particularly useful when using a
higher current device, such as the AD8531/AD8532/AD8534.
A typical example is the 3.3 V or 4.5 V reference voltage developed
from a 5 V system source. Generating these voltages requires a
three terminal reference, such as the REF196 (3.3 V) or the
REF194 (4.5 V), both of which feature low power, with sourcing
outputs of 30 mA or less. Figure 42 shows how such a reference
can be outfitted with an AD8531/AD8532/AD8534 buffer for
higher currents and/or voltage levels, plus sink and source load
capability.
R2
10kΩ1%
VOUT1 =
3.3V @ 100mA
R5
0.2Ω
C5
100µF/16V
TANTALUM
R1
10kΩ
1%
C1
0.1µF
V
S
5V
VOUT2 =
3.3V C4
1µF
6
2
3
4
VOUT
COMMON
C3
0.1µF
C2
0.1µF
VC
ON/OFF
CONTROL
INPUT CMOS HI
(OR OPEN) = ON
LO = OFF
VS
COMMON
R3
(See Text)
R4
3.3kΩ
U2
AD8531
U1
REF196
01099-042
Figure 42. High Output Current Reference/Regulator
The low dropout performance of this circuit is provided by
stage U2, an AD8531 connected as a follower/buffer for the
basic reference voltage produced by U1. The low voltage
saturation characteristic of the AD8531/AD8532/AD8534
allows up to 100 mA of load current in the illustrated use,
as a 5 V to 3.3 V converter with good dc accuracy. In fact,
the dc output voltage change for a 100 mA load current delta
measures less than 1 mV. This corresponds to an equivalent
output impedance of < 0.01 Ω. In this application, the stable
3.3 V from U1 is applied to U2 through a noise filter, R1 to C1.
U2 replicates the U1 voltage within a few millivolts, but at a
higher current output at VOUT1, with the ability to both sink and
source output current(s), unlike most IC references. R2 and C2
in the feedback path of U2 provide additional noise filtering.
Transient performance of the reference/regulator for a 100 mA
step change in load current is also quite good and is largely
determined by the R5 to C5 output network. With values as
shown, the transient is about 20 mV peak and settles to within
2 mV in less than 10 μs for either polarity. Although room exists
for optimizing the transient response, any changes to the R5 to
C5 network should be verified by experiment to preclude the
possibility of excessive ringing with some capacitor types.
To scale VOUT2 to another (higher) output level, the optional
resistor R3 (shown dotted in Figure 42) is added, causing the
new VOUT1 to become
⎟
⎠
⎞
⎜
⎝
⎛+×= R3
R2
VV OUT2OUT1 1
The circuit can either be used as shown, as a 5 V to 3.3 V
reference/regulator, or with on/off control. By driving Pin 3 of
U1 with a logic control signal as noted, the output is switched
on/off. Note that when on/off control is used, R4 must be used
with U1 to speed on/off switching.
SINGLE-SUPPLY, BALANCED LINE DRIVER
The circuit in Figure 43 is a unique line driver circuit topology
used in professional audio applications. It was modified for
automotive and multimedia audio applications. On a single 5 V
supply, the line driver exhibits less than 0.7% distortion into a
600 Ω load from 20 Hz to 15 kHz (not shown) with an input
signal level of 4 V p-p. In fact, the output drive capability of the
AD8531/AD8532/AD8534 maintains this level for loads as
small as 32 Ω. For input signals less than 1 V p-p, the THD is
less than 0.1%, regardless of load. The design is a transformer-
less, balanced transmission system where output common-
mode rejection of noise is of paramount importance. As with
the transformer-based system, either output can be shorted
to ground for unbalanced line driver applications without changing
the circuit gain of 1. Other circuit gains can be set according to the
equation in the diagram. This allows the design to be easily
configured for inverting, noninverting, or differential operation.
R
L
600Ω
C1
22µF
A2 7
6
5
3
1
2
A1
5V
R1
10kΩ
R2
10kΩ
R11
10kΩ
R7
10kΩ
6
7
5
A1
12V
5V
R8
100kΩ
R9
100kΩ
C2
1µF
R12
10kΩ
R14
50Ω
A2 1
2
3
R3
10kΩ
R6
10kΩ
R13
10kΩ
C3
47µF
V
OUT1
V
OUT2
C4
47µF
A1, A2 = 1/2 AD8532
GAIN = R3
R2
SET: R7, R10, R11 = R2
SET: R6, R12, R13 = R3
V
IN
R10
10kΩ
R5
50Ω
01099-043
Figure 43. Single-Supply, Balanced Line Driver for Multimedia and
Automotive Applications
AD8531/AD8532/AD8534
Rev. F | Page 15 of 20
SINGLE-SUPPLY HEADPHONE AMPLIFIER
Because of its speed and large output drive, the AD8531/
AD8532/AD8534 make an excellent headphone driver, as
illustrated in Figure 44. Its low supply operation and rail-to-rail
inputs and outputs give a maximum signal swing on a single
5 V supply. To ensure maximum signal swing available to drive
the headphone, the amplifier inputs are biased to V+/2, which
in this case is 2.5 V. The 100 kΩ resistor to the positive supply
is equally split into two 50 kΩ resistors, with their common
point bypassed by 10 μF to prevent power supply noise from
contaminating the audio signal.
The audio signal is then ac-coupled to each input through a
10 μF capacitor. A large value is needed to ensure that the 20 Hz
audio information is not blocked. If the input already has the
proper dc bias, the ac coupling and biasing resistors are not
required. A 270 μF capacitor is used at the output to couple the
amplifier to the headphone. This value is much larger than that
used for the input because of the low impedance of the head-
phones, which can range from 32 Ω to 600 Ω. An additional 16 Ω
resistor is used in series with the output capacitor to protect the
output stage of the op amp by limiting the capacitor discharge
current. When driving a 48 Ω load, the circuit exhibits less
than 0.3% THD+N at output drive levels of 4 V p-p.
1/2
AD8532
16Ω
50kΩ
270µF LEFT
HEADPHONE
10µF
50kΩ
50kΩ
100kΩ
10µF
LEFT
INPUT
1/2
AD8532
16Ω
50kΩ
270µF
RIGHT
HEADPHONE
10µF
50kΩ
50kΩ
100kΩ
10µF
RIGHT
INPUT
V
V5V 1µF/0.1µF
V
5V
01099-044
Figure 44. Single-Supply, Stereo Headphone Driver
SINGLE-SUPPLY, 2-WAY LOUDSPEAKER
CROSSOVER NETWORK
Active filters are useful in loudspeaker crossover networks
because of small size, relative freedom from parasitic effects, the
ease of controlling low/high channel drive, and the controlled
driver damping provided by a dedicated amplifier. Both Sallen-
Key (SK) and multiple-feedback (MFB) filter architectures are
useful in implementing active crossover networks. The circuit
shown in Figure 45 is a single-supply, 2-way active crossover
that combines the advantages of both filter topologies.
This active crossover exhibits less than 0.4% THD+N at output
levels of 1.4 V rms using general-purpose, unity-gain HP/LP stages.
In this 2-way example, the LO signal is a dc-to-500 Hz LP woofer
output, and the HI signal is the HP (>500 Hz) tweeter output.
U1B forms an LP section at 500 Hz, while U1A provides an HP
section, covering frequencies ≥500 Hz.
V
IN
3
2
1
U1A
AD8532
V
S
4
R1
31.6kΩ
C1
0.01µF
C2
0.01µF
R2
31.6kΩ
R5
31.6kΩR6
31.6kΩ
R4
49.9Ω
HI
LO
500Hz
AND UP
DC –
500Hz
6
5
7
C3
0.01µF
U1B
AD8532
C4
0.02µF
R7
15.8kΩ
R3
49.9Ω270µF
270µF
100kΩ
V
S
10µF
100kΩ
100kΩ
C
IN
10µF
R
IN
100kΩ
0.1µ F
100µF/25V
V
S
TO U1
5V
COM
+
100kΩ
+
01099-045
Figure 45. A Single-Supply, 2-Way Active Crossover
The crossover example frequency of 500 Hz can be shifted
lower or higher by frequency scaling of either resistors or
capacitors. In configuring the circuit for other frequencies,
complementary LP/HP action must be maintained between
sections, and component values within the sections must be in
the same ratio. Table 6 provides a design aid to adaptation, with
suggested standard component values for other frequencies.
For additional information on the active filters and active crossover
networks, refer to the data sheet for the OP279, a dual rail-to-
rail, high output current, operational amplifier.
Table 6. RC Component Selection for Various Crossover
Frequencies1
Crossover Frequency (Hz) R1/C1 (U1A)2, R5/C3 (U1B)3
100 160 kΩ/0.01 μF
200 80.6 kΩ/0.01 μF
319 49.9 kΩ/0.01 μF
500 31.6 kΩ/0.01 μF
1 k 16 kΩ/0.01 μF
2 k 8.06 kΩ/0.01 μF
5 k 3.16 kΩ/0.01 μF
10 k 1.6 kΩ/0.01 μF
1 Applicable for Filter A = 2.
2 For Sallen-Key stage U1A: R1 = R2, and C1 = C2, and so on.
3 For multiple feedback stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3.
AD8531/AD8532/AD8534
Rev. F | Page 16 of 20
DIRECT ACCESS ARRANGEMENT FOR TELEPHONE
LINE INTERFACE
6.2V
6.2V
TRANSMIT
TxA
RECEIVE
RxA
C1
0.1µF
R1
10kΩ
R2
9.09kΩ
2kΩ
P1
Tx GAIN
ADJUST
A1
A2
A3
A4
A1, A2 = 1/2 AD8532
A3, A4 = 1/2 AD8532
R3
360Ω
1:1
T1
T
OTELEPHONE
LINE
1
2
3
7
6
5
2
3
1
6
5
7
10µF
R7
10kΩ
R8
10kΩ
R5
10kΩ
R6
10kΩ
R9
10kΩ
R14
14.3kΩ
R10
10kΩ
R11
10kΩ
R12
10kΩ
R13
10kΩ
C2
0.1µF
P2
Rx GAIN
ADJUST
2kΩ
Z
O
600Ω
5V DC
MIDCOM
671-8005
01099-046
Figure 46 illustrates a 5 V only transmit/receive telephone line
interface for 600 Ω transmission systems. It allows full duplex
transmission of signals on a transformer-coupled 600 Ω line in
a differential manner. A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the high output current
drive and low dropout voltage of the AD8531/AD8532/AD8534,
the largest signal available on a single 5 V supply is approximately
4.5 V p-p into a 600 Ω transmission system. A3 is configured as
a difference amplifier for two reasons: it prevents the transmit
signal from interfering with the receive signal, and it extracts
the receive signal from the transmission line for amplification
by A4. The gain of A4 can be adjusted in the same manner as
that of A1 to meet the input signal requirements of the modem.
Standard resistor values permit the use of single in-line package
(SIP) format resistor arrays. Figure 46. Single-Supply Direct Access Arrangement for Modems
AD8531/AD8532/AD8534
Rev. F | Page 17 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-203-AA
0.30
0.15
0.10 MAX
1.00
0.90
0.70
0.46
0.36
0.26
SEATING
PLANE
0.22
0.08
1.10
0.80
45
123
PIN 1
0.65 BSC
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
0.10 COPLANARITY
0.40
0.10
Figure 47. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
PIN 1
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
5
123
4
0.22
0.08
10°
5°
0°
0.50
0.30
0.15 MAX SEATING
PLANE
1.45 MAX
1.30
1.15
0.90
2.90 BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-A A
Figure 48. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 49. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
AD8531/AD8532/AD8534
Rev. F | Page 18 of 20
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 50. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
85
41
PIN 1
0.65 BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
0.20
0.09
8°
0°
6.40 BSC
4.50
4.40
4.30
3.10
3.00
2.90
COPLANARITY
0.10
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Figure 51. 8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
Dimensions shown in millimeters
4.50
4.40
4.30
14 8
71
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09
8°
0°
0.75
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
AD8531/AD8532/AD8534
Rev. F | Page 19 of 20
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 53. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
AD8531/AD8532/AD8534
Rev. F | Page 20 of 20
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8531AKS-R2 −40°C to +85°C 5-Lead SC70 KS-5 A7B
AD8531AKS-REEL7 −40°C to +85°C 5-Lead SC70 KS-5 A7B
AD8531AKSZ-R21−40°C to +85°C 5-Lead SC70 KS-5 A0Q
AD8531AKSZ-REEL71−40°C to +85°C 5-Lead SC70 KS-5 A0Q
AD8531ART-REEL −40°C to +85°C 5-Lead SOT-23 RJ-5 A7A
AD8531ART-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 A7A
AD8531ARTZ-REEL1−40°C to +85°C 5-Lead SOT-23 RJ-5 A0P
AD8531ARTZ-REEL71−40°C to +85°C 5-Lead SOT-23 RJ-5 A0P
AD8531AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8531AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD8531ARZ1−40°C to +85°C 8-Lead SOIC_N R-8
AD8531ARZ-REEL1−40°C to +85°C 8-Lead SOIC_N R-8
AD8532AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8532AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD8532AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD8532ARZ1−40°C to +85°C 8-Lead SOIC_N R-8
AD8532ARZ-REEL1−40°C to +85°C 8-Lead SOIC_N R-8
AD8532ARZ-REEL71−40°C to +85°C 8-Lead SOIC_N R-8
AD8532ARM-R2 −40°C to +85°C 8-Lead MSOP RM-8 ARA
AD8532ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 ARA
AD8532ARMZ-R21−40°C to +85°C 8-Lead MSOP RM-8 A0R
AD8532ARMZ-REEL1−40°C to +85°C 8-Lead MSOP RM-8 A0R
AD8532ARU −40°C to +85°C 8-Lead TSSOP RU-8
AD8532ARU-REEL −40°C to +85°C 8-Lead TSSOP RU-8
AD8532ARUZ1−40°C to +85°C 8-Lead TSSOP RU-8
AD8532ARUZ-REEL1−40°C to +85°C 8-Lead TSSOP RU-8
AD8534AR −40°C to +85°C 14-Lead SOIC_N R-14
AD8534AR-REEL −40°C to +85°C 14-Lead SOIC_N R-14
AD8534ARZ1−40°C to +85°C 14-Lead SOIC_N R-14
AD8534ARZ-REEL1−40°C to +85°C 14-Lead SOIC_N R-14
AD8534ARU −40°C to +85°C 14-Lead TSSOP RU-14
AD8534ARU-REEL −40°C to +85°C 14-Lead TSSOP RU-14
AD8534ARUZ1−40°C to +85°C 14-Lead TSSOP RU-14
AD8534ARUZ-REEL1−40°C to +85°C 14-Lead TSSOP RU-14
1 Z = RoHS Compliant Part.
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D01099-0-1/08(F)
