Low Cost, 250 mA Output, Single-Supply Amplifiers AD8531/AD8532/AD8534 PIN CONFIGURATIONS OUT A 1 Multimedia audio LCD drivers ASIC input or output amplifiers Headphone drivers 5 V+ 4 -IN A V- 2 +IN A 3 Figure 1. 5-Lead SC70 and 5-Lead SOT-23 (KS and RJ Suffixes) NC 1 APPLICATIONS AD8531 01099-001 Single-supply operation: 2.7 V to 6 V High output current: 250 mA Low supply current: 750 A/amplifier Wide bandwidth: 3 MHz Slew rate: 5 V/s No phase reversal Low input currents Unity gain stable Rail-to-rail input and output AD8531 8 NC -IN A 2 7 V+ +IN A 3 6 OUT A V- 4 5 NC NC = NO CONNECT 01099-002 FEATURES Figure 2. 8-Lead SOIC (R Suffix) The very low input bias currents enable the AD853x to be used for integrators, diode amplification, and other applications requiring low input bias current. Supply current is only 750 A per amplifier at 5 V, allowing low current applications to control high current loads. Applications include audio amplification for computers, sound ports, sound cards, and set-top boxes. The AD853x family is very stable, and it is capable of driving heavy capacitive loads such as those found in LCDs. The ability to swing rail-to-rail at the inputs and outputs enables designers to buffer CMOS DACs, ASICs, or other wide output swing devices in single-supply systems. OUT A 1 8 V+ -IN A 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B AD8532 Figure 3. 8-Lead SOIC, 8-Lead TSSOP, and 8-Lead MSOP (R, RU, and RM Suffixes) 14 OUT D OUT A 1 -IN A 13 -IN D 2 +IN A 3 V+ 4 +IN B 5 12 +IN D AD8534 11 V- 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C 01099-004 The AD8531, AD8532, and AD8534 are single, dual, and quad rail-to-rail input/output single-supply amplifiers featuring 250 mA output drive current. This high output current makes these amplifiers excellent for driving either resistive or capacitive loads. AC performance is very good with 3 MHz bandwidth, 5 V/s slew rate, and low distortion. All are guaranteed to operate from a 3 V single supply as well as a 5 V supply. 01099-003 GENERAL DESCRIPTION Figure 4. 14-Lead SOIC and 14-Lead TSSOP (R and RU Suffixes) The AD8531/AD8532/AD8534 are specified over the extended industrial temperature range (-40C to +85C). The AD8531 is available in 8-lead SOIC, 5-lead SC70, and 5-lead SOT-23 packages. The AD8532 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead TSSOP surface-mount packages. The AD8534 is available in narrow 14-lead SOIC and 14-lead TSSOP surface-mount packages. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1996-2008 Analog Devices, Inc. All rights reserved. AD8531/AD8532/AD8534 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Calculating Power by Measuring Ambient and Case Temperature ................................................................................ 12 General Description ......................................................................... 1 Calculating Power by Measuring Supply Current ................. 12 Pin Configurations ........................................................................... 1 Input Overvoltage Protection ................................................... 12 Revision History ............................................................................... 2 Output Phase Reversal............................................................... 13 Specifications..................................................................................... 3 Capacitive Load Drive ............................................................... 13 Electrical Characteristics............................................................. 3 Applications Information .............................................................. 14 Absolute Maximum Ratings............................................................ 5 High Output Current, Buffered Reference/Regulator........... 14 Thermal Resistance ...................................................................... 5 Single-Supply, Balanced Line Driver ....................................... 14 ESD Caution.................................................................................. 5 Single-Supply Headphone Amplifier....................................... 15 Typical Performance Characteristics ............................................. 6 Single-Supply, 2-Way Loudspeaker Crossover Network....... 15 Theory of Operation ...................................................................... 11 Direct Access Arrangement for Telephone Line Interface ... 16 Short-Circuit Protection............................................................ 11 Outline Dimensions ....................................................................... 17 Power Dissipation....................................................................... 11 Ordering Guide .......................................................................... 20 Power Calculations for Varying or Unknown Loads............. 12 REVISION HISTORY 1/08--Rev. E to Rev. F Changes to Layout ............................................................................ 5 Changes to Figure 12 and Figure 13............................................... 7 Changes to Figure 38...................................................................... 11 Changes to Input Overvoltage Protection Section..................... 12 Changes to Figure 43...................................................................... 14 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 20 4/05--Rev. D to Rev. E Updated Format..................................................................Universal Changes to Pin Configurations....................................................... 1 Changes to Table 4............................................................................ 5 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 10/02--Rev. C to Rev. D Deleted 8-Lead PDIP (N-8) .............................................. Universal Deleted 14-Lead PDIP (N-14) .......................................... Universal Edits to Figure 34...............................................................................9 Updated Outline Dimensions ........................................................15 8/96--Revision 0: Initial Version Rev. F | Page 2 of 20 AD8531/AD8532/AD8534 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 3.0 V, VCM = 1.5 V, TA = 25C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min Typ VOS -40C TA +85C Input Bias Current IB 5 -40C TA +85C Input Offset Current IOS 1 -40C TA +85C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density CMRR AVO VOS/T IB/T IOS/T VCM = 0 V to 3 V RL = 2 k, VO = 0.5 V to 2.5 V VOH IL = 10 mA -40C TA +85C IL = 10 mA -40C TA +85C VOL IOUT ZOUT 2.85 2.8 VS = 3 V to 6 V VO = 0 V -40C TA +85C SR tS GBP o CS RL = 2 k To 0.01% en Unit 25 30 50 60 25 30 3 mV mV pA pA pA pA V dB V/mV V/C fA/C fA/C 45 25 20 50 20 2.92 60 100 125 250 60 f = 1 MHz, AV = 1 PSRR ISY in 0 38 Max 45 55 0.70 1 1.25 V V mV mV mA dB mA mA f = 1 kHz, RL = 2 k 3.5 1.6 2.2 70 65 V/s s MHz Degrees dB f = 1 kHz f = 10 kHz f = 1 kHz 45 30 0.05 nV/Hz nV/Hz pA/Hz Rev. F | Page 3 of 20 AD8531/AD8532/AD8534 VS = 5.0 V, VCM = 2.5 V, TA = 25C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min Typ VOS -40C TA +85C Input Bias Current IB 5 -40C TA +85C Input Offset Current IOS 1 -40C TA +85C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density CMRR AVO VOS/T IB/T IOS/T VCM = 0 V to 5 V RL = 2 k, VO = 0.5 V to 4.5 V -40C TA +85C VOH IL = 10 mA -40C TA +85C IL = 10 mA -40C TA +85C VOL IOUT ZOUT 4.9 4.85 VS = 3 V to 6 V VO = 0 V -40C TA +85C SR BWp tS GBP o CS RL = 2 k 1% distortion To 0.01% en Unit 25 30 50 60 25 30 5 mV mV pA pA pA pA V dB V/mV V/C fA/C fA/C 47 80 20 50 20 4.94 50 100 125 250 40 f = 1 MHz, AV = 1 PSRR ISY in 0 38 15 Max 45 55 0.75 1.25 1.75 V V mV mV mA dB mA mA f = 1 kHz, RL = 2 k 5 350 1.4 3 70 65 V/s kHz s MHz Degrees dB f = 1 kHz f = 10 kHz f = 1 kHz 45 30 0.05 nV/Hz nV/Hz pA/Hz Rev. F | Page 4 of 20 AD8531/AD8532/AD8534 ABSOLUTE MAXIMUM RATINGS Table 3. -VOL +VOH 2.0 1.5 1.0 For supplies less than 6 V, the differential input voltage is equal to VS. 0.5 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 0 0 20 JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. JA 376 230 158 210 240 120 240 JC 126 146 43 45 43 36 43 40 60 80 100 120 RLOAD () 140 160 Figure 5. Output Voltage vs. Load, VS = 2.5 V, RLOAD Is Connected to GND (0 V) ESD CAUTION THERMAL RESISTANCE Package Type 5-Lead SC70 (KS) 5-Lead SOT-23 (RJ) 8-Lead SOIC (R) 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 14-Lead SOIC (R) 14-Lead TSSOP (RU) 01099-005 1 2.5 Rating 7V GND to VS 6 V -65C to +150C -40C to +85C -65C to +150C 300C VOUT Parameter Supply Voltage (VS) Input Voltage Differential Input Voltage1 Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Unit C/W C/W C/W C/W C/W C/W C/W Rev. F | Page 5 of 20 180 200 AD8531/AD8532/AD8534 TYPICAL PERFORMANCE CHARACTERISTICS VS = 2.7V VCM = 1.35V TA = 25C INPUT BIAS CURRENT (pA) 400 300 200 100 -10 -8 -6 -4 -2 0 INPUT OFFSET VOLTAGE (mV) 2 7 6 5 4 3 2 01099-006 -12 4 -35 Figure 6. Input Offset Voltage Distribution 5 25 45 TEMPERATURE (C) 65 85 VS = 5V TA = 25C 8 INPUT BIAS CURRENT (pA) QUANTITY (Amplifiers) -15 Figure 9. Input Bias Current vs. Temperature VS = 5V VCM = 2.5V TA = 25C 500 VS = 5V, 3V VCM = VS/2 01099-009 QUANTITY (Amplifiers) 500 8 400 300 200 6 5 4 3 2 -10 -8 -6 -4 -2 0 INPUT OFFSET VOLTAGE (mV) 2 4 0 Figure 7. Input Offset Voltage Distribution INPUT OFFSET CURRENT (pA) 5 -4 -5 -6 -7 -8 -15 5 25 45 TEMPERATURE (C) 65 VS = 5V, 3V VCM = VS/2 4 3 2 1 0 -1 01099-008 INPUT OFFSET VOLTAGE (mV) 6 -3 -35 5 Figure 10. Input Bias Current vs. Common-Mode Voltage VS = 5V VCM = 2.5V -2 1 2 3 4 COMMON-MODE VOLTAGE (V) -2 85 Figure 8. Input Offset Voltage vs. Temperature 01099-011 -12 01099-010 01099-007 100 7 -35 -15 5 25 45 TEMPERATURE (C) 65 Figure 11. Input Offset Current vs. Temperature Rev. F | Page 6 of 20 85 AD8531/AD8532/AD8534 VS = 2.7V TA = 25C 100 VS = 5V RL = NO LOAD TA = 25C 80 SOURCE GAIN (dB) SINK 10 1 60 45 40 90 20 135 0 180 0.01 0.1 1 LOAD CURRENT (mA) 10 01099-015 1k 100 5 VS = 5V TA = 25C OUTPUT SWING (V p-p) OUTPUT VOLTAGE (mV) SOURCE SINK 1 3 2 01099-013 0.01 0.1 1 LOAD CURRENT (mA) 10 0 1k 100 10k 100k FREQUENCY (Hz) 1M 10M Figure 16. Closed-Loop Output Swing vs. Frequency Figure 13. Output Voltage to Supply Rail vs. Load Current 5 VS = 2.7V RL = NO LOAD TA = 25C VS = 5V TA = 25C RL = 2k VIN = 4.9V p-p 45 40 90 20 135 0 180 PHASE SHIFT (Degrees) 60 OUTPUT SWING (V p-p) 4 80 3 2 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 14. Open-Loop Gain and Phase Shift vs. Frequency 0 1k 01099-017 1 01099-014 GAIN (dB) 100M 1 0.1 0.01 0.001 10M VS = 2.7V TA = 25C RL = 2k VIN = 2.5V p-p 4 100 10 100k 1M FREQUENCY (Hz) Figure 15. Open-Loop Gain and Phase Shift vs. Frequency Figure 12. Output Voltage to Supply Rail vs. Load Current 1000 10k 01099-016 0.01 0.001 01099-012 0.1 10k 100k FREQUENCY (Hz) 1M Figure 17. Closed-Loop Output Swing vs. Frequency Rev. F | Page 7 of 20 10M PHASE SHIFT (Degrees) OUTPUT VOLTAGE (mV) 1000 AD8531/AD8532/AD8534 IMPEDANCE () 140 120 100 80 AV = 10 60 AV = 1 01099-018 40 20 0 1k 10k 100k 1M LOAD CURRENT (mA) 10M 0.1 01099-021 160 VS = 5V TA = 25C 0.01 10 100M 100 Figure 18. Closed-Loop Output Impedance vs. Frequency 110 VS = 5V AV = 1000 TA = 25C FREQUENCY = 1kHz 100V/DIV 10 0% 90 80 70 60 01099-019 40 1k Figure 19. Voltage Noise Density vs. Frequency (1 kHz) 10k 100k FREQUENCY (Hz) 1M 10M Figure 22. Common-Mode Rejection vs. Frequency 140 VS = 5V AV = 1000 TA = 25C FREQUENCY = 10kHz POWER SUPPLY REJECTION (dB) 120 200V/DIV 90 VS = 5V TA = 25C 100 50 MARKER 41V/Hz 100 100k 01099-022 90 10k Figure 21. Current Noise Density vs. Frequency COMMON-MODE REJECTION (dB) 100 1k FREQUENCY (Hz) 10 01099-020 0% VS = 2.7V TA = 25C 100 80 60 PSSR- 40 20 PSSR+ 0 -20 01099-023 180 1 VS = 5V TA = 25C CURRENT NOISE DENSITY (pA/Hz) 200 -40 -60 100 MARKER 25.9V/Hz Figure 20. Voltage Noise Density vs. Frequency (10 kHz) 1k 10k 100k FREQUENCY (Hz) 1M Figure 23. Power Supply Rejection vs. Frequency Rev. F | Page 8 of 20 10M AD8531/AD8532/AD8534 80 PSSR- 60 PSSR+ 20 0 -20 -60 100 1k 10k 100k FREQUENCY (Hz) 1M 50 SMALL SIGNAL OVERSHOOT (%) VS = 2.7V TA = 25C RL = 2k 30 -OS 20 +OS 10 0 10 100 1000 CAPACITANCE (pF) 10000 40 VS = 2.7V TA = 25C RL = 600 30 20 -OS 10 100 1000 CAPACITANCE (pF) 10000 Figure 28. Small Signal Overshoot vs. Load Capacitance 0.90 SUPPLY CURRENT/AMPLIFIER (mA) VS = 5V TA = 25C RL = 2k 40 -OS 30 +OS 20 10 0 10 10000 +OS 01099-026 SMALL SIGNAL OVERSHOOT (%) 50 100 1000 CAPACITANCE (pF) 0 10 Figure 25. Small Signal Overshoot vs. Load Capacitance 60 10 Figure 27. Small Signal Overshoot vs. Load Capacitance 01099-025 SMALL SIGNAL OVERSHOOT (%) 40 +OS 20 0 10 10M Figure 24. Power Supply Rejection vs. Frequency 50 -OS 01099-028 -40 30 100 1000 CAPACITANCE (pF) 0.85 0.80 0.75 0.70 0.65 0.60 Figure 26. Small Signal Overshoot vs. Load Capacitance VS = 3V 0.55 0.50 -40 10000 VS = 5V 01099-029 40 40 VS = 5V TA = 25C RL = 600 01099-027 100 01099-024 POWER SUPPLY REJECTION (dB) 120 50 VS = 5V TA = 25C SMALL SIGNAL OVERSHOOT (%) 140 -20 0 20 40 TEMPERATURE (C) 60 80 Figure 29. Supply Current per Amplifier vs. Temperature Rev. F | Page 9 of 20 AD8531/AD8532/AD8534 TA = 25C 90 0.6 0.5 0.4 0.3 10 0.2 0.1 1.00 1.50 2.00 SUPPLY VOLTAGE (V) 2.50 500mV 500ns 01099-033 0% 0 0.75 3.00 Figure 33. Large Signal Transient Response Figure 30. Supply Current per Amplifier vs. Supply Voltage VS = 1.35V VIN = 50mV AV = 1 RL = 2k CL = 300pF TA = 25C 20mV/DIV VS = 2.5V AV = 1 RL = 2k TA = 25C 100 0.7 01099-030 SUPPLY CURRENT/AMPLIFIER (mA) 0.8 VS = 1.35V AV = 1 RL = 2k TA = 25C 100 90 0V 10 500mV 500ns 01099-034 01099-031 0% 500 ns/DIV Figure 34. Large Signal Transient Response Figure 31. Small Signal Transient Response 1V 10s 100 VS = 2.5V VIN = 50mV AV = 1 RL = 2k CL = 300pF TA = 25C 10 0% 01099-035 0V 01099-032 20mV/DIV 90 1V 500ns/DIV Figure 35. No Phase Reversal Figure 32. Small Signal Transient Response Rev. F | Page 10 of 20 AD8531/AD8532/AD8534 THEORY OF OPERATION Figure 36 illustrates a simplified equivalent circuit for the AD8531/AD8532/AD8534. Like many rail-to-rail input amplifier configurations, it comprises two differential pairs, one N-channel (M1 to M2) and one P-channel (M3 to M4). These differential pairs are biased by 50 A current sources, each with a compliance limit of approximately 0.5 V from either supply voltage rail. The differential input voltage is then converted into a pair of differential output currents. These differential output currents are then combined in a compound folded-cascade second gain stage (M5 to M9). The outputs of the second gain stage at M8 and M9 provide the gate voltage drive to the rail-to-rail output stage. Additional signal current recombination for the output stage is achieved using M11 to M14. To achieve rail-to-rail output swings, the AD8531/AD8532/ AD8534 design employs a complementary, common source output stage (M15 to M16). However, the output voltage swing is directly dependent on the load current because the difference between the output voltage and the supply is determined by the AD8531/AD8532/AD8534's output transistors on channel resistance (see Figure 12 and Figure 13). The output stage also exhibits voltage gain by virtue of the use of common source amplifiers; as a result, the voltage gain of the output stage (thus, the open-loop gain of the device) exhibits a strong dependence on the total load resistance at the output of the AD8531/ AD8532/AD8534. V+ 50A 100A 20A 100A M11 M12 M5 VB2 M3 As a result of the design of the output stage for the maximum load current capability, the AD8531/AD8532/AD8534 do not have any internal short-circuit protection circuitry. Direct connection of the output of the AD8531/AD8532/AD8534 to the positive supply in single-supply applications destroys the device. In applications where some protection is needed, but not at the expense of reduced output voltage headroom, a low value resistor in series with the output, as shown in Figure 37, can be used. The resistor, connected within the feedback loop of the amplifier, has very little effect on the performance of the amplifier other than limiting the maximum available output voltage swing. For single 5 V supply applications, resistors less than 20 are not recommended. 5V VIN AD8532 RX 20 POWER DISSIPATION Although the AD8531/AD8532/AD8534 are capable of providing load currents to 250 mA, the usable output load current drive capability is limited to the maximum power dissipation allowed by the device package used. In any application, the absolute maximum junction temperature for the AD8531/AD8532/AD8534 is 150C. The maximum junction temperature should never be exceeded because the device could suffer premature failure. Accurately measuring power dissipation of an integrated circuit is not always a straightforward exercise; therefore, Figure 38 is provided as a design aid for either setting a safe output current drive level or selecting a heat sink for the package options available on the AD8531/AD8532/AD8534. 1.5 M4 M2 TJ MAX = 150C FREE AIR NO HEAT SINK M15 IN- VOUT Figure 37. Output Short-Circuit Protection M8 VB3 M9 M14 20A 50A M7 M10 M13 V- SOIC 1.0 JA = 158C/W MSOP JA = 210C/W SOT-23 JA = 230C/W SC70 0.5 = 376C/W JA Figure 36. Simplified Equivalent Circuit TSSOP JA = 240C/W 0 0 25 50 TEMPERATURE (C) 01099-038 IN+ M16 POWER DISSIPATION (W) OUT M6 01099-036 M1 SHORT-CIRCUIT PROTECTION 01099-037 The AD8531/AD8532/AD8534 are all CMOS, high output current drive, rail-to-rail input/output operational amplifiers. Their high output current drive and stability with heavy capacitive loads make the AD8531/AD8532/AD8534 excellent choices as drive amplifiers for LCD panels. 75 85 100 Figure 38. Maximum Power Dissipation vs. Ambient Temperature Rev. F | Page 11 of 20 AD8531/AD8532/AD8534 The thermal resistance curves were determined using the AD8531/AD8532/AD8534 thermal resistance data for each package and a maximum junction temperature of 150C. The following formula can be used to calculate the internal junction temperature of the AD8531/AD8532/AD8534 for any application: TJ = PDISS x JA + TA The two equations can be solved for P (power) PDISS = (TA - TC)/(JC - JA) Once power is determined, it is necessary to go back and calculate the junction temperature to ensure that it has not been exceeded. The temperature measurements should be directly on the package and on a spot on the board that is near the package but not touching it. Measuring the package could be difficult. A very small bimetallic junction glued to the package can be used, or measurement can be done using an infrared sensing device if the spot size is small enough. To calculate the power dissipated by the AD8531/AD8532/ AD8534, the following equation can be used: PDISS = ILOAD x (VS - VOUT) where: ILOAD is the output load current. VS is the supply voltage. VOUT is the output voltage. CALCULATING POWER BY MEASURING SUPPLY CURRENT The quantity within the parentheses is the maximum voltage developed across either output transistor. As an additional design aid in calculating available load current from the AD8531/AD8532/AD8534, Figure 5 illustrates the output voltage of the AD8531/AD8532/AD8534 as a function of load resistance. POWER CALCULATIONS FOR VARYING OR UNKNOWN LOADS Often, calculating power dissipated by an integrated circuit to determine if the device is being operated in a safe range is not as simple as it may seem. In many cases, power cannot be directly measured, which may be the result of irregular output waveforms or varying loads; indirect methods of measuring power are required. There are two methods to calculate power dissipated by an integrated circuit. The first can be done by measuring the package temperature and the board temperature, and the other is to directly measure the supply current of the circuit. CALCULATING POWER BY MEASURING AMBIENT AND CASE TEMPERATURE Given the two equations for calculating junction temperature where: TJ is the junction temperature. TA is the ambient temperature. JA is the junction to ambient thermal resistance. where: TC is the case temperature. JA and JC are given in the data sheet. TA + PDISS JA = TC + PJC where: TJ is the junction temperature. PDISS is the power dissipation. JA is the package thermal resistance, junction-to-case. TA is the ambient temperature of the circuit. TJ = TA + PDISS JA TJ = TC + PDISS JA Power can be calculated directly, knowing the supply voltage and current. However, supply current may have a dc component with a pulse into a capacitive load, which can make rms current very difficult to calculate. It can be overcome by lifting the supply pin and inserting an rms current meter into the circuit. For this to work, be sure the current is being delivered by the supply pin being measured. This is usually a good method in a single-supply system; however, if the system uses dual supplies, both supplies may need to be monitored. INPUT OVERVOLTAGE PROTECTION As with any semiconductor device, whenever the condition exists for the input to exceed either supply voltage, the input overvoltage characteristic of the device must be considered. When an overvoltage occurs, the amplifier can be damaged, depending on the magnitude of the applied voltage and the magnitude of the fault current. Although not shown here, when the input voltage exceeds either supply by more than 0.6 V, pn junctions internal to the AD8531/AD8532/AD8534 energize, allowing current to flow from the input to the supplies. As illustrated in the simplified equivalent input circuit (see Figure 36), the AD8531/AD8532/AD8534 do not have any internal current limiting resistors; therefore, fault currents can quickly rise to damaging levels. This input current is not inherently damaging to the device, as long as it is limited to 5 mA or less. For the AD8531/AD8532/ AD8534, once the input voltage exceeds the supply by more than 0.6 V, the input current quickly exceeds 5 mA. If this condition continues to exist, an external series resistor should be added. The size of the resistor is calculated by dividing the maximum overvoltage by 5 mA. For example, if the input voltage could reach 10 V, the external resistor should be (10 V/5 mA) = 2 k. This resistance should be placed in series with either or both inputs if they are exposed to an overvoltage condition. Rev. F | Page 12 of 20 AD8531/AD8532/AD8534 OUTPUT PHASE REVERSAL 5V CAPACITIVE LOAD DRIVE The AD8531/AD8532/AD8534 exhibit excellent capacitive load driving capabilities. They can drive up to 10 nF directly, as shown in Figure 25 through Figure 28. However, even though the device is stable, a capacitive load does not come without a penalty in bandwidth. As shown in Figure 39, the bandwidth is reduced to less than 1 MHz for loads greater than 10 nF. A snubber network on the output does not increase the bandwidth, but it does significantly reduce the amount of overshoot for a given capacitive load. A snubber consists of a series RC network (RS, CS), as shown in Figure 40, connected from the output of the device to ground. This network operates in parallel with the load capacitor, CL, to provide phase lag compensation. The actual value of the resistor and capacitor is best determined empirically. AD8532 VIN 100mV p-p RS 5 CS 1F VOUT CL 47nF 01099-040 Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. The AD8531/ AD8532/AD8534 are free from reasonable input voltage range restrictions, provided that input voltages no greater than the supply voltage rails are applied. Although the output of the device does not change phase, large currents can flow through internal junctions to the supply rails, which was described in the Input Overvoltage Protection section. Without limit, these fault currents can easily destroy the amplifier. The technique recommended in the Input Overvoltage Protection section should therefore be applied in those applications where the possibility of input voltages exceeding the supply voltages exists. Figure 40. Snubber Network Compensates for Capacitive Loads The first step is to determine the value of the resistor, RS. A good starting value is 100 . This value is reduced until the small signal transient response is optimized. Next, CS is determined; 10 F is a good starting point. This value is reduced to the smallest value for acceptable performance (typically, 1 F). For the case of a 47 nF load capacitor on the AD8531/AD8532/AD8534, the optimal snubber network is 5 in series with 1 F. The benefit is immediately apparent, as seen in Figure 41. The top trace was taken with a 47 nF load, and the bottom trace was taken with the 5 in series with a 1 F snubber network in place. The amount of overshoot and ringing is dramatically reduced. Table 5 illustrates a few sample snubber networks for large load capacitors. Table 5. Snubber Networks for Large Capacitive Loads Load Capacitance (CL) 0.47 nF 4.7 nF 47 nF Snubber Network (RS, CS) 300 , 0.1 F 30 , 1 F 5 , 1 F 50mV 100 47nF LOAD 90 ONLY 4.0 VS = 2.5V RL = 1k TA = 25C 3.5 2.5 1.5 50mV 1.0 0.5 0 0.01 0.1 1 CAPACITIVE LOAD (nF) 10 10s Figure 41. Overshoot and Ringing Are Reduced by Adding a Snubber Network in Parallel with the 47 nF Load 100 Figure 39. Unity-Gain Bandwidth vs. Capacitive Load Rev. F | Page 13 of 20 01099-041 SNUBBER 10 IN CIRCUIT 0% 2.0 01099-039 BANDWIDITH (MHz) 3.0 AD8531/AD8532/AD8534 APPLICATIONS INFORMATION Many applications require stable voltage outputs relatively close in potential to an unregulated input source. This low dropout type of reference/regulator is readily implemented with a railto-rail output op amp and is particularly useful when using a higher current device, such as the AD8531/AD8532/AD8534. A typical example is the 3.3 V or 4.5 V reference voltage developed from a 5 V system source. Generating these voltages requires a three terminal reference, such as the REF196 (3.3 V) or the REF194 (4.5 V), both of which feature low power, with sourcing outputs of 30 mA or less. Figure 42 shows how such a reference can be outfitted with an AD8531/AD8532/AD8534 buffer for higher currents and/or voltage levels, plus sink and source load capability. VS 5V U2 AD8531 C1 0.1F VOUT1 = 3.3V @ 100mA R2 10k 1% R1 10k 1% VC ON/OFF CONTROL INPUT CMOS HI (OR OPEN) = ON LO = OFF 2 3 U1 REF196 4 C2 0.1F R3 (See Text) 6 VOUT2 = 3.3V C5 100F/16V TANTALUM R5 0.2 C4 1F R4 3.3k VS COMMON VOUT COMMON 01099-042 C3 0.1F Figure 42. High Output Current Reference/Regulator The low dropout performance of this circuit is provided by stage U2, an AD8531 connected as a follower/buffer for the basic reference voltage produced by U1. The low voltage saturation characteristic of the AD8531/AD8532/AD8534 allows up to 100 mA of load current in the illustrated use, as a 5 V to 3.3 V converter with good dc accuracy. In fact, the dc output voltage change for a 100 mA load current delta measures less than 1 mV. This corresponds to an equivalent output impedance of < 0.01 . In this application, the stable 3.3 V from U1 is applied to U2 through a noise filter, R1 to C1. U2 replicates the U1 voltage within a few millivolts, but at a higher current output at VOUT1, with the ability to both sink and source output current(s), unlike most IC references. R2 and C2 in the feedback path of U2 provide additional noise filtering. Transient performance of the reference/regulator for a 100 mA step change in load current is also quite good and is largely determined by the R5 to C5 output network. With values as shown, the transient is about 20 mV peak and settles to within 2 mV in less than 10 s for either polarity. Although room exists for optimizing the transient response, any changes to the R5 to C5 network should be verified by experiment to preclude the possibility of excessive ringing with some capacitor types. To scale VOUT2 to another (higher) output level, the optional resistor R3 (shown dotted in Figure 42) is added, causing the new VOUT1 to become R2 VOUT1 = VOUT2 x 1 + R3 The circuit can either be used as shown, as a 5 V to 3.3 V reference/regulator, or with on/off control. By driving Pin 3 of U1 with a logic control signal as noted, the output is switched on/off. Note that when on/off control is used, R4 must be used with U1 to speed on/off switching. SINGLE-SUPPLY, BALANCED LINE DRIVER The circuit in Figure 43 is a unique line driver circuit topology used in professional audio applications. It was modified for automotive and multimedia audio applications. On a single 5 V supply, the line driver exhibits less than 0.7% distortion into a 600 load from 20 Hz to 15 kHz (not shown) with an input signal level of 4 V p-p. In fact, the output drive capability of the AD8531/AD8532/AD8534 maintains this level for loads as small as 32 . For input signals less than 1 V p-p, the THD is less than 0.1%, regardless of load. The design is a transformerless, balanced transmission system where output commonmode rejection of noise is of paramount importance. As with the transformer-based system, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily configured for inverting, noninverting, or differential operation. R3 10k R5 50 2 3 R2 10k A2 VIN 5V 6 GAIN = R3 R2 1 7 R1 10k R11 R12 10k 10k A1 A1, A2 = 1/2 AD8532 VOUT1 12V 2 3 C3 47F R6 10k R7 10k 5V C1 22F 1 R10 10k SET: R7, R10, R11 = R2 6 5 A2 R8 100k A1 5 7 R13 10k R9 100k R14 50 RL 600 C2 1F C4 47F VOUT2 SET: R6, R12, R13 = R3 Rev. F | Page 14 of 20 Figure 43. Single-Supply, Balanced Line Driver for Multimedia and Automotive Applications 01099-043 HIGH OUTPUT CURRENT, BUFFERED REFERENCE/REGULATOR AD8531/AD8532/AD8534 Because of its speed and large output drive, the AD8531/ AD8532/AD8534 make an excellent headphone driver, as illustrated in Figure 44. Its low supply operation and rail-to-rail inputs and outputs give a maximum signal swing on a single 5 V supply. To ensure maximum signal swing available to drive the headphone, the amplifier inputs are biased to V+/2, which in this case is 2.5 V. The 100 k resistor to the positive supply is equally split into two 50 k resistors, with their common point bypassed by 10 F to prevent power supply noise from contaminating the audio signal. This active crossover exhibits less than 0.4% THD+N at output levels of 1.4 V rms using general-purpose, unity-gain HP/LP stages. In this 2-way example, the LO signal is a dc-to-500 Hz LP woofer output, and the HI signal is the HP (>500 Hz) tweeter output. U1B forms an LP section at 500 Hz, while U1A provides an HP section, covering frequencies 500 Hz. C1 0.01F 2 R2 31.6k CIN 10F 4 R5 31.6k R6 31.6k C4 0.02F 100k 100k DC - 500Hz 270F + C3 0.01F LO 100k 6 7 5 U1B 10F VS TO U1 R4 49.9 R7 15.8k VS AD8532 5V 0.1F 1F/0.1F AD8532 1 RIN 100k V 5V V 5V HI 100k U1A 3 VIN 500Hz AND UP VS C2 0.01F The audio signal is then ac-coupled to each input through a 10 F capacitor. A large value is needed to ensure that the 20 Hz audio information is not blocked. If the input already has the proper dc bias, the ac coupling and biasing resistors are not required. A 270 F capacitor is used at the output to couple the amplifier to the headphone. This value is much larger than that used for the input because of the low impedance of the headphones, which can range from 32 to 600 . An additional 16 resistor is used in series with the output capacitor to protect the output stage of the op amp by limiting the capacitor discharge current. When driving a 48 load, the circuit exhibits less than 0.3% THD+N at output drive levels of 4 V p-p. 50k R3 49.9 270F + R1 31.6k 100F/25V 01099-045 SINGLE-SUPPLY HEADPHONE AMPLIFIER COM Figure 45. A Single-Supply, 2-Way Active Crossover 10F 50k LEFT INPUT 1/2 AD8532 16 270F LEFT HEADPHONE 50k 10F 100k V 50k 50k 10F 1/2 AD8532 16 270F RIGHT HEADPHONE 50k 100k 01099-044 RIGHT INPUT 10F Figure 44. Single-Supply, Stereo Headphone Driver SINGLE-SUPPLY, 2-WAY LOUDSPEAKER CROSSOVER NETWORK Active filters are useful in loudspeaker crossover networks because of small size, relative freedom from parasitic effects, the ease of controlling low/high channel drive, and the controlled driver damping provided by a dedicated amplifier. Both SallenKey (SK) and multiple-feedback (MFB) filter architectures are useful in implementing active crossover networks. The circuit shown in Figure 45 is a single-supply, 2-way active crossover that combines the advantages of both filter topologies. The crossover example frequency of 500 Hz can be shifted lower or higher by frequency scaling of either resistors or capacitors. In configuring the circuit for other frequencies, complementary LP/HP action must be maintained between sections, and component values within the sections must be in the same ratio. Table 6 provides a design aid to adaptation, with suggested standard component values for other frequencies. For additional information on the active filters and active crossover networks, refer to the data sheet for the OP279, a dual rail-torail, high output current, operational amplifier. Table 6. RC Component Selection for Various Crossover Frequencies 1 Crossover Frequency (Hz) 100 200 319 500 1k 2k 5k 10 k 1 R1/C1 (U1A) 2 , R5/C3 (U1B) 3 160 k/0.01 F 80.6 k/0.01 F 49.9 k/0.01 F 31.6 k/0.01 F 16 k/0.01 F 8.06 k/0.01 F 3.16 k/0.01 F 1.6 k/0.01 F Applicable for Filter A = 2. For Sallen-Key stage U1A: R1 = R2, and C1 = C2, and so on. 3 For multiple feedback stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3. 2 Rev. F | Page 15 of 20 AD8531/AD8532/AD8534 DIRECT ACCESS ARRANGEMENT FOR TELEPHONE LINE INTERFACE TO TELEPHONE LINE 1:1 2k R3 360 1 2 A1 R5 10k 6.2V ZO 600 R2 9.09k C1 R1 10k 0.1F TRANSMIT TxA 3 6.2V 5V DC T1 MIDCOM 671-8005 R6 10k 6 7 A2 R7 10k 5 R8 10k 10F R9 10k R11 10k A1, A2 = 1/2 AD8532 A3, A4 = 1/2 AD8532 Rev. F | Page 16 of 20 R12 10k R10 10k 2 3 A3 1 R13 R14 10k 14.3k 2k 6 5 P2 Rx GAIN ADJUST A4 7 RECEIVE RxA C2 0.1F Figure 46. Single-Supply Direct Access Arrangement for Modems 01099-046 Figure 46 illustrates a 5 V only transmit/receive telephone line interface for 600 transmission systems. It allows full duplex transmission of signals on a transformer-coupled 600 line in a differential manner. A1 provides gain that can be adjusted to meet the modem output drive requirements. Both A1 and A2 are configured to apply the largest possible signal on a single supply to the transformer. Because of the high output current drive and low dropout voltage of the AD8531/AD8532/AD8534, the largest signal available on a single 5 V supply is approximately 4.5 V p-p into a 600 transmission system. A3 is configured as a difference amplifier for two reasons: it prevents the transmit signal from interfering with the receive signal, and it extracts the receive signal from the transmission line for amplification by A4. The gain of A4 can be adjusted in the same manner as that of A1 to meet the input signal requirements of the modem. Standard resistor values permit the use of single in-line package (SIP) format resistor arrays. P1 Tx GAIN ADJUST AD8531/AD8532/AD8534 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 5 2.40 2.10 1.80 4 1 2 3 PIN 1 0.65 BSC 1.00 0.90 0.70 1.10 0.80 0.30 0.15 0.10 MAX 0.40 0.10 0.46 0.36 0.26 0.22 0.08 SEATING PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 47. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters 2.90 BSC 5 4 2.80 BSC 1.60 BSC 1 2 3 PIN 1 0.95 BSC 1.90 BSC 1.30 1.15 0.90 1.45 MAX 0.15 MAX 0.50 0.30 0.22 0.08 10 5 0 SEATING PLANE 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-A A Figure 48. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 49. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. F | Page 17 of 20 012407-A 4.00 (0.1574) 3.80 (0.1497) AD8531/AD8532/AD8534 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.38 0.22 0.80 0.60 0.40 8 0 0.23 0.08 SEATING PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 50. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 3.10 3.00 2.90 8 5 4.50 4.40 4.30 1 6.40 BSC 4 PIN 1 0.65 BSC 0.15 0.05 1.20 MAX COPLANARITY 0.10 0.30 0.19 SEATING 0.20 PLANE 0.09 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AA Figure 51. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 SEATING COPLANARITY PLANE 0.10 8 0 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. F | Page 18 of 20 0.75 0.60 0.45 AD8531/AD8532/AD8534 8.75 (0.3445) 8.55 (0.3366) 8 14 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 53. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. F | Page 19 of 20 060606-A 4.00 (0.1575) 3.80 (0.1496) AD8531/AD8532/AD8534 ORDERING GUIDE Model AD8531AKS-R2 AD8531AKS-REEL7 AD8531AKSZ-R2 1 AD8531AKSZ-REEL71 AD8531ART-REEL AD8531ART-REEL7 AD8531ARTZ-REEL1 AD8531ARTZ-REEL71 AD8531AR AD8531AR-REEL AD8531ARZ1 AD8531ARZ-REEL1 AD8532AR AD8532AR-REEL AD8532AR-REEL7 AD8532ARZ1 AD8532ARZ-REEL1 AD8532ARZ-REEL71 AD8532ARM-R2 AD8532ARM-REEL AD8532ARMZ-R21 AD8532ARMZ-REEL1 AD8532ARU AD8532ARU-REEL AD8532ARUZ1 AD8532ARUZ-REEL1 AD8534AR AD8534AR-REEL AD8534ARZ1 AD8534ARZ-REEL1 AD8534ARU AD8534ARU-REEL AD8534ARUZ1 AD8534ARUZ-REEL1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 5-Lead SC70 5-Lead SC70 5-Lead SC70 5-Lead SC70 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Z = RoHS Compliant Part. (c)1996-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01099-0-1/08(F) Rev. F | Page 20 of 20 Package Option KS-5 KS-5 KS-5 KS-5 RJ-5 RJ-5 RJ-5 RJ-5 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RU-8 RU-8 RU-8 RU-8 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14 Branding A7B A7B A0Q A0Q A7A A7A A0P A0P ARA ARA A0R A0R