DS12885, DS12885Q, DS12885T
Real Time Clock
DS12885, DS12885Q, DS12885T
022798 1/6
FEATURES
•Drop–in replacement for IBM AT computer clock/ca-
lendar
•Pin configuration closely matches MC146818B and
DS1285
•Counts seconds, minutes, hours, days, day of the
week, date, month, and year with leap year compen-
sation valid up to 2100
•Binary or BCD representation of time, calendar, and
alarm
•12– or 24–hour clock with AM and PM in 12–hour
mode
•Daylight Savings Time option
•Selectable between Motorola and Intel bus timing
•Multiplex bus for pin efficiency
•Interfaced with software as 128 RAM locations
- 14 bytes of clock and control registers
- 114 bytes of general purpose RAM
•Programmable square wave output signal
•Bus compatible interrupt signals (IRQ)
•Three interrupts are separately software–maskable
and testable
- T ime–of–day alarm once/second to once/day
- Periodic rates from 122 µs to 500 ms
- End of clock update cycle
•Optional 28–pin PLCC surface mount package or
32–pin TQFP
•Optional industrial temperature range available
DESCRIPTION
The DS12885 Real Time Clock plus RAM is designed to
be a direct replacement for the DS1285. The DS12885
is identical in form, fit, and function to the DS1285, and
has an additional 64 bytes of general purpose RAM. Ac-
cess to this additional RAM space is determined by the
logic level presented on AD6 during the address portion
of an access cycle. An external crystal and battery are
the only components required to maintain time–of–day
and memory status in the absence of power. For a com-
plete description of operating conditions, electrical
characteristics, bus timing, and pin descriptions other
than X1, X2, VBAT, and RCLR, see the DS12887 data
sheet.
PIN ASSIGNMENT
RESET
IRQ
VBAT
RCLR
DS12885 24–PIN DIP
VCC
SQW
NC
RCLR
VBAT
IRQ
RESET
DS
GND
R/W
AS
CS
MOT
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
4321 RCLR
VBAT
IRQ
RESET
DS
GND
R/W
28 27 26
25
24
23
22
21
20
19
DS12885Q
28–PIN PLCC
X1
MOT
NC
VCC
SQW
NC
X2AD6
AD7
GND
CS
AS
NC
12 13 14 1516 17 18
AD0
AD1
AD2
AD3
AD4
AD5
NC
5
6
7
8
9
10
11
NC
DS12885S 24–PIN SOIC
NC
NC
DS
GND
AD0
AD1
AD2
NC
AD3
NC
AD4
AD5
AD6
NC
AD7
GND
CS
AS
NC
R/W
NC
X2
X1
MOT
VCC
NC
SQW
NC
DS12885T
32–PIN TQFP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 101112131415 16
32 31 30 29 28 27 26 25
DS12885, DS12885Q, DS12885T
022798 2/6
PIN DESCRIPTION
AD0–AD7 – Multiplexed Address/Data Bus
NC – No Connection
MOT – Bus Type Selection
CS – Chip Select
AS – Address Strobe
R/W – Read/W rite Input
DS – Data Strobe
RESET – Reset Input
IRQ – Interrupt Request Output (open
drain)
SQW – Square Wave Output
Vcc – +5 Volt Supply
GND – Ground
X1,X2 – 32.768 kHz Crystal Connections
VBAT – +3 volt Battery Input
RCLR – RAM Clear
PIN DESCRIPTION
X1, X2 – Connections for a standard 32.768 kHz quartz
crystal. The internal oscillator circuitry is designed for
operation with a crystal having a specified load capaci-
tance (CL) of 6 pF. The crystal is connected directly to
the X1 and X2 pins. There is no need for external capac-
itors or resistors. Note: X1 and X2 are very high imped-
ance nodes. It is recommended that they and the crystal
be guard–ringed with ground and that high frequency
signals be kept away from the crystal area. For more
information on crystal selection and crystal layout con-
siderations, please consult Application Note 58, “Crys-
tal Considerations with Dallas Real T ime Clocks”.
VBAT – Battery input for any standard 3 volt lithium cell or
other energy source. Battery voltage must be held be-
tween 2.5 and 4 volts for proper operation. A maximum
load of 0.5 µA at 25°C in the absence of power should be
used to size the external energy source.
The battery should be connected directly to the VBAT
pin. A diode must not be placed in series with the battery
to the VBAT pin. Furthermore, a diode is not necessary
because reverse charging current protection circuitry is
provided internal to the device and has passed the
requirements of Underwriters Laboratories for UL
listing.
RCLR – The RCLR pin is used to clear (set to logic 1) all
114 bytes of general purpose RAM but does not affect
the RAM associated with the real time clock. In order to
clear the RAM, RCLR must be forced to an input logic
“0” (–0.3 to +0.8 volts) during battery back–up mode
when VCC is not applied. The RCLR function is de-
signed to be used via human interface (shorting to
ground manually or by switch) and not to be driven with
external buf fers. This pin is internally pulled up. Do not
use an external pull–up resistor on this pin.
DS12885, DS12885Q, DS12885T
022798 3/6
DS12885 24–PIN DIP
1
C
A
B D
H
J
KGE
F
DIM MIN MAX
24–PINPKG
A IN. 1.245 1.270
MM 31.62 32.25
B IN. 0.530 0.550
MM 13.46 13.97
C IN. 0.145 0.165
MM 3.68 4.19
D IN. 0.600 0.625
MM 15.24 15.88
E IN. 0.015 0.050
MM 0.380 1.27
F IN. 0.120 0.145
MM 3.05 3.68
G IN. 0.090 0.110
MM 2.29 2.79
H IN. 0.625 0.675
MM 15.88 17.15
J IN. 0.008 0.012
MM 0.20 0.30
K IN. 0.015 0.022
MM 0.38 0.559
DS12885, DS12885Q, DS12885T
022798 4/6
DS12885 24–PIN SOIC
J
K G
C
EA
F
L
phi
DIM MIN MAX
24–PINPKG
B H
A IN. 0.602 0.612
MM 15.29 15.54
B IN. 0.290 0.300
MM 7.37 7.65
C IN. 0.089 0.095
MM 2.26 2.41
E IN. 0.004 0.012
MM 0.102 0.30
F IN. 0.094 0.105
MM 2.38 2.68
G IN. 0.050 BSC
MM 1.27 BSC
H IN. 0.398 0.416
MM 10.11 10.57
J IN. 0.009 0.013
MM 0.229 0.33
K IN. 0.013 0.019
MM 0.33 0.48
L IN. 0.016 0.040
MM 0.406 1.02
phi 0°8°
DS12885, DS12885Q, DS12885T
022798 5/6
DS12885Q 28–PIN PLCC
H
B1
DIM MIN MAX
28–PINPKG
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
7.62
0.442
17.68 0.462
11.73
0.027
0.68 0.033
0.84
0.480
12.2 0.500
12.7
0.090
2.29 0.120
3.05
0.020
0.51 MIN
MIN
0.390
9.91 0.430
10.92
0.165
4.19 0.180
4.57
B1 IN.
MM 0.013
0.33 0.021
0.53
0.300 REF
0.010 R (3X) 45 DEG.
DS12885, DS12885Q, DS12885T
022798 6/6
DS12885T 32–PIN TQFP
