DS12885, DS12885Q, DS12885T DS12885, DS12885Q, DS12885T Real Time Clock * * X2 3 22 NC AD0 4 21 RCLR AD1 5 20 VBAT AD2 6 19 IRQ AD3 7 18 RESET AD4 8 17 DS AD5 9 16 GND AD6 10 15 R/W AD7 11 14 AS GND 12 13 CS AD0 AD1 AD2 AD3 AD4 8 9 AD5 10 NC 11 NC 3 2 NC 4 5 6 7 VCC SQW DS12885 24-PIN DIP DS12885S 24-PIN SOIC 1 28 27 26 25 24 23 DS12885Q 22 28-PIN PLCC 21 RCLR VBAT IRQ RESET DS 20 GND 19 12 13 14 15 16 17 18 R/W NC * * * SQW CS AS * * * * VCC 23 GND * 24 2 X2 * 1 X1 X1 MOT * MOT NC AD7 * lendar Pin configuration closely matches MC146818B and DS1285 Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation valid up to 2100 Binary or BCD representation of time, calendar, and alarm 12- or 24-hour clock with AM and PM in 12-hour mode Daylight Savings Time option Selectable between Motorola and Intel bus timing Multiplex bus for pin efficiency Interfaced with software as 128 RAM locations - 14 bytes of clock and control registers - 114 bytes of general purpose RAM Programmable square wave output signal Bus compatible interrupt signals (IRQ) Three interrupts are separately software-maskable and testable - Time-of-day alarm once/second to once/day - Periodic rates from 122 s to 500 ms - End of clock update cycle Optional 28-pin PLCC surface mount package or 32-pin TQFP Optional industrial temperature range available PIN ASSIGNMENT AD6 * Drop-in replacement for IBM AT computer clock/ca- NC X2 X1 MOT VCC NC SQW NC FEATURES DESCRIPTION AD0 AD1 AD2 NC AD3 NC AD4 AD5 32 31 30 29 28 27 26 25 24 1 23 2 22 3 21 4 DS12885T 32-PIN TQFP 20 5 19 6 18 7 17 8 9 10 11 12 13 14 15 16 RCLR NC VBAT IRQ NC RESET DS GND AD6 NC AD7 GND CS AS NC R/W The DS12885 Real Time Clock plus RAM is designed to be a direct replacement for the DS1285. The DS12885 is identical in form, fit, and function to the DS1285, and has an additional 64 bytes of general purpose RAM. Access to this additional RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle. An external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power. For a complete description of operating conditions, electrical characteristics, bus timing, and pin descriptions other than X1, X2, VBAT, and RCLR, see the DS12887 data sheet. 022798 1/6 DS12885, DS12885Q, DS12885T PIN DESCRIPTION AD0-AD7 NC MOT CS AS R/W DS RESET IRQ drain) SQW Vcc GND X1,X2 VBAT RCLR - - - - - - - - - Multiplexed Address/Data Bus No Connection Bus Type Selection Chip Select Address Strobe Read/Write Input Data Strobe Reset Input Interrupt Request Output (open - - - - - - Square Wave Output +5 Volt Supply Ground 32.768 kHz Crystal Connections +3 volt Battery Input RAM Clear PIN DESCRIPTION X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. For more 022798 2/6 information on crystal selection and crystal layout considerations, please consult Application Note 58, "Crystal Considerations with Dallas Real Time Clocks". VBAT - Battery input for any standard 3 volt lithium cell or other energy source. Battery voltage must be held between 2.5 and 4 volts for proper operation. A maximum load of 0.5 A at 25C in the absence of power should be used to size the external energy source. The battery should be connected directly to the VBAT pin. A diode must not be placed in series with the battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current protection circuitry is provided internal to the device and has passed the requirements of Underwriters Laboratories for UL listing. RCLR - The RCLR pin is used to clear (set to logic 1) all 114 bytes of general purpose RAM but does not affect the RAM associated with the real time clock. In order to clear the RAM, RCLR must be forced to an input logic "0" (-0.3 to +0.8 volts) during battery back-up mode when VCC is not applied. The RCLR function is designed to be used via human interface (shorting to ground manually or by switch) and not to be driven with external buffers. This pin is internally pulled up. Do not use an external pull-up resistor on this pin. DS12885, DS12885Q, DS12885T DS12885 24-PIN DIP PKG MIN MAX A IN. MM 1.245 31.62 1.270 32.25 B IN. MM 0.530 13.46 0.550 13.97 C IN. MM 0.145 3.68 0.165 4.19 D IN. MM 0.600 15.24 0.625 15.88 E IN. MM 0.015 0.380 0.050 1.27 C F IN. MM 0.120 3.05 0.145 3.68 F G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.625 15.88 0.675 17.15 J IN. MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.38 0.022 0.559 B D 1 A K G E 24-PIN DIM J H 022798 3/6 DS12885, DS12885Q, DS12885T DS12885 24-PIN SOIC K G PKG B C H DIM MIN MAX A IN. MM 0.602 15.29 0.612 15.54 B IN. MM 0.290 7.37 0.300 7.65 C IN. MM 0.089 2.26 0.095 2.41 E IN. MM 0.004 0.102 0.012 0.30 F IN. MM 0.094 2.38 0.105 2.68 G IN. MM 0.050 BSC 1.27 BSC H IN. MM 0.398 10.11 0.416 10.57 J IN. MM 0.009 0.229 0.013 0.33 K IN. MM 0.013 0.33 0.019 0.48 L IN. MM 0.016 0.406 0.040 1.02 0 8 A E phi F phi 022798 4/6 24-PIN J L DS12885, DS12885Q, DS12885T DS12885Q 28-PIN PLCC 0.010 R (3X) H 45 DEG. B1 PKG 28-PIN DIM MIN A IN. MM 0.300 REF 7.62 MAX B IN. MM 0.442 17.68 0.462 11.73 B1 IN. MM 0.013 0.33 0.021 0.53 C IN. MM 0.027 0.68 0.033 0.84 D IN. MM 0.480 12.2 0.500 12.7 E IN. MM 0.090 2.29 0.120 3.05 F IN. MM 0.020 0.51 MIN MIN G IN. MM 0.390 9.91 0.430 10.92 H IN. MM 0.165 4.19 0.180 4.57 022798 5/6 DS12885, DS12885Q, DS12885T DS12885T 32-PIN TQFP 022798 6/6