© Semiconductor Components Industries, LLC, 2010
January, 2010 Rev. 23
1Publication Order Number:
CS5171/D
CS5171, CS5172, CS5173,
CS5174
1.5 A 280 kHz/560 kHz
Boost Regulators
The CS5171/2/3/4 products are 280 kHz/560 kHz switching
regulators with a high efficiency, 1.5 A integrated switch. These parts
operate over a wide input voltage range, from 2.7 V to 30 V. The
flexibility of the design allows the chips to operate in most power
supply configurations, including boost, flyback, forward, inverting,
and SEPIC. The ICs utilize current mode architecture, which allows
excellent load and line regulation, as well as a practical means for
limiting current. Combining high frequency operation with a highly
integrated regulator circuit results in an extremely compact power
supply solution. The circuit design includes provisions for features
such as frequency synchronization, shutdown, and feedback controls
for either positive or negative voltage regulation. These parts are
pintopin compatible with LT1372/1373.
Part Number Frequency Feedback Voltage Polarity
CS5171 280 kHz positive
CS5172 280 kHz negative
CS5173 560 kHz positive
CS5174 560 kHz negative
Features
Integrated Power Switch: 1.5 A Guaranteed
Wide Input Range: 2.7 V to 30 V
High Frequency Allows for Small Components
Minimum External Components
Easy External Synchronization
Built in Overcurrent Protection
Frequency Foldback Reduces Component Stress During an
Overcurrent Condition
Thermal Shutdown with Hysteresis
Regulates Either Positive or Negative Output Voltages
Shut Down Current: 50 mA Maximum
PintoPin Compatible with LT1372/1373
Wide Temperature Range
Industrial Grade: 40°C to 125°C
Commercial Grade: 0°C to 125°C
PbFree Packages are Available
517xy = Device Code
x= 1, 2, 3, or 4
y= E, G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
ORDERING INFORMATION
CS5171/3
CS5172/4
SOIC8
D SUFFIX
CASE 751
VCC
SS
1
517xy
ALYW
G
8
AGNDTest
PGNDFB
VSW
VC
MARKING DIAGRAM AND
PIN CONNECTIONS
VCC
SS
1
517xy
ALYW
G
8
AGNDNFB
PGND
Test
VSW
VC
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See detailed ordering and shipping information in the
package dimensions section on page 20 of this data sheet.
1
8
CS5171, CS5172, CS5173, CS5174
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2
+
CS5171/3
1
2
3
45
6
7
8VOUT
L1
5 V
C3
22 mF
VC
FB
Test
SS VCC
AGND
PGND
VSW
+
MBRS120T3
D1
22 mH
C2
22 mF
R3
1.28 k
3.72 k
R2
C1
SS
3.3 V
R1
5 k
0.01 mF
Figure 1. Applications Diagram
MAXIMUM RATINGS
Rating Value Unit
Junction Temperature Range, TJ40 to +150 °C
Storage Temperature Range, TSTORAGE 65 to +150 °C
Package Thermal Resistance, JunctiontoCase, RqJC
JunctiontoAmbient, RqJA
45
165
°C/W
°C/W
Lead Temperature Soldering: Reflow (Note 1) 230 Peak °C
ESD, Human Body Model 1.2 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Name Pin Symbol VMAX VMIN ISOURCE ISINK
IC Power Input VCC 35 V 0.3 V N/A 200 mA
Shutdown/Sync SS 30 V 0.3 V 1.0 mA 1.0 mA
Loop Compensation VC6.0 V 0.3 V 10 mA 10 mA
Voltage Feedback Input FB
(CS5171/3 only)
10 V 0.3 V 1.0 mA 1.0 mA
Negative Feedback Input
(transient, 10 ms)
NFB
(CS5172/4 only)
10 V 10 V 1.0 mA 1.0 mA
Test Pin Test 6.0 V 0.3 V 1.0 mA 1.0 mA
Power Ground PGND 0.3 V 0.3 V 4 A 10 mA
Analog Ground AGND 0 V 0 V N/A 10 mA
Switch Input VSW 40 V 0.3 V 10 mA 3.0 A
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ELECTRICAL CHARACTERISTICS (2.7 V< VCC < 30 V; Industrial Grade: 40°C < TJ < 125°C;
Commercial Grade: 0°C < TJ < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.)
Characteristic Test Conditions Min Typ Max Unit
Positive and Negative Error Amplifiers
FB Reference Voltage (CS5171/3 only) VC tied to FB; measure at FB 1.246 1.276 1.300 V
NFB Reference Voltage (CS5172/4 only) VC = 1.25 V 2.55 2.45 2.35 V
FB Input Current (CS5171/3 only) FB = VREF 1.0 0.1 1.0 mA
NFB Input Current (CS5172/4 only) NFB = NVREF 16 10 5.0 mA
FB Reference Voltage Line Regulation
(CS5171/3 only)
VC = FB 0.01 0.03 %/V
NFB Reference Voltage Line Regulation
(CS5172/4 only)
VC = 1.25 V 0.01 0.05 %/V
Positive Error Amp Transconductance IVC = ±25 mA300 550 800 mMho
Negative Error Amp Transconductance IVC = ±5 mA115 160 225 mMho
Positive Error Amp Gain (Note 2) 200 500 V/V
Negative Error Amp Gain (Note 2) 100 180 320 V/V
VC Source Current FB = 1.0 V or NFB = 1.9 V, VC = 1.25 V 25 50 90 mA
VC Sink Current FB = 1.5 V or NFB = 3.1 V, VC = 1.25 V 200 625 1500 mA
VC High Clamp Voltage FB = 1.0 V or NFB = 1.9 V;
VC sources 25 mA
1.5 1.7 1.9 V
VC Low Clamp Voltage FB = 1.5 V or NFB = 3.1 V, VC sinks 25 mA0.25 0.50 0.65 V
VC Threshold Reduce VC from 1.5 V until switching stops 0.75 1.05 1.30 V
Oscillator
Base Operating Frequency CS5171/2, FB = 1 V or NFB = 1.9 V 230 280 310 kHz
Reduced Operating Frequency CS5171/2, FB = 0 V or NFB = 0 V 30 52 120 kHz
Maximum Duty Cycle CS5171/2 90 94 %
Base Operating Frequency CS5173/4, FB = 1 V or NFB = 1.9 V 460 560 620 kHz
Reduced Operating Frequency CS5173/4, FB = 0 V or NFB = 0 V 60 104 160 kHz
Maximum Duty Cycle CS5173/4 82 90 %
NFB Frequency Shift Threshold Frequency drops to reduced operating frequency 0.80 0.65 0.50 V
FB Frequency Shift Threshold Frequency drops to reduced operating frequency 0.36 0.40 0.44 V
Sync/ Shutdown
Sync Range CS5171/2 320 500 kHz
Sync Range CS5173/4 640 1000 kHz
Sync Pulse Transition Threshold Rise time = 20 ns 2.5 V
SS Bias Current SS = 0 V
SS = 3.0 V
15
3.0
3.0
8.0
mA
mA
Shutdown Threshold 0.50 0.85 1.20 V
Shutdown Delay 2.7 V VCC 12 V
12 V < VCC 30 V
12
12
80
36
350
200
ms
ms
2. Guaranteed by design, not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (2.7 V< VCC < 30 V; Industrial Grade: 40°C < TJ < 125°C;
Commercial Grade: 0°C < TJ < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.)
Characteristic UnitMaxTypMinTest Conditions
Power Switch
Switch Saturation Voltage ISWITCH = 1.5 A, (Note 3)
ISWITCH = 1.0 A, 0°C TJ 85°C
ISWITCH = 1.0 A, 40°C TJ 0°C
ISWITCH = 10 mA
0.8
0.55
0.75
0.09
1.4
0.45
V
V
V
V
Switch Current Limit 50% duty cycle, (Note 3)
80% duty cycle, (Note 3)
1.6
1.5
1.9
1.7
2.4
2.2
A
A
Minimum Pulse Width FB = 0 V or NFB = 0 V, ISW = 4.0 A, (Note 3) 200 250 300 ns
DICC/ DIVSW 2.7 V VCC 12 V, 10 mA ISW 1.0 A
12 V < VCC 30 V, 10 mA ISW 1.0 A
2.7 V VCC 12 V, 10 mA ISW 1.5 A, (Note 3)
12 V < VCC 30 V, 10 mA ISW 1.5 A, (Note 3)
10
17
30
100
30
100
mA/A
mA/A
mA/A
mA/A
Switch Leakage VSW = 40 V, VCC = 0V 2.0 100 mA
General
Operating Current ISW = 0 5.5 8.0 mA
Shutdown Mode Current VC < 0.8 V, SS = 0 V, 2.7 V VCC 12 V
VC < 0.8 V, SS = 0 V, 12 V VCC 30 V
12
60
100
mA
Minimum Operation Input Voltage VSW switching, maximum ISW = 10 mA 2.45 2.70 V
Thermal Shutdown (Note 3) 150 180 210 °C
Thermal Hysteresis (Note 3) 25 °C
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
Package
Pin #
Pin
Symbol Function
1 VCLoop compensation pin. The VC pin is the output of the error amplifier and is used for loop compensation,
current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the
application diagram on page 2 as R1 and C1.
2
(CS5171/3
only)
FB Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When
the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency.
2
(CS5172/4)
3
CS5171/3)
Test These pins are connected to internal test logic and should either be left floating or tied to ground. Connection
to a voltage between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running.
3
(CS5172/4)
NFB Negative feedback pin. This pin senses a negative output voltage and is referenced to 2.5 V. When the
voltage at this pin goes above 0.65 V, chip switching frequency reduces to 20% of the nominal frequency.
4 SS Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base
frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used,
this pin should be either tied high or left floating for normal operation.
5 VCC Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to
AGND.
6 AGND Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of
large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is
connected to the IC substrate.
CS5171, CS5172, CS5173, CS5174
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PACKAGE PIN DESCRIPTION
Package
Pin # Function
Pin
Symbol
7 PGND Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection
to a good ground plane is essential.
8 VSW High current switch pin. This pin connects internally to the collector of the power switch. The open voltage
across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical.
PGND
VSW
+
+
+
VCC
SS
NFB
FB
AGND
Positive
Error Amp
CS5172/4
only
CS5171/3
only
Negative
Error Amp
PWM Compar-
ator
Ramp
Summer
Slope
Compensation
Thermal
Shutdown
2.0 V
Regulator
Delay
Timer
Sync
Shutdown
Oscillator
Frequency
Shift 5:1
SPWM
Latch
R
QDriver Switch
63 mW
0.65 V Detector
0.4 V Detector
1.276 V
250 k
200 k
2.0 V
VC
×5
Fi
g
ure 2. Block Dia
g
ram
CS5171, CS5172, CS5173, CS5174
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6
TYPICAL PERFORMANCE CHARACTERISTICS
0
Temperature (°C)
Figure 3. ICC (No Switching) vs. Temperature
Current (mA)
7.2
7.0
6.8
6.6
6.4
6.2
6.0
5.8
VCC = 30 V
5.6 50 100
VCC = 12 V
VCC = 2.7 V
0
Temperature (°C)
Figure 4. DICC/ DIVSW vs. Temperature
(mA/A)
70
60
50
40
30
20
10
50 100
VCC = 30 V
VCC = 12 V
VCC = 2.7 V
ISW = 1.5 A
0
ISW (mA)
Figure 5. VCE(SAT) vs. ISW
VCE(SAT) (mV)
1200
1000
800
600
400
200
0500 1000
40 °C
85 °C
25 °C
Temperature (°C)
Figure 6. Minimum Input Voltage vs. Temperature
VIN (V)
1.5
1.6
1.7
1.8
1.9
0 10050
Temperature (°C)
Figure 7. Switching Frequency vs. Temperature
(CS5171/2 only)
fOSC (kHz)
255
260
265
270
275
0 10050
280
285
Temperature (°C)
Figure 8. Switching Frequency vs. Temperature
(CS5173/4 only)
fOSC (kHz)
540
545
550
555
560
0 10050
565
570
535
530
525
520
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TYPICAL PERFORMANCE CHARACTERISTICS
Temperature (°C)
Voltage (V)
1.268
1.270
1.272
1.274
1.276
0 10050
1.278
1.280
VCC = 12 V
VCC = 2.7 V VCC = 30 V
Temperature (°C)
Voltage (V)
2.48
2.47
2.46
2.45
2.44
0 10050
2.43
2.42
VCC = 12 V
VCC = 30 V
VCC = 2.7 V
Temperature (°C)
IFB (mA)
0.08
0.10
0.12
0.14
0.16
0 10050
0.18
0.20
VCC = 12 V
VCC = 2.7 V
0
VFB (mV)
fOSC (% of Typical)
100
75
50
25
350
VCC = (12 V)
380 400 420 450
85°C
25°C
40°C
0
VNFB (mV)
fOSC (% of Typical)
100
75
50
25
550
VCC = (12 V)
85°C
25°C
40°C
660 725
Temperature (°C)
INFB (mA)
7
8
10
0 50 100
9
11
12
13
14
Figure 9. Switching Frequency vs. VFB
(CS5171/3 only)
Figure 10. Switching Frequency vs. VNFB
(CS5172/4 only)
Figure 11. Reference Voltage vs. Temperature
(CS5171/3 only)
Figure 12. Reference Voltage vs. Temperature
(CS5172/4 only)
Figure 13. IFB vs. Temperature (CS5171/3 only) Figure 14. INFB vs. Temperature (CS5172/ 4 only)
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TYPICAL PERFORMANCE CHARACTERISTICS
Temperature (°C)
Voltage (V)
0.5
0.6
0.7
0.8
0.9
0100
50
1.0
1.1
0.4
Temperature (°C)
Current (A)
2.20
2.30
2.40
2.50
0 10050
2.60
VCC = 12 V VCC = 30 V
VCC = 2.7 V
Temperature (°C)
Delay (ms)
80
100
120
140
0 10050
160
VCC = 12 V
VCC = 30 V
VCC = 2.7 V
60
40
Temperature (°C)
Duty Cycle (%)
95
96
97
98
0 10050
99 VCC = 30 V
VCC = 2.7 V
94
93
VSS (V)
ISS (mA)
10
20
30
40
175
40°C
0
10
85°C
25°C
39
VCC = 12 V
Temperature (°C)
Voltage (V)
0.7
0.9
1.1
1.3
0 10050
1.5
1.7
VC High Clamp Voltage
VC Threshold
Figure 15. Current Limit vs. Temperature Figure 16. Maximum Duty Cycle vs. Temperature
Figure 17. VC Threshold and High Clamp
Voltage vs. Temperature
Figure 18. Shutdown Threshold vs. Temperature
Figure 19. Shutdown Delay vs. Temperature Figure 20. ISS vs. VSS
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TYPICAL PERFORMANCE CHARACTERISTICS
VIN (V)
ICC (mA)
20
30
40
10
40°C
10
0
85°C
25°C
VREF VFB (mV)
IOUT (mA)
20
60
100
0
20
60 252575
125175255
Temperature (°C)
gm (mmho)
450
500
0 10050
550
600
VREF VNFB (mV)
IOUT (mA)
20
60
100
0
20
60 5050
100150200
80
40
0
40
Temperature (°C)
gm (mmho)
160
170
0 10050
180
190
150
140
130
120
110
100
Temperature (°C)
Current (mA)
2.6
0 10050
2.5
2.4
2.3
2.2
2.1
2.0
Figure 21. ICC vs. VIN During Shutdown Figure 22. Error Amplifier Transconductance
vs. Temperature (CS5171/3 only)
Figure 23. Negative Error Amplifier
Transconductance vs. Temperature (CS5172/4 only)
Figure 24. Error Amplifier IOUT vs. VFB
(CS5171/3 only)
Figure 25. Error Amplifier IOUT vs. VNFB
(CS5172/4 only)
Figure 26. Switch Leakage vs. Temperature
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APPLICATIONS INFORMATION
THEORY OF OPERATION
Current Mode Control
+
Driver
CORLOAD
VSW
X5
SUMMER
Slope Compensation
VC
Oscillator
D1
VCC
S
R
Q
In Out
PWM
Comparator
L
63 mW
Figure 27. Current Mode Control Scheme
Power Switch
The CS517x family incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the ontime of the
power switch. The oscillator is used as a fixedfrequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulsebypulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows both a simpler compensation and a higher
gainbandwidth over a comparable voltage mode circuit.
Without discrediting its apparent merits, current mode
control comes with its own peculiar problems, mainly,
subharmonic oscillation at duty cycles over 50%. The
CS517x family solves this problem by adopting a slope
compensation scheme in which a fixed ramp generated by
the oscillator is added to the current ramp. A proper slope
rate is provided to improve circuit stability without
sacrificing the advantages of current mode control.
Oscillator and Shutdown
Figure 28. Timing Diagram of Sync and Shutdown
VSW
Current
Ramp
Sync
The oscillator is trimmed to guarantee an 18% frequency
accuracy. The output of the oscillator turns on the power
switch at a frequency of 280 kHz (CS5171/2) or 560 kHz
(CS5173/4), as shown in Figure 27. The power switch is
turned off by the output of the PWM Comparator.
A TTLcompatible sync input at the SS pin is capable of
syncing up to 1.8 times the base oscillator frequency. As
shown in Figure 28, in order to sync to a higher frequency,
a positive transition turns on the power switch before the
output of the oscillator goes high, thereby resetting the
oscillator. The sync operation allows multiple power
supplies to operate at the same frequency.
A sustained logic low at the SS pin will shut down the IC
and reduce the supply current.
An additional feature includes frequency shift to 20% of
the nominal frequency when either the NFB or FB pins
trigger the threshold. During power up, overload, or short
circuit conditions, the minimum switch ontime is limited
by the PWM comparator minimum pulse width. Extra
switch offtime reduces the minimum duty cycle to protect
external components and the IC itself.
As previously mentioned, this block also produces a ramp
for the slope compensation to improve regulator stability.
Error Amplifier
+
+
CS5172/4
CS5171/3
Figure 29. Error Amplifier Equivalent Circuit
2.0 V
200 k
250 k
1MW
positive erroramp
negative erroramp
1.276 V
FB
NFB
VC
C1
R1
5 kW
0.01 mF
Voltage
Clamp
120 pF
For CS5172/4, the NFB pin is internally referenced to
2.5 V with approximately a 250 kW input impedance. For
CS5171/3, the FB pin is directly connected to the inverting
input of the positive error amplifier, whose noninverting
input is fed by the 1.276 V reference. Both amplifiers are
transconductance amplifiers with a high output impedance
of approximately 1 MW, as shown in Figure 29. The VC pin
is connected to the output of the error amplifiers and is
internally clamped between 0.5 V and 1.7 V. A typical
connection at the VC pin includes a capacitor in series with
a resistor to ground, forming a pole/zero for loop
compensation.
An external shunt can be connected between the VC pin
and ground to reduce its clamp voltage. Consequently, the
current limit of the internal power transistor current is
reduced from its nominal value.
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11
Switch Driver and Power Switch
The switch driver receives a control signal from the logic
section to drive the output power switch. The switch is
grounded through emitter resistors (63 mW total) to the
PGND pin. PGND is not connected to the IC substrate so that
switching noise can be isolated from the analog ground. The
peak switching current is clamped by an internal circuit. The
clamp current is guaranteed to be greater than 1.5 A and
varies with duty cycle due to slope compensation. The
power switch can withstand a maximum voltage of 40 V on
the collector (VSW pin). The saturation voltage of the switch
is typically less than 1 V to minimize power dissipation.
Short Circuit Condition
When a short circuit condition happens in a boost circuit,
the inductor current will increase during the whole
switching cycle, causing excessive current to be drawn from
the input power supply. Since control ICs don’t have the
means to limit load current, an external current limit circuit
(such as a fuse or relay) has to be implemented to protect the
load, power supply and ICs.
In other topologies, the frequency shift built into the IC
prevents damage to the chip and external components. This
feature reduces the minimum duty cycle and allows the
transformer secondary to absorb excess energy before the
switch turns back on.
Figure 30. Startup Waveforms of Circuit Shown in
the Application Diagram. Load = 400 mA.
IL
VOUT
VC
VCC
The CS517x can be activated by either connecting the
VCC pin to a voltage source or by enabling the SS pin.
Startup waveforms shown in Figure 30 are measured in the
boost converter demonstrated in the Application Diagram
on the page 2 of this document. Recorded after the input
voltage is turned on, this waveform shows the various
phases during the power up transition.
When the VCC voltage is below the minimum supply
voltage, the VSW pin is in high impedance. Therefore,
current conducts directly from the input power source to the
output through the inductor and diode. Once VCC reaches
approximately 1.5 V, the internal power switch briefly turns
on. This is a part of the CS517x’s normal operation. The
turnon of the power switch accounts for the initial current
swing.
When the VC pin voltage rises above the threshold, the
internal power switch starts to switch and a voltage pulse can
be seen at the VSW pin. Detecting a low output voltage at the
FB pin, the builtin frequency shift feature reduces the
switching frequency to a fraction of its nominal value,
reducing the minimum duty cycle, which is otherwise
limited by the minimum ontime of the switch. The peak
current during this phase is clamped by the internal current
limit.
When the FB pin voltage rises above 0.4 V, the frequency
increases to its nominal value, and the peak current begins
to decrease as the output approaches the regulation voltage.
The overshoot of the output voltage is prevented by the
active pullon, by which the sink current of the error
amplifier is increased once an overvoltage condition is
detected. The overvoltage condition is defined as when the
FB pin voltage is 50 mV greater than the reference voltage.
COMPONENT SELECTION
Frequency Compensation
The goal of frequency compensation is to achieve
desirable transient response and DC regulation while
ensuring the stability of the system. A typical compensation
network, as shown in Figure 31, provides a frequency
response of two poles and one zero. This frequency response
is further illustrated in the Bode plot shown in Figure 32.
CS5171
Figure 31. A Typical Compensation Network
VC
GND
C1
R1
C2
The high DC gain in Figure 32 is desirable for achieving
DC accuracy over line and load variations. The DC gain of
a transconductance error amplifier can be calculated as
follows:
GainDC +GM RO
where:
GM = error amplifier transconductance;
RO = error amplifier output resistance 1 MW.
The low frequency pole, fP1, is determined by the error
amplifier output resistance and C1 as:
fP1 +1
2pC1RO
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The first zero generated by C1 and R1 is:
fZ1 +1
2pC1R1
The phase lead provided by this zero ensures that the loop
has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
fP+1
2pCORLOAD
where:
CO = equivalent output capacitance of the error amplifier
120pF;
RLOAD= load resistance.
The high frequency pole, fP2, can be placed at the output
filters ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
fP2 +1
2pC2R1
One simple method to ensure adequate phase margin is to
design the frequency response with a 20 dB per decade
slope, until unitygain crossover. The crossover frequency
should be selected at the midpoint between fZ1 and fP2 where
the phase margin is maximized.
Figure 32. Bode Plot of the Compensation Network
Shown in Figure 31
Frequency (LOG)
fP1
Gain (dB)
DC Gain
fZ1
fP2
Negative Voltage Feedback
Since the negative error amplifier has finite input
impedance as shown in Figure 33, its induced error has to be
considered. If a voltage divider is used to scale down the
negative output voltage for the NFB pin, the equation for
calculating output voltage is:
*VOUT +
ǒ
*2.5
(
R1 )R2
)
R2
Ǔ
*10 mA R1
+
Figure 33. Negative Error Amplifier and NFB Pin
2 V
200 kW
Negative ErrorAmp
RP
NFB RIN
VOUT
R1
250 kW
R2
It is shown that if R1 is less than 10 k, the deviation from
the design target will be less than 0.1 V. If the tolerances of
the negative voltage reference and NFB pin input current are
considered, the possible offset of the output VOFFSET varies
in the range of:
ǒ*0.0.5 (R1 )R2)
R2 Ǔ*(15 mA R1) vVOFFSET
v
ǒ
0.0.5 (R1 )R2)
R2
Ǔ
*(5 mA R1
)
VSW Voltage Limit
In the boost topology, VSW pin maximum voltage is set by
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes
VSW(MAX) +VOUT(MAX))VF
where:
VF = output diode forward voltage.
In the flyback topology, peak VSW voltage is governed by:
VSW(MAX) +VCC(MAX))(VOUT)VF) N
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
spike superimposed on top of the steadystate voltage.
Usually this voltage spike is caused by transformer leakage
inductance charging stray capacitance between the VSW and
PGND pins. To prevent the voltage at the VSW pin from
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
the VSW pin and ground.
CS5171, CS5172, CS5173, CS5174
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13
Magnetic Component Selection
When choosing a magnetic component, one must consider
factors such as peak current, core and ferrite material, output
voltage ripple, EMI, temperature range, physical size and
cost. In boost circuits, the average inductor current is the
product of output current and voltage gain (VOUT/VCC),
assuming 100% energy transfer efficiency. In continuous
conduction mode, inductor ripple current is
IRIPPLE +VCC(VOUT *VCC)
(f)(L)(VOUT)
where:
f = 280 kHz for CS5171/2 and 560 kHz for CS5173/4.
The peak inductor current is equal to average current plus
half of the ripple current, which should not cause inductor
saturation. The above equation can also be referenced when
selecting the value of the inductor based on the tolerance of
the ripple current in the circuits. Small ripple current
provides the benefits of small input capacitors and greater
output current capability. A core geometry like a rod or
barrel is prone to generating high magnetic field radiation,
but is relatively cheap and small. Other core geometries,
such as toroids, provide a closed magnetic loop to prevent
EMI.
Input Capacitor Selection
In boost circuits, the inductor becomes part of the input
filter, as shown in Figure 35. In continuous mode, the input
current waveform is triangular and does not contain a large
pulsed current, as shown in Figure 34. This reduces the
requirements imposed on the input capacitor selection.
During continuous conduction mode, the peak to peak
inductor ripple current is given in the previous section. As
we can see from Figure 34, the product of the inductor
current ripple and the input capacitors effective series
resistance (ESR) determine the VCC ripple. In most
applications, input capacitors in the range of 10 mF to 100 mF
with an ESR less than 0.3 W work well up to a full 1.5 A
switch current.
VCC ripple
Figure 34. Boost Input Voltage and Current
Ripple Waveforms
IIN
IL
+
Figure 35. Boost Circuit Effective Input Filter
VCC CIN
RESR
IL
IIN
The situation is different in a flyback circuit. The input
current is discontinuous and a significant pulsed current is
seen by the input capacitors. Therefore, there are two
requirements for capacitors in a flyback regulator: energy
storage and filtering. To maintain a stable voltage supply to
the chip, a storage capacitor larger than 20 mF with low ESR
is required. To reduce the noise generated by the inductor,
insert a 1.0 mF ceramic capacitor between VCC and ground
as close as possible to the chip.
Output Capacitor Selection
Figure 36. Typical Output Voltage Ripple
VOUT ripple
IL
By examining the waveforms shown in Figure 36, we can
see that the output voltage ripple comes from two major
sources, namely capacitor ESR and the
charging/discharging of the output capacitor. In boost
circuits, when the power switch turns off, IL flows into the
output capacitor causing an instant DV = IIN × ESR. At the
same time, current IL I
OUT charges the capacitor and
increases the output voltage gradually. When the power
switch is turned on, IL is shunted to ground and IOUT
discharges the output capacitor. When the IL ripple is small
enough, IL can be treated as a constant and is equal to input
current IIN.
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14
Summing up, the output voltage peakpeak ripple can be
calculated by:
VOUT(RIPPLE) +(IIN *IOUT)(1 *D)
(COUT)(f)
)IOUTD
(COUT)(f) )IIN ESR
The equation can be expressed more conveniently in
terms of VCC, VOUT and IOUT for design purposes as
follows:
VOUT(RIPPLE) +IOUT(VOUT *VCC)
(COUT)(f) 1
(COUT)(f)
)(IOUT)(VOUT)(ESR)
VCC
The capacitor RMS ripple current is:
IRIPPLE +(IIN *IOUT)2(1 *D))(IOUT)2(D)
Ǹ
+IOUT VOUT *VCC
VCC
Ǹ
Although the above equations apply only for boost
circuits, similar equations can be derived for flyback
circuits.
Reducing the Current Limit
In some applications, the designer may prefer a lower
limit on the switch current than 1.5 A. An external shunt can
be connected between the VC pin and ground to reduce its
clamp voltage. Consequently, the current limit of the
internal power transistor current is reduced from its nominal
value.
The voltage on the VC pin can be evaluated with the
equation
VC+ISWREAV
where:
RE = .063W, the value of the internal emitter resistor;
AV = 5 V/V, the gain of the current sense amplifier.
Since RE and AV cannot be changed by the end user, the
only available method for limiting switch current below
1.5 A is to clamp the VC pin at a lower voltage. If the
maximum switch or inductor current is substituted into the
equation above, the desired clamp voltage will result.
A simple diode clamp, as shown in Figure 37, clamps the
VC voltage to a diode drop above the voltage on resistor R3.
Unfortunately, such a simple circuit is not generally
acceptable if VIN is loosely regulated.
Figure 37. Current Limiting using a Diode Clamp
VC
D1
VCC
R1
VIN
C2
C1
R2
R3
Another solution to the current limiting problem is to
externally measure the current through the switch using a
sense resistor. Such a circuit is illustrated in Figure 38.
+
Figure 38. Current Limiting using a Current Sense
Resistor
VC
RSENSE
Q1
VCC
R1
VIN
C2
C1
R2
C3 Output
Ground
PGND AGND
The switch current is limited to
ISWITCH(PEAK) +VBE(Q1)
RSENSE
where:
VBE(Q1) = the baseemitter voltage drop of Q1, typically
0.65 V.
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15
The improved circuit does not require a regulated voltage
to operate properly. Unfortunately, a price must be paid for
this convenience in the overall efficiency of the circuit. The
designer should note that the input and output grounds are
no longer common. Also, the addition of the current sense
resistor, RSENSE, results in a considerable power loss which
increases with the duty cycle. Resistor R2 and capacitor C3
form a lowpass filter to remove noise.
Subharmonic Oscillation
Subharmonic oscillation (SHM) is a problem found in
currentmode control systems, where instability results
when duty cycle exceeds 50%. SHM only occurs in
switching regulators with a continuous inductor current.
This instability is not harmful to the converter and usually
does not affect the output voltage regulation. SHM will
increase the radiated EM noise from the converter and can
cause, under certain circumstances, the inductor to emit
highfrequency audible noise.
SHM is an easily remedied problem. The rising slope of
the inductor current is supplemented with internal “slope
compensation” to prevent any duty cycle instability from
carrying through to the next switching cycle. In the CS517x
family, slope compensation is added during the entire switch
ontime, typically in the amount of 180 mA/ms.
In some cases, SHM can rear its ugly head despite the
presence of the onboard slope compensation. The simple
cure to this problem is more slope compensation to avoid the
unwanted oscillation. In that case, an external circuit, shown
in Figure 39, can be added to increase the amount of slope
compensation used. This circuit requires only a few
components and is “tacked on” to the compensation
network.
Figure 39. Technique for Increasing Slope
Compensation
VC
R1
C2
C1
R2
R3
VSW
C3
VSW
The dashed box contains the normal compensation
circuitry to limit the bandwidth of the error amplifier.
Resistors R2 and R3 form a voltage divider off of the VSW
pin. In normal operation, VSW looks similar to a square
wave, and is dependent on the converter topology. Formulas
for calculating VSW in the boost and flyback topologies are
given in the section “VSW Voltage Limit.” The voltage on
VSW charges capacitor C3 when the switch is off, causing
the voltage at the VC pin to shift upwards. When the switch
turns on, C3 discharges through R3, producing a negative
slope at the VC pin. This negative slope provides the slope
compensation.
The amount of slope compensation added by this circuit
is
DI
DT+VSW ǒR3
R2)R3Ǔǒ1*e
*(1*D)
R3C3fSWǓǒ fSW
(1 *D)REAVǓ
where:
DI/DT = the amount of slope compensation added (A/s);
VSW = the voltage at the switch node when the transistor
is turned off (V);
fSW = the switching frequency, typically 280 kHz
(CS5171/3) or 560 kHz (CS5172/4) (Hz);
D = the duty cycle;
RE = 0.063 W, the value of the internal emitter resistor;
AV = 5 V/V, the gain of the current sense amplifier.
In selecting appropriate values for the slope compensation
network, the designer is advised to choose a convenient
capacitor, then select values for R2 and R3 such that the
amount of slope compensation added is 100 mA/ms. Then
R2 may be increased or decreased as necessary. Of course,
the series combination of R2 and R3 should be large enough
to avoid drawing excessive current from VSW. Additionally,
to ensure that the control loop stability is improved, the time
constant formed by the additional components should be
chosen such that
R3C3t1*D
fSW
Finally, it is worth mentioning that the added slope
compensation is a tradeoff between duty cycle stability and
transient response. The more slope compensation a designer
adds, the slower the transient response will be, due to the
external circuitry interfering with the proper operation of the
error amplifier.
SoftStart
Through the addition of an external circuit, a SoftStart
function can be added to the CS5171/2/3/4 family of
components. SoftStart circuitry prevents the VC pin from
slamming high during startup, thereby inhibiting the
inductor current from rising at a high slope.
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16
This circuit, shown in Figure 40, requires a minimum
number of components and allows the SoftStart circuitry to
activate any time the SS pin is used to restart the converter.
Figure 40. Soft Start
VC
R1
C2
C1
D2
D1
VCC
C3
V
IN
SS
SS
Resistor R1 and capacitors C1 and C2 form the
compensation network. At turn on, the voltage at the VC pin
starts to come up, charging capacitor C3 through Schottky
diode D2, clamping the voltage at the VC pin such that
switching begins when VC reaches the VC threshold,
typically 1.05 V (refer to graphs for detail over temperature).
VC+VF(D2))VC3
Therefore, C3 slows the startup of the circuit by limiting
the voltage on the VC pin. The SoftStart time increases with
the size of C3.
Diode D1 discharges C3 when SS is low. If the shutdown
function is not used with this part, the cathode of D1 should
be connected to VIN.
Calculating Junction Temperature
To ensure safe operation of the CS5171/2/3/4, the
designer must calculate the onchip power dissipation and
determine its expected junction temperature. Internal
thermal protection circuitry will turn the part off once the
junction temperature exceeds 180°C ±30°. However,
repeated operation at such high temperatures will ensure a
reduced operating life.
Calculation of the junction temperature is an imprecise
but simple task. First, the power losses must be quantified.
There are three major sources of power loss on the CS517x:
biasing of internal control circuitry, PBIAS
switch driver, PDRIVER
switch saturation, PSAT
The internal control circuitry, including the oscillator and
linear regulator, requires a small amount of power even
when the switch is turned off. The specifications section of
this datasheet reveals that the typical operating current, IQ,
due to this circuitry is 5.5 mA. Additional guidance can be
found in the graph of operating current vs. temperature. This
graph shows that IQ is strongly dependent on input voltage,
VIN, and temperature. Then
PBIAS +VINIQ
Since the onboard switch is an NPN transistor, the base
drive current must be factored in as well. This current is
drawn from the VIN pin, in addition to the control circuitry
current. The base drive current is listed in the specifications
as DICC/DISW, or switch transconductance. As before, the
designer will find additional guidance in the graphs. With
that information, the designer can calculate
PDRIVER +VINISW ICC
DISW D
where:
ISW = the current through the switch;
D = the duty cycle or percentage of switch ontime.
ISW and D are dependent on the type of converter. In a
boost converter,
ISW(AVG) ^IL(AVG) D 1
Efficiency
D^VOUT *VIN
VOUT
In a flyback converter,
ISW(AVG) ^VOUTILOAD
VIN 1
Efficiency 1
D
D^VOUT
VOUT )NS
NPVIN
The switch saturation voltage, V(CE)SAT, is the last major
source of onchip power loss. V(CE)SAT is the
collectoremitter voltage of the internal NPN transistor
when it is driven into saturation by its base drive current. The
value for V(CE)SAT can be obtained from the specifications
or from the graphs, as “Switch Saturation Voltage.” Thus,
PSAT ^V(CE)SATISW D
Finally, the total onchip power losses are
PD+PBIAS)PDRIVER)PSAT
Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
gradient is expressed in manufacturers’ data sheets as qJA,
or junctiontoambient thermal resistance. The onchip
junction temperature can be calculated if qJA, the air
temperature near the surface of the IC, and the onchip
power dissipation are known.
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17
TJ+TA)(PDqJA)
where:
TJ = IC or FET junction temperature (°C);
TA = ambient temperature (°C);
PD = power dissipated by part in question (W);
qJA = junctiontoambient thermal resistance (°C/W).
For the CS517x, qJA=165°C/W.
Once the designer has calculated TJ, the question of
whether the CS517x can be used in an application is settled.
If TJ exceeds 150°C, the absolute maximum allowable
junction temperature, the CS517x is not suitable for that
application.
If TJ approaches 150°C, the designer should consider
possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
surface of the chip might be considered to reduce TA.
Circuit Layout Guidelines
In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage
transitions that can cause problems. Therefore the following
guidelines should be followed in the layout.
1. In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
onchip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
onchip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.
2. Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.
3. Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.
+
+
+
CS5172/4
C2
D2
C3
D1
C4
R2
1
2
3
45
6
7
8
22 mF
22 mF
VOUT
12 VVC
Test
NFB
SS
0.01 mF
C1
VSW
VCC
AGND
PGND
VCC
SS
5.0 V
5.0 k
R1 R3
1.27 k
4.87 k
MBRS120T3
MBRS120T3
22 mF
22 mH
L1
Figure 41. Additional Application Diagram, 5.0 V to 12 V/ 75 mA Inverting Converter
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18
CS5171/3
3.3 VIN
VC (1 ) FB (2)
0.1 mF
VCC (5)
AGND (6)
PGND (7) VSW (8)
200 pF
MBRS120T3
22 mF
22 mH
Figure 42. Additional Application Diagram, 3.3 V Input, 5.0 V/ 400 mA Output Boost Converter
10 mF
GND
5.0 k
3.6 k
GND
5.0 VO
1.3 k
+
+
+
CS5171/3
+12 V
VC (1 ) FB (2)
VCC (5)
AGND (6)
PGND (7) VSW (8)
MBRS140T3
22 mF
47 mF
Figure 43. Additional Application Diagram, 2.7 to 13 V Input, +12 V/ 200 mA Output Flyback Converter
1.0 mF
GND
2.0 k
10.72 k
GND
1.28 k
47 mF
47 nF
4.7 nF
VCC 12 V
T1
1:2
P6KE15A
1N4148
MBRS140T3
CS5171/3
VC (1 )
FB (2)
VCC (5)
AGND (6)
PGND (7)
VSW (8)
2.2 mF
Figure 44. Additional Application Diagram, 9.0 V to 28 V Input, 5.0 V/700 mA Output Inverted Buck Converter
15 mH
GND
300
GND
5.0 k
.01 mF
200 pF
VIN
5.0
VOUT
1.1 k
22 mF
Low
ESR
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19
CS5171/3
+
+
VC (1 )
FB (2)
VCC (5)
AGND (6)
PGND (7)
VSW (8)
22 mF
Figure 45. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter
GND
12.76 k
GND
5.0 k
.01 mF
200 pF
VCC
22 mH
Low
ESR
22 mF
22 mH22 mF37.24 k
5.0 V
CS5171/3
VC
FB
AGND
PGND
VSW
Figure 46. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with
Output Voltage Multiplier
GND
GND
.01 m
VCC
4.0 V
Test
SS
1
2
3
4
8
7
6
5
C11
R1 R2
R3
C10
.1 m
C8 C9
C1 C2 C3
C4 C5 C6
C7
.1 m
.1 m.1 m.1 m
50 V
50 V 50 V 50 V
.1 m
50 V
.1 m
50 V
.1 m
50 V
D1 D1 D1 D1 D1 D1 D1
1N41481N41481N41481N41481N41481N41481N4148
99.755 k/0.1 W, 1%1.245 k/0.1 W, 1%
2.0 k
.1 m
10 m
100 VO
+
+
+
CS5171
VC
FB
VCC
AGND
PGND
VSW
Figure 47. Additional Application Diagram, 5.0 V Input, ± 12 V Output Dual Boost Converter
GND GND
0.01 mF
200 pF
22 mF
15 mH
22 mF
1.28 k
5.0 k
SS
Test
1
2
3
45
6
7
8
+5.0 V
SS
C6 C1
R1
R2 R3
10.72 k
C5
22 mF
C3
D3
D2
L1
D1
12 V
+12 V
C4
0.1 mF
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20
ORDERING INFORMATION
Device
Operating
Temperature Range Package Shipping
CS5171ED8
40°C < TJ < 125°C
SOIC898 Units/Rail
CS5171ED8G SOIC8
(PbFree)
98 Units/Rail
CS5171EDR8 SOIC82500 Tape & Reel
CS5171EDR8G SOIC8
(PbFree)
2500 Tape & Reel
CS5172ED8 SOIC898 Units/Rail
CS5172ED8G SOIC8
(PbFree)
98 Units/Rail
CS5172EDR8 SOIC82500 Tape & Reel
CS5172EDR8G SOIC8
(PbFree)
2500 Tape & Reel
CS5173ED8 SOIC898 Units/Rail
CS5173ED8G SOIC8
(PbFree)
98 Units/Rail
CS5173EDR8 SOIC82500 Tape & Reel
CS5173EDR8G SOIC8
(PbFree)
2500 Tape & Reel
CS5174ED8 SOIC898 Units/Rail
CS5174ED8G SOIC8
(PbFree)
98 Units/Rail
CS5174EDR8 SOIC82500 Tape & Reel
CS5174EDR8G SOIC8
(PbFree)
2500 Tape & Reel
CS5171GD8
0°C < TJ < 125°C
SOIC898 Units/Rail
CS5171GD8G SOIC8
(PbFree)
98 Units/Rail
CS5171GDR8 SOIC82500 Tape & Reel
CS5171GDR8G SOIC8
(PbFree)
2500 Tape & Reel
CS5172GD8 SOIC898 Units/Rail
CS5172GD8G SOIC8
(PbFree)
98 Units/Rail
CS5172GDR8 SOIC82500 Tape & Reel
CS5172GDR8G SOIC8
(PbFree)
2500 Tape & Reel
CS5173GD8 SOIC898 Units/Rail
CS5173GD8G SOIC8
(PbFree)
98 Units/Rail
CS5173GDR8 SOIC82500 Tape & Reel
CS5173GDR8G SOIC8
(PbFree)
2500 Tape & Reel
CS5174GD8 SOIC898 Units/Rail
CS5174GD8G SOIC8
(PbFree)
98 Units/Rail
CS5174GDR8 SOIC82500 Tape & Reel
CS5174GDR8G SOIC8
(PbFree)
2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
CS5171, CS5172, CS5173, CS5174
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21
PACKAGE DIMENSIONS
SOIC8 NB
CASE 75107
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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