Product Folder Order Now Technical Documents Support & Community Tools & Software UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 UCC2863x, High-Power Flyback Controller with Primary-Side Regulation and Peak-Power Mode 1 Features 3 Description * * The UCC2863x targets high-power, primary-side regulated flyback converters. The ability to operate in both CCM and DCM make the device suitable for applications with a wide power range. The peak power mode allows transient peak power delivery up to 200% of nominal rating, with only a 25% peak current increase, maximizing transformer utilization. 1 * * * * * * * * * * * * * High-Power, Primary-Side CV/CC Regulation Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) Operation Built-In 700-V Start-Up Current Source Active X-Capacitor Discharge (UCC28630 and UCC28633) Adjustable Constant-Current (CC) Mode Limiting (except for UCC28630) High Gate Drive Current 1-A Source and 2-A Sink Low Power Modes for <30-mW System Standby Best-In-Class Light Load (10%) Efficiency >85% PSR design with no opto-coupler - can meet high CM isolation & surge requirements VDD OVP for independent indirect output OV under open-feedback fault conditions Peak-Power Mode for Transient Overload Shutdown Pin Interface for External NTC Protections: Overvoltage, Overcurrent, OverTemperature, Overload Timer (UCC28630), AC Line UV, Brownout and Pin Protections Frequency Dither to Ease EMI Compliance (except the UCC28632) Create a Custom Design Using the UCC2863x With the WEBENCH(R) Power Designer The transformer bias winding is used to sense output voltage for regulation, and for low-loss input voltage sensing. Advanced sampling techniques allow CCM operation, and deliver excellent output voltage regulation performance for opto-coupler-less designs at power levels of 100 W and above. A high-voltage current source enables fast and efficient start-up. Advanced light-load modes are deployed to reduce both controller and system power consumption at no load and light load. These modes enable potential system designs to meet 30-mW noload power for power designs up to 30 W nominal, 60 W peak. The device has been designed for ease-of-use and incorporates many features to enable a wide range of designs. Extensive protection features are included to simplify system design. See the Device Comparison Table for details. Device Information PART NUMBER 2 Applications UCC28630 * UCC28631 * * AC-DC Adapters for Notebook, Game Consoles, Printers Open Frame SMPS for Industrial, Printer, White Goods, LCD Monitors Energy Efficient AC-DC Supplies for Nominal Power 10-W to 65-W, (with up to 200% transient peak power) Simplified Schematic UCC28632 PACKAGE BODY SIZE SOIC (7) 4.90 mm x 3.90 mm UCC28633 UCC28634 (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Measured Regulation 21 VOUT VAC 20.5 Output Voltage (V) EMC Filter 20 19.5 19 +5% Limit 115V/60 Hz 230V/50 Hz " 1% Typical 18.5 1 VSENSE HV 8 3 CS 5% Limit 18 2 SD to UCC28630 VDD 6 4 GND 0 10 20 30 40 50 Output Power (W) 60 70 C001 DRV 5 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 3 5 5 6 7.1 7.2 7.3 7.4 7.5 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information (UCC28630, UCC28631)......... 7 Thermal Information (UCC28632, UCC28633, (UCC28630, UCC28634) ........................................... 7 7.6 Electrical Characteristics........................................... 8 7.7 Typical Characteristics ............................................ 10 8 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 14 8.3 Feature Description................................................. 15 2 Submit Documentation Feedback 8.4 Device Functional Modes........................................ 52 9 Applications and Implementation ...................... 53 9.1 Application Information............................................ 53 9.2 Typical Application ................................................. 53 9.3 Dos and Don'ts........................................................ 73 10 Power Supply Recommendations ..................... 73 11 Layout................................................................... 74 11.1 Layout Guidelines ................................................. 74 11.2 Layout Example .................................................... 75 12 Device and Documentation Support ................. 76 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 76 76 76 76 77 77 77 13 Mechanical, Packaging, and Orderable Information ........................................................... 77 Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 4 Revision History Changes from Revision C (March 2015) to Revision D Page * Added UCC28634 initial release. .......................................................................................................................................... 1 * Deleted text "for 65-W Nominal Power Design" ..................................................................................................................... 1 * Added text "PSR design with no opto-coupler - can meet high CM isolation & surge requirements".................................... 1 * Added text "VDD OVP for independent indirect output OV under open-feedback fault conditions" ..................................... 1 * Added Webench links............................................................................................................................................................. 1 * Added Device Comparison Table details. .............................................................................................................................. 1 * Added UCC28634 to the Device Information Table. ............................................................................................................. 1 * Added UCC28634 to the Device Comparison Table.............................................................................................................. 5 * Added UCC28634 to Thermal Information ............................................................................................................................ 7 * Added UCC28634 to Electrical Characteristics ...................................................................................................................... 8 * Added UCC28634 to Electrical Characteristics ...................................................................................................................... 8 * Changed picture to represent added UCC28634 ................................................................................................................ 10 * Added UCC28634 ............................................................................................................................................................... 13 * Added UCC28634 ............................................................................................................................................................... 15 * Added UCC28634 ............................................................................................................................................................... 16 * Changed to correct picture link ............................................................................................................................................ 19 * Changed to fix equation typo ............................................................................................................................................... 21 * Added UCC28634 ............................................................................................................................................................... 41 * Changed to correct typo ...................................................................................................................................................... 41 * Changed to correct typo, changed from 4.7 to 47 ............................................................................................................... 41 * Added paragraph to clarify the fault protection. .................................................................................................................. 41 * Added UCC28634 ............................................................................................................................................................... 42 * Added text "For UCC28634, all pin-faults are non-latching." .............................................................................................. 43 * Added UCC28634 to the table ............................................................................................................................................ 52 * Changed equation to fix typo ............................................................................................................................................... 67 Changes from Revision B (March 2014) to Revision C Page * Changed "No" to "Yes" in Device Comparison Table for Part# UCC28633D, "ACTIVE-X CAPACITOR DISCHARGE" column .................................................................................................................................................................................... 5 * Changed "Handling Ratings" table to "ESD Ratings" table. Moved Storage Temperature and Lead Temperature to Abs Max Ratings table. .......................................................................................................................................................... 6 * Revised Figure 40 ............................................................................................................................................................... 47 Changes from Revision A (January 2014) to Revision B Page * Added parts UCC28631, UCC28632 and UCC28633 to the datasheet. ............................................................................... 1 * Added Active X-Capacitor Discharge Function reference to the UCC28630 and UCC28633. ............................................. 1 * Added Adjustable Constant-Current (CC) Mode Limiting bullet. ............................................................................................ 1 * Added Overload Timer reference to the UCC28630 only....................................................................................................... 1 * Added Frequency Dither to Ease EMI Compliance exception for the UCC28632. ................................................................ 1 * Added UCC28631D, UCC28632D and UCC28633D to the Device Information Section....................................................... 1 * Added Device Comparison Table........................................................................................................................................... 5 * Added UCC28632 Frequency dither range exception. .......................................................................................................... 8 * Added UCC28632 Dither repetition period exception. ........................................................................................................... 8 Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 3 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com * Added UCC28633 Wake-up level (rising) exception. ............................................................................................................. 8 * Added UCC28633 SD VWAKE(rise) vs. Temperature exception............................................................................................... 12 * Added text to the, "The controller operates in either DCM and CCM..." paragraph. .......................................................... 13 * Changed the "Supply the device bias power during latched fault mode" bullet. .................................................................. 15 * Added UCC28630 and UCC28633 only exception to the "AC sense input for X-capacitor discharge detect" bullet. ......... 15 * Changed HV Pin Connection diagram. ............................................................................................................................... 15 * Added sentence, "In the UCC28631 and the UCC28632, the HV pin can connect to either the AC or DC side of the bridge.".................................................................................................................................................................................. 16 * Added VIN(avg) definition. ................................................................................................................................................... 16 * Added (UCC28630 and UCC28633 only) to the Active X-Capacitor Discharge section...................................................... 19 * Added UCC28633 to the Improved Performance with UCC28630 section.......................................................................... 20 * Added UCC28631, UCC28632 and the UCC28633 IOUT(lim) adjustment note. .................................................................... 37 * Added UCC28630 only note to the Primary-Side Overload Timer section. ......................................................................... 38 * Added UCC28630 only note added to the Overload Timer Adjustment section. ................................................................ 40 * Added CC-Mode IOUT(lim) Adjustment section. ...................................................................................................................... 41 * Added UCC28631, UCC28632 and the UCC28633 to the Fault Sources and Associated Responses table. .................... 42 * Added The fault response (latching or auto recovery) depends on the device variant, per Table 3. ................................. 44 * Added The fault response (latching or recovery) depends on the device variant, per Table 3. ......................................... 44 * Added UCC28633 exception to the External SD Pin Wake Input section. .......................................................................... 45 * Added External Wake Input at VSENSE Pin (UCC28633 Only) section.............................................................................. 46 * Added UCC28632 exception to the Frequency Dither For EMI section............................................................................... 51 * Added External Wake Pulse Calculation at VSENSE Pin (UCC28633 Only) section.......................................................... 66 Changes from Original (January 2014) to Revision A * 4 Page Changed marketing status from Product Preview to Production Data. .................................................................................. 1 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 5 Device Comparison Table FEATURES ACTIVE-X CAPACITOR DISCHARGE OVERLOAD TIMER UCC28630D Yes UCC28631D No UCC28632D ORDER NUMBER ADJUSTABLE CC LIMIT FREQUENCY DITHER SECONDARYSIDE WAKE UP Yes No Yes SD Pin No Yes Yes SD Pin No No Yes No SD Pin UCC28633D Yes No Yes Yes VSENSE Pin UCC28634D No No Yes Yes SD Pin 6 Pin Configuration and Functions 7-Pin SOIC Package D (Top View) VSENSE 1 8 HV SD 2 CS 3 6 VDD GND 4 5 DRV PIN Functions PIN NAME NO. I/O DESCRIPTION CS 3 I Current sense input DRV 5 O Output drive pin for the external flyback MOSFET GND 4 G Ground reference connection for all signals HV 8 P High-voltage connection to the internal high-voltage start-up current source SD 2 I Latching fault shutdown input pin. May be connected to an external temperature sensor VDD 6 P Bias supply input pin to the device. Decoupled with a 1-F ceramic bypass capacitor, connect directly across pins 6-4. Connect an additional hold-up capacitor charged from the transformer auxiliary bias winding to this pin. VSENSE 1 I Sense pin for the flyback transformer bias and sense winding for output feedback regulation, output OVP, and input voltage sense/UV protection Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 5 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating junction temperature range (unless otherwise noted) MIN MAX Start-up pin voltage HV 700 Bias supply voltage VDD 20 Current sense input voltage CS -0.3 1.5 VSENSE -0.3 VDD SD -0.3 VDD Operating junction temperature range, TJ -40 125 Storage temperature, Tstg -65 125 All other input pins Lead temperature (1) UNIT V C 260 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. All voltages are with respect to GND. These ratings apply over the junction operating temperature ranges unless otherwise noted. 7.2 ESD Ratings VALUE Electrostatic discharge (1) V(ESD) (1) (2) (3) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (3) 500 UNIT V Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as 500 V may actually have higher performance. 7.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM MAX CS input 0 1.0 All other inputs (except HV, CS) 0 VDD SD pin external capacitance 0 1 RHV, external resistor on HV pin, see Figure 15 180 200 220 RP, external pull-up resistor on VSENSE pin, see Figure 21 3.8 3.9 4.0 6 Submit Documentation Feedback UNIT V nF k Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 7.4 Thermal Information (UCC28630, UCC28631) UCC28630 THERMAL METRIC (1) UCC28631 D D 7 PINS 7 PINS UNIT JA Junction-to-ambient thermal resistance 128.5 128.5 JCtop Junction-to-case (top) thermal resistance 57.3 57.3 JB Junction-to-board thermal resistance 83.4 83.4 JT Junction-to-top characterization parameter 12.3 12.3 JB Junction-to-board characterization parameter 82.1 82.1 (1) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Thermal Information (UCC28632, UCC28633, (UCC28630, UCC28634) THERMAL METRIC (1) UCC28632 UCC28633 D D UCC28634 D 7 PINS 7 PINS 7 PINS JA Junction-to-ambient thermal resistance 128.5 128.5 128.5 JCtop Junction-to-case (top) thermal resistance 57.3 57.3 57.3 JB Junction-to-board thermal resistance 83.4 83.4 83.4 JT Junction-to-top characterization parameter 12.3 12.3 12.3 JB Junction-to-board characterization parameter 82.1 82.1 82.1 (1) UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 7 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 7.6 Electrical Characteristics over operating junction temperature range (unless otherwise noted) and VDD = 12 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT START-UP CURRENT SOURCE IVDD0 VDD pin short-circuit charging current VDD = 0.2 V, VHV = 100 V 0.6 0.9 1.2 mA IVDD1 VDD pin final charging current VDD = 11.9 V, VHV = 100 V 1.1 4.0 7.6 mA ILEAK HV current source leakage current VDD = 18 V, VHV = 100 V HV, current source off, TA = 25C 0.1 0.5 A 13.00 14.75 16.50 V 7.3 8.0 8.5 V SUPPLY VOLTAGE MONITORING VDD(start) VDD start-up voltage VDD increasing VDD(stop) VDD minimum operating voltage after start-up VDD decreasing after start-up VDD(hyst) VDD start - VDD stop level VDD(reset) VDD reset restart level VDD(ovp) VDD over-voltage protection level 6.5 V 3.5 5.0 6.5 V VDD increasing after start-up, UCC28630, UCC28631, UCC28632, UCC28633 16.5 17.5 18.3 V VDD increasing after start-up, UCC28634 only 14.0 14.85 15.55 V 6.0 9.0 13.0 mA 90 110 A (1) IDD(run) Supply current during normal operation VSENSE = 0.45 V, CS = 0 V See CLOAD = 700 pF on DRV IDD(sleep) Supply current during sleep mode, between switching pulses VSENSE = 8.0 V, VCS = 1.0 V, lightload mode at 200 Hz, TA = 25C OSCILLATOR fSW(max) Maximum switching frequency VSENSE = 0.45 V, VCS = 0 V 110 120 130 kHz fSW(min) Minimum switching frequency VSENSE = 8.0 V, VCS = 1.0 V, lightload mode 0.18 0.20 0.22 kHz DMAX Maximum Duty Cycle VSENSE = 0.45 V, VCS = 0 V tON(min) Minimum On time VSENSE = 8.0 V, VCS = 1.0 V, lightload mode 650 ns fSW(dith) Frequency dither range Except UCC28632 6.7% tDITH Dither repetition period Except UCC28632 6.0 70% 550 600 ms SHUTDOWN (SD) PIN (EXTERNAL FAULT INPUT) (2) IPULLUP Internal pull-up current source See (2) (3) (4) , , 185 210 235 A 3.2 3.5 3.8 V 2.2 2.5 2.8 V 1.7 2.00 2.3 V (2) (3) (4) VTRIP(rise) VTRIP(fall) Fault ok level (rising) Fault trip level (falling) See , , , UCC28630, UCC28631, UCC28632,UCC28633 See (2) (3) (4) See (2) (3) (4) , , , , UCC28634 only , See (2) (3) (4) VWAKE(rise) Wake-up level (rising) See (2) (3) (4) tWAKE Wake delay time Delay to first DRV pulse VTRIP(hyst) (1) (2) (3) (4) 8 , , , , Except UCC28633 1.5 1.8 2.2 10 V 2.6 V s CLOAD = 700 pF included on DRV pin. The SD pin functions as an NTC input pin (with internal pull-up) during normal operation. The internal pull-up is clamped to 4 V. At startup, the external temperature sensor (NTC) must be cool enough that the SD pin pulls up above the VTRIP(rise) start level. After start-up, if this pin is pulled below VTRIP(fall) level, this activates external over-temperature shut-down. During low power modes (when FSW < FSMP(max)), the internal SD pin pull-up is disabled, and the pin functions as a transient wake-up input. In this case, if the pin is raised above VWAKE(rise) level, the device wakes from low power sleep mode (rather than waiting for the scheduled timer-based wake). This is useful for applications that require a response to load transients from zero or near-zero load, where a wake-up signal can be appropriately coupled to the SD pin from the secondary-side. A decoupling capacitor on the SD pin should not be required; if used, it must not exceed 1 nF. Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Electrical Characteristics (continued) over operating junction temperature range (unless otherwise noted) and VDD = 12 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 7.425 7.500 7.575 V VSENSE Pin (MAGNETIC SENSE) VOUT(ref) Internal output voltage sense reference level Required positive voltage at VSENSE pin during off-time (at 25C) tOUT(smp) Vsense sample delay for VOUT Measured w.r.t. DRV falling edge VOUT(ovp) Internal output voltage sense OVP level Measured w.r.t. regulation level, tracking 120% 1.7 s CURRENT SENSE (CS) Pin VCS(max) Peak CS pin voltage level At maximum modulator demand 800 VCS(min) Peak CS pin voltage level At minimum modulator demand 172 mV mV VSLOPE Slope compensation ramp 30 mV/s OVER TEMPERATURE PROTECTION TEMPTRIP Thermal protection shutdown temperature Default internal setting, latch-off protection 125 TEMPHYST Thermal protection hysteresis 10 C C GATE DRIVE OUTPUT (DRV) ROH High level source resistance IOH = 100 mA 22 35 ROL Low level sink resistance IOL = -100 mA 1.2 2.5 Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 9 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 1 4 0.995 3.9 0.99 3.8 0.985 3.7 Current (mA) Current (mA) 7.7 Typical Characteristics 0.98 0.975 0.97 3.6 3.5 3.4 0.965 3.3 0.96 3.2 0.955 3.1 0.95 3 50 0 50 100 Temperature (C) 150 0 50 50 100 Temperature (C) C002 Figure 1. IVDD0 Charging Current vs. Temperature 150 C003 Figure 2. IVDD1 Charging Current vs. Temperature 14.9 12 11.5 14.85 11 14.8 Voltage (V) Current (mA) 10.5 10 9.5 9 14.75 14.7 8.5 8 14.65 7.5 7 14.6 50 0 50 100 Temperature (C) 150 Figure 3. IDD(run) Current vs. Temperature 100 150 C005 Figure 4. VDD(start) Threshold vs. Temperature 1.036 8.15 Normalized VDD(ovp) Thresholds 1.03 8.1 8.05 Voltage (V) 50 Temperature (C) 8.2 8 7.95 7.9 7.85 7.8 7.75 1.024 1.018 1.012 1.006 1 0.994 0.988 0.982 0.976 7.7 50 0 50 100 Temperature (C) Figure 5. VDD(stop) Threshold vs. Temperature 10 0 50 C004 Submit Documentation Feedback 150 C006 0.97 -50 0 50 Temperature (oC) 100 150 D001 Figure 6. Normalized VDD(ovp) Threshold vs. Temperature Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 5 7.6 4.95 7.58 4.9 7.56 4.85 7.54 Voltage (V) Voltage (V) Typical Characteristics (continued) 4.8 4.75 4.7 7.52 7.5 7.48 4.65 7.46 4.6 7.44 4.55 7.42 4.5 7.4 50 0 50 100 Temperature (C) 150 50 0 50 100 Temperature (C) C008 Figure 7. VDD(reset) Threshold vs. Temperature 150 C009 Figure 8. VOUT(ref) vs. Temperature 122 205 204 121 Frequency (Hz) Frequency (kHz) 203 120 119 118 117 202 201 200 199 198 197 116 196 115 195 50 0 50 100 Temperature (C) 150 50 50 100 Temperature (C) Figure 9. FSW(max) vs. Temperature 150 C011 Figure 10. FSW(min) vs. Temperature 1.02 212 1.015 211 1.01 Current ( A) DRV Measure Gain (Normalized) (dB) 0 C010 1.005 1 0.995 0.99 210 209 208 0.985 0.98 207 50 0 50 Temperature (C) 100 150 C012 Figure 11. DRV Programming Current Measure vs. Temperature Copyright (c) 2014-2017, Texas Instruments Incorporated 50 0 50 100 Temperature (C) 150 C013 Figure 12. SD Pull-Up vs. Temperature Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 11 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Typical Characteristics (continued) 2.04 2.25 2.02 2.23 Voltage (V) Voltage (V) 2 1.98 1.96 2.21 2.19 1.94 2.17 1.92 1.9 2.15 50 0 50 100 Temperature (C) Figure 13. SD VTRIP(fall) vs. Temperature 12 Submit Documentation Feedback 150 C014 50 0 50 100 Temperature (C) 150 C015 Figure 14. SD VWAKE(rise) vs. Temperature (except UCC28633) Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 8 Detailed Description 8.1 Overview The UCC28630, UCC28631, UCC28633, UCC28633 and UCC28634 family of devices are highly-integrated, primary-side-regulated (PSR) flyback controllers. The device supports magnetically-sensed output voltage regulation via the transformer bias winding. This feature eliminates the need for a secondary-side reference, error amplifier and opto-isolator. The device employs an advanced internal control algorithm that offers accurate static output voltage regulation against line and load. The fixed-point, magnetic-sampling scheme allows operation in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Additionally, the device achieves accurate constant-current (CC) control of the output current limit using only primary-side, current sensing. Uniquely, this CC function operates seamlessly as the operating mode changes between DCM and CCM operation. The controller includes an internal, high-voltage (HV) start-up current-source, and employs low-power sleep modes and switching frequency reduction, to improve light-load efficiency and standby power. The device typically achieves standby power levels between 0.05% and 0.1% of peak output power. The controller operates in either DCM and CCM, using a mix of peak current-mode PWM (AM) and switchingfrequency modulation (FM) schemes. The control approach improves performance (efficiency, size and cost) and can reduce transformer size and cost by allowing operation in CCM with FM during peak overload conditions. Extensive protection features are incorporated, including output overvoltage protection (OVP), bias rail overvoltage and undervoltage (OV/UV), active X-capacitor discharge, line undervoltage and brownout protection, overcurrent overload timer, open- and short-circuit pin protections, peak current adjustment with line and frequency dither for system EMI reduction. The various devices in the UCC2863x family offer a different mix of features to suit a wide range of applications and requirements. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 13 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 8.2 Functional Block Diagram + VREF x 120% OVP Fault tSMP1 + VREF VO Voltage Loop Compensation VO Sample VSENSE tSW PLIM VIN Sample VIN + Current Loop Compensation PIN Compute PIN=(VIN x ISW(MID))x(tON/tSW) FM + AM Modulator Min Demand ILIM x VO tSMP2 1 CV Demand Sleep Timer 8 HV 6 VDD 5 DRV IPK(dem) CC Demand PIN OCP Fault ISW(mid) VAC(min) SD + SD Fault tSMP3 3 VO Overload Timer Fault Filtering and Status Monitor Start-Up and Bias Control VVDD(ov) + VDD + VDD UV Fault + Over-Temp Fault tSMP,n tON(min) tON(max) IDD(LIMIT) and IHV(MEAS) JFET Control X-Cap Discharge Detect IHV(meas) PWM Enable tSW S 4 + IPK(dem) / VVDD(uv) VTRIP(TEMP) 14 PWM Enable VDD OV Fault X-Cap Fault n JFET Control tSMP4 Isw Sample Internal Temp Sensor GND Timing and Trigger Generation tSW tON Line UV Fault SD Fault OVP Fault OCP Fault VDD OV Fault VDD UV Fault Over-Temp Fault X-Cap Fault VTRIP(sd) CS tSW Line UV Fault 2 + tON PWM Comparator Submit Documentation Feedback Q tON R tON(min) tON(max) Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 8.3 Feature Description The application designer requires some key device internal parameters in order to calculate the required power stage components and values for a given design specification. Table 6 summarizes the key parameters. 8.3.1 High-Voltage Current Source Start-Up Operation The controller includes a switched, high-voltage, current source on the HV pin to allow fast start-up, and eliminates the static power dissipation in a conventional resistive start-up approach. This feature reduces standby power consumption. The HV pin has three major functions: * Supply the device start-up current * Supply the device bias power during latched fault mode * AC sense input for X-capacitor discharge detect (UCC28630 and UCC28633 only) The UCC28630 and UCC28633 input supply to the HV start-up pin must be connected to the AC side of the bridge rectifier as shown in Figure 15, in order to support X-capacitor discharge. More details are given in Active X-Capacitor Discharge (UCC28630 and UCC28633 only), below. Connection to the AC side of the bridge also allows faster detection of AC mains removal under latched fault conditions, allowing prompt reset of latched faults for fast restart. EMC Filter VAC EMC Filter VAC RHV 1 VSENSE 2 3 SD UCC2863X CS VDD 6 4 GND 5 HV DRV 8 (a) AC-side 1 VSENSE 2 3 SD UCC2863X CS VDD 6 4 GND 5 HV DRV 8 RHV (b) DC-side Figure 15. HV Pin Connection: (a) AC-side, (b) DC-side (UCC28631, UCC28632 and UCC28634 only) Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 15 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) In the UCC28631, UCC28632 and UCC28634, the HV pin can connect to either the AC or DC side of the bridge. The addition of the 200-k external HV resistance (required for X-capacitor discharge sensing) limits the available charging current for the external bias supply input capacitor. However, for typical values of between 22 F and 33 F of input capacitance, start-up bias times of less than 1.5 s are achievable at 90 VAC. Start-up time can be estimated using Equation 1. VIN:avg; tSTART = RHV x CVDD x ln F G VIN:avg; F VDD:start_max; where * VIN(avg) = VRMS x 2 x 3/42 N for AC connection and VIN(avg) = VRMS x 2 for DC connection (1) For 90 VAC, if CVDD = 22 F and worst case VDD(start_max) = 16.5 V, then tSTART is 1.002 s. Figure 16 illustrates the start-up behavior of the controller. The HV current source has built-in short-circuit protection that limits the initial charge current out of the bias voltage pin until the bias voltage reaches VDD(sc). This limits the power dissipated in the HV current source in the event of a short circuit on the VDD pin. Thereafter, the HV current source switches to full available current. The controller remains in a low-power, startup mode until the bias voltage reaches VDD(start), after which the HV current source is turned off and the controller initiates a start-up sequence. 16 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) The bias voltage decays during the start-up sequence at a rate dependent on the size of the energy storage capacitor connected to the VDD pin. The VDD storage capacitor must be sized appropriately to ensure adequate energy storage to supply both the controller bias power and MOSFET drive power during start-up, until the VDD rail can be supplied through the transformer bias winding. If the bias voltage falls below VDD(stop) (due to bias winding fault or an inadequate VDD storage capacitance), the controller stops switching, and transitions into lowpower mode for a time delay of tRESET(long), or until the bias voltage falls to the VDD(reset) level, whichever is shorter. See VDD Capacitor Selection for required VDD capacitor sizing. Once the time delay elapses, the bias voltage rapidly discharges to the VDD(reset) level, followed by turn-on of the internal HV current source, and a normal restart attempt follows. VDD charge current is limited for VDD < 1.0 V (Short circuit protection) VDD(start) VDD(stop) Rectified bias winding voltage increases with soft-start, must exceed falling level on bias capacitor before reaching VDD(stop) threshold Controller OFF Controller ON HV Current Source OFF HV Current Source ON Device Start Up Normal Operation Soft Start Figure 16. Normal Start-Up Sequence, (assuming VAC > UV start threshold) Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 17 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) 8.3.2 AC Input UVLO / Brownout Protection At start-up, once the VDD pin has reached the VDD(start) level, the internal start-up current source is turned off. The controller tests the voltage across the bulk capacitor to determine if the level is high enough to allow the power stage to start, if it has exceeded the rising ACON level. Because there is no load across the bulk capacitor at this stage, the bulk voltage can be used as a proxy for the peak of the AC line. In order to measure the bulk voltage in a low-loss fashion, the controller generates a sequence of three exploratory switching pulses at a frequency of fSW(uv), at minimum peak-current demand level VCS(min) to avoid audible noise, and to deliver minimum energy to the output of the power stage. Based on the magnetic sampling information determined via the bias winding during these switching pulses, if the output voltage is greater than the output overvoltage threshold, the pulsing stops immediately, and the controller transitions into latched-fault mode. If, however, there is no overvoltage condition detected at the output, the pulse-set completes. If the sensed line voltage is above the line ACON start threshold, then the controller starts up normally, and begins to generate the PWM drive pulses that charge and regulate the output voltage. Alternatively, if the sensed bulk level is below the ACON threshold, then the controller enters low power mode for the reset period (tRESET(short)). It then depletes the VDD rail to the VDD(reset) level. At this point, the start-up sequence repeats, and the device generates another set of exploratory switching pulses. This sequence repeats indefinitely until the AC input is increased to a sufficient level that the bulk voltage exceeds the ACON level. VAC(on) threshold VBULK VAC rectified VDD(start) VDD(stop) VDD tRESET(short) VDD(reset) DRV Terminal Line UV check exploratory pulses Line UV check exploratory pulses Normal PWM Apply AC tONUV(max) at fSW(uv) tONUV(max) at fSW(uv) Normal PWM softstart Figure 17. AC Input UVLO Detection and Start Up Once started, the controller regularly monitors the bulk capacitor voltage. Because the ripple on the bulk capacitor depends on the load level, the device determines the maximum bulk level every 11 ms (approprite for minimum AC frequency of 47 Hz), so the AC peak can be determined. The controller provides input undervoltage protection based on the sensed AC peak level. Once the peak drops below the ACOFF level for the delay period (tUV(delay)), the PWM switching halts, and the controller enters low-power mode for the reset period (tRESET(short)). The device then discharges the bias voltage to the VDD(reset) level, followed by a restart sequence. The controller cycles through the ACON, monitoring (detailed above) indefinitely until the AC input again rises above the ACON level. 18 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) 8.3.3 Active X-Capacitor Discharge (UCC28630 and UCC28633 only) Safety standards such as EN60950 require that any X-capacitors in EMC filters on the AC side of the bridge rectifier quickly discharge to a safe level when AC is disconnected. This discharge requirement ensures that any high-voltage level present at the pins of the AC plug does not present an electric shock hazard. The standards require that the voltage across the X-capacitor decay with a maximum time constant of 1 second. Typically, this requirement is achieved by including a resistive discharge element in parallel with the X-capacitor. However, this resistance causes a continuous power dissipation that impacts the standby power performance. The power dissipation in the discharge resistors depends on the X-capacitor value. Assuming that the discharge resistor meets the 1-second time-constant requirement, (in other words, the R-C product is 1 second) the dissipation is described in Equation 2. 2 PX = VAC x CX (2) Thus at 230 VAC, the discharge resistor causes 5.3-mW dissipation for every 100 nF of X-capacitance - for a typical 470-nF X-capacitor value, that causes 25 mW to be lost in the discharge resistors. The safety standard does not mandate that the X-capacitor is fully discharged to zero within one second. It simply requires the discharge rate to exhibit a 1-s time constant. Figure 18 shows the discharge characteristic (for a 1-s discharge time constant) versus time, for disconnection at the peak of 90 VAC, 115 VAC, 230 VAC and 264 VAC. For AC inputs above 115 VAC, with 1-s discharge time constant, the voltage does not drop below the Safety-Extra-Low-Voltage (SELV) 60-V level until 1 s or longer. In fact, at 264 VAC, 1.83 seconds elapse before reaching 60 V. 400 V_SELV 350 Xcap_90 Xcap_115 300 Xcap_230 Vrms (V) 250 Xcap_264 200 150 100 50 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Time ( s) 2 2.2 2.4 C016 Figure 18. X-Capacitor Discharge with 1-s Time Constant, for Various Voltages Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 19 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) 8.3.3.1 Improved Performance with UCC28630 and UCC28633 In order to reduce standby power and eliminate the standing loss associated with the conventional discharge resistors, the UCC28630 and the UCC28633 devices incorporate active X-capacitor discharge circuitry. This circuit periodically monitors the voltage across the X-capacitor to detect any possible DC-condition (which would indicate that AC mains disconnection has occurred), and then discharges the voltage across the X-capacitor using the internal HV current source. The X-capacitor discharge function discharges the X-capacitor to the SELV 60-V level in 1 s (as long as the design considerations discussed in this section are followed). The device internally monitors the current into the HV pin to determine if the voltage across the X-capacitor in the EMI filter has a sufficient AC ripple component. If insufficient AC content is detected, then a DC condition is internally flagged. This causes the controller to enter low-power mode for the reset period (tRESET(short)), followed by bias voltage discharge to the reset level (VDD(reset)) , and then the start-up HV current source turns on again to effectively discharge the X-capacitor by transferring charge to the VDD reservoir capacitor. Because the device monitors the HV pin to detect a DC condition on the X-capacitor, the system cannot operate with DC input to the HV pin. Instead, the HV pin must be connected to an AC source only. The device interprets any DC input on the HV pin as DC across the X-capacitor, indicating an AC-disconnect event. This causes a repeating cycle of start-up and shutdown. The device requires an external 200-k of resistance on the HV pin, to limit the current to a level below the saturation point of the internal HV current source. This limit produces a HV input current that is approximately proportional to AC line, so that the AC content can be sensed. The size of the X-capacitor that can be discharged depends on the VDD energy storage capacitor. Assuming the worst case, a maximum X-capacitor disconnect voltage could be at the peak of 264 VRMS, and assuming that it should be discharged down to 60-V SELV level, the minimum allowed VDD capacitor can be sized based on the worst case VDD(reset) and VDD(start) levels as described in Equation 3. VAC :pk ; F VSELV 373 F 60 CVDD R CX x F G = CX x l p = CX x (48.15) 13.0 F 6.5 VDD :start _min ; F VDD :reset _max ; (3) For example, for a 330-nF X-capacitor value, the required VDD capacitor is 15.9 F, so a 22-F capacitor suffices. CVDD R 330 nF x :48.15; = 15.9 JF (4) In order to reduce the power consumption from the high voltage AC line, the device pulses current into the HV pin at a low frequency with very low duty-cycle. The HV current source on-time (tON(HV)) , repeats at intervals of tSMP(HV). Moreover, the pulsing occurs in bursts, with a time delay between bursts. The sampling occurs in bursts of 21, at intervals of tSMP(HV), with a wait time of tWAIT(HV) between bursts. This reduces the effective average dutycycle to a very low value (approximately 0.2%), and minimizes the overhead of X-capacitor sampling current and device bias consumption overhead to approximately 2 mW of extra standby consumption at high-line 230 VAC. The device enables the X-capacitor monitor in latched fault mode, and in light-load regions where the power level is below PLL(%), as a percentage of the nominal rated level. Above the PLL(%) level, the X-capacitor monitor is disabled. At this load level the bulk capacitor discharges at a rate that is sufficient to also discharge the Xcapacitor, which appears in parallel with the bulk capacitor once the bulk voltage drops far enough to forward bias the bridge rectifier diodes. In this case ensure that the bulk capacitance value is not too large for the power level desired, which in-turn ensures that the bulk capacitor discharge rate is fast enough to discharge the Xcapacitor to meet the 1-s discharge target. This can be calculated in Equation 5. CBULK 20 P x PLL% p xt XCAP(dis) 2 l NOM D Q kVAC(pk) 2 F VSELV 2 o Submit Documentation Feedback (5) Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) Assuming a worst case AC disconnect at the peak at 264 VRMS (373 VPK), and a requirement to discharge to SELV level of 60 V in tXCAP(dis) of 1 s, for a PNOM of 65 W at 87% efficiency, this is calculated in Equation 6. CBULK :65 x 0.125; h x1 2xd 0.87 Q Lsuz JF :3732 F 602; (6) Once the bulk capacitance value is chosen, also ensure that when the bulk capacitor has been discharged down to the line UV ACOFF threshold, that it continues to discharge to an acceptable level during the line UV persistence delay time (tUV(delay)) as shown in Equation 7. P uP * 2 u NOM LL% u t UV delay (c) C BULK d 2 2 2 u AC OFF VSELV (7) Again, taking the example above: :65 x 0.125; 2 x l p x 0.04 0.87 CBULK Q Lswv JF 2 :2 x 65 F 602 ; (8) Once the first constraint is satisfied, the second one is also automatically met. Figure 19. X-Capacitor Discharge Activation, at 230 VAC, No Load (red = X-capacitor, blue = bulk-capacitor, both 100 V/div) Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 21 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) Figure 20. X-Capacitor Decay Rate Without Active Discharge (time constant dominated by 20-M probe impedance) (red = X-capacitor, blue = bulk-capacitor, both 100 V/div) 22 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) 8.3.4 Magnetic Input and Output Voltage Sensing A sense winding on the transformer is used to measure the input voltage and output voltage of the power stage. This winding is typically the converter bias winding. The sense winding should be interfaced to the VSENSE pin as shown in Figure 21. This interface requires that the voltage across the winding be scaled with a resistor divider RA / RB, and then offset with a switched, pull-up resistor RP (in series with a diode) connected to the gate drive pin DRV. 5 DRV 1 VSENSE VF RA NB RP RB Figure 21. VSENSE Pin Interface Arrangement During the off-time portion of the switching cycle (also referred to as the flyback interval), the resistor divider (RB / (RA + RB)) scales the positive voltage swing at the VSENSE pin for output voltage regulation, as shown in Figure 22. During this interval, since the DRV output is low, the diode in series with RP is reverse-biased, and so RP is out-of-circuit. VO x (NB/NS) RA GND VO x K1 VSENSE = VO x K1 NB RB VIN x (NB/NP) Figure 22. VOUT Sense Using the Positive Swing on the Sense Winding Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 23 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) During the on-time portion of the switching cycle, when the DRV pin goes high (should swing very close to the value at the VDD pin), the switched pull-up RP allows the negative swing on the winding to be level-shifted positive, and thus also be sensed at the VSENSE pin, as shown in Figure 23. In this way the bias winding may be used to sense both line input voltage and output voltage. NOTE The input voltage sensed by the transformer bias winding is actually the voltage across the bulk capacitor, not the AC input voltage, because the bulk capacitor voltage appears across the primary winding when the flyback switch turns on Uses of the sensed bulk and output voltages: * * * * * * Input AC mains UVLO Input brownout Line-dependent peak-current adjustment Accurate output-current regulation Output-voltage regulation Output over-voltage protection (OVP) 5 DRV VF RP VO x (NB/NS) RA GND NB RB VDRV VF VIN x K2 VIN x (NB/NP) VVSENSE = VDRV VF VIN x K2 Figure 23. Line Input Sense by Offsetting the Negative Swing on the Sense Winding In order to protect the VSENSE pin from excessive negative current in the event of a manufacturing fault (such as an open circuit on RP), use a series limiting resistor and clamping diode on the VSENSE pin. Combine the clamping diode and DRV pull-up diode into a single-package common-cathode diode to reduce the component count of the system. This is illustrated in Figure 24. RP BAV70 RA NB RB 100 1 VSENSE 2 3 SD UCC28630 CS VDD 6 4 GND HV 8 DRV 5 Figure 24. VSENSE Pin Protection and Interface to Bias Winding 24 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) The device continually adjusts the input voltage sample delay, measuring the sample half-way through the ontime interval, to ensure the cleanest signal. The device uses same mid-point sample trigger when measuring the main MOSFET switch current (ISW). Sampling MOSFET switch current in the middle of the on-time automatically measures the average current during the on-time, ISW(on_avg), which is required for the current limit and overload timer block. The output voltage sample point is always time relative to the turn-off instant. Internally, the device uses the CS pin to determine the cycle end, rather than the PWM falling edge on the DRV pin. The device bases this determination on the instant that the MOSFET switch current drops below the demanded peak current level (IPEAK ) at the peak current mode comparator. Some delay always occurs from the falling edge on DRV to the point when the external power MOSFET turns off. This internal timing method ensures a more accurate measure of ISW(on_avg), and also ensures that the output voltage sample point is not measured too early, before the leakage ringing has subsided. The effect of the gate turn-off delay and the adjustment of the output voltage sample point is illustrated in Figure 25. IPK(dem) Gate turn-off delay Current Sense PWM Comparator PWM drive FET Gate VO sample delay Bias Winding Time Figure 25. VOUT Sample Adjust for External Gate Delay Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 25 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) The sampling of the input voltage and output voltage signals on the bias winding must be synchronized to the ontime and off-time flyback intervals respectively, because the signals occur during only those intervals in the switching cycle. Typical waveforms and timing are illustrated in Figure 26. More conventional knee-point detection schemes, where the sample is measured at the end of the flyback interval when the secondary-side current has decayed to zero, inherently always operate in discontinuous conduction mode (DCM). However, the fixed sample-point scheme used on the UCC2863x has the advantages of being able to operate in regions of fixed frequency, and being able to operate in continuous conduction mode (CCM). Fixed sample-point schemes conventionally suffer poorer regulation than knee-point schemes, because there is always current flowing at the sample instant. This current produces a sensing error as a result of the voltage drop produced across the secondary-side resistance and leakage inductance. This parasitic voltage drop varies with output voltage, line and load, thus influencing the regulation. The UCC2863x devices uses a novel internal compensation scheme to adjust for this parasitic voltage drop, and can deliver excellent static line and load regulation, even when operating heavily in CCM. DRV VIN Sample VIN sample delay VO sample delay VO sample Sense Winding Primary Current Secondary Current Time Figure 26. VIN and VOUT Sample Trigger Timing 26 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) 8.3.5 Fixed-Point Magnetic Sense Sampling Error Sources To support operation in CCM, and allow operation at fixed frequency over a large percentage of the load range, the UCC2863x uses fixed-point sampling rather than knee-point detection. When conventionally used, fixed-point sampling typically suffers from poorer regulation performance. This poor performance results from the voltage drops across the secondary-side parasitic resistance RSEC, and the secondary-side leakage inductance from secondary-side to bias LLK(sec_bias), as a consequence of the fact that current remains flowing on the secondaryside when the device measures the output voltage. As shown in Figure 27, the secondary-side pin voltage that gets reflected to the bias winding is detailed in Equation 9. VSEC = VOUT + VRECT + VR(sec) F VL:leak; + VRC:esr; (9) Equation 9 can be expanded and rearranged into Equation 10. VSEC = VOUT x l1 F LLK (sec bias ) p + VRECT + ISEC x kRSEC + RC:esr; o F kILOAD x RC:esr; o LSEC (10) VRECT + + + + VBIAS COUT VSEC - - RSEC VR(sec) + + LLEAK(sec_bias) VLEAK - ISEC ILOAD VO + VRC(esr) RC(esr) - Figure 27. Secondary-Side Pin Voltage Contributors with Secondary-Side Current Flow Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 27 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) Many elements contribute errors to the sensed secondary-side pin voltage, when measured across the bias winding: * VL(leak): Negative voltage drop across the sec-bias leakage inductance LLK(sec_bias); assuming constant regulated output voltage, this voltage drop is fixed constant offset, because VOUT/LSEC is constant as long as the output is in regulation. * VRECT: Positive voltage drop across the output rectifier (assuming use of a conventional diode). This voltage drop varies with load current and temperature. However, a constant nominal voltage drop can usually be used, because the increasing forward voltage drop with increasing load current is largely cancelled by the decrease in forward drop as a result of the temperature rise that results. * VR(sec): This is the drop across the secondary-side winding resistance. This value depends on loading, and varies in proportion to the primary peak current demand that is set by the modulator. * VRC(esr): This is the drop across the output capacitor equivalent series resistance (esr). This value depends on the difference between the secondary-side winding current and the DC load current being drawn. Typically, the peak secondary-side winding current ISEC is many times larger than the load current, and the secondary-side winding resistance is typically larger than the output capacitor esr. Thus, the last term in Equation 10 involving ILOAD can typically be neglected. The leakage inductance and secondary-side rectifier terms represent quasi-constant offset terms, so do not affect regulation to a significant extent. Thus, the quasi-constant offset terms can be accounted for in the calculation of the required scaling resistors to produce the desired setpoint voltage. The remaining term that dominates the regulation error in Equation 10 is the drop across the secondary-side winding resistance and capacitor esr at the sample instant, {ISEC x(RSEC + RC(esr))}. The controller internally adjusts the control loop reference in proportion to the primary peak current demand in order to null the ISEC related error term in the sampled bias winding voltage. Since the peak secondary-side current ISEC(pk) is the primary peak current IPRI(pk) scaled by the transformer turns ratio, the internal control loop reference effectively varies in approximate proportion to ISEC, resulting in dramatically improved regulation performance. This improved regulation performance allows the use of primary-side regulation in a wider range of applications, and at unprecedented power levels, operating in both CCM and DCM. 28 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) 8.3.6 Magnetic Sense Resistor Network Calculations Because the device uses the VSENSE pin to measure both VOUT and VIN of the power stage, it is important to calculate the resistor values correctly. The step-by-step design process is outlined in this section. 8.3.6.1 Step 1 Depending on the power level, choice of transformer size, and required trade-offs between primary MOSFET and secondary-side rectifier ratings, the transformer turns NP, NS and NB will be chosen first. The controller can support a wide range of turns ratios. 5 DRV 1 VSENSE VF RP RA NB RB2 RB1 Figure 28. Practical Magnetic Sense Setup with Extra Resistor RB2 for Setpoint Fine Adjust 8.3.6.2 Step 2 Once NP, and NB are known, the required value of RA in Figure 28 is calculated using Equation 11. NB R A = R P x l p x K LINE NP (11) In this equation, the internal controller gain KLINE is 49.25 (see Table 6 for key internal controller parameters), and the internal gains are designed for a fixed value for RP, (i.e. RP MUST be 3.9 k). Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 29 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) 8.3.6.3 Step 3 Once NS, target VOUT, output rectifier drop VRECT, and the secondary-side-to-bias leakage inductance LLK(sec_bias) are known, the required value for RB can be calculated. Referring to Equation 10, LLK(sec_bias) can be approximated as a percentage of the secondary-side-referred magnetizing inductance LSEC. (See Magnetic Sense Resistor Network Selection for details). RB = RA N kVOUT x k1 F %LLK:sec _bias ; o + VRECT o x @ B A NS L F 1M VOUT:ref ; (12) In this case, RB may need to be empirically adjusted to achieve the required exact output set-point, especially if VRECT varies or is not known precisely. For this reason, it is recommended that RB should be implemented on the system PCB as two parallel resistors RB1 and RB2 as shown in Figure 28, to allow easier fine-tuning of set-point. For set-point tuning, only RB should be adjusted. RA should never be adjusted, because to do so would affect the line sense gain and introduce errors into the line voltage measurement. 8.3.6.4 Step 4 Verify that the equivalent Thevenin resistance RTH of the RA/RB combination falls in the required range of 10 k to 20 k. RA x RB R A + RB (13) 10 k3 O R TH < 20 k3 (14) R TH = If the Thevenin resistance is outside of that range, then the original choice of turns ratio must be adjusted, and design steps repeated until a valid value for RTH is determined. This is unlikely to occur in practice, unless an extreme turns ratio is chosen. If RTH is outside this range, it triggers the VSENSE pin open or short pin-check at start-up. 30 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) 8.3.7 Magnetic Sensing: Power Stage Design Constraints Because the controller employs fixed-point sampling for output voltage sensing, there are some transformer design constraints that must be observed. The minimum magnetizing volt-seconds during the on-time interval occurs at the minimum CS pin voltage, VCS(min), under light-load conditions. This minimum should be the case at all line voltages, because the controller compensates for line-dependent peak-current overshoot during turn-off delay. The choice of transformer turns ratio, transformer inductance (LPRI), and current sense resistance (RCS) must ensure that the corresponding reset volt-seconds during the flyback interval are sufficient that a valid output sample is available at the sample point, tOUT(smp). This constraint is summarized in Equation 15. VCS:min ; RCS NS 1 Q x x LPRI tOUT:smp ; NP :VOUT + VRECT; where * VRECT is the voltage drop across the output rectifier (15) Additionally, the device requires a minimum on-time, tON(min) , to ensure enough time for the system input voltage (VIN) and switch current (ISW ) to be measured. To meet the minimum on-time requirement at maximum line, and minimum load, the ratio of current sense resistance (RCS) to transformer inductance (LPRI) must meet the constraint shown in Equation 16. VCS:min ; R CS 1 Q x tON:min ; VIN:pk _max ; LPRI (16) Equation 15 or Equation 16 sets the limit for the ratio of RCS to LPRI, but both need to be verified. See Typical Application for more details. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 31 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) 8.3.8 Magnetic Sense Voltage Control Loop Because the output voltage feedback is inherently a sampled signal obtained from the bias winding, the internal voltage control loop is most naturally implemented digitally. The internal control loop implements the equivalent of a PID loop in digital form. Because the output can be sampled only at certain intervals in each switching cycle, the sample rate is naturally tied to the switching frequency, and the sample rate increases with increasing frequency. However, the device clamps the sample rate at a normalized maximum rate, fSMP(max). But because the device must always synchronize to the next available switching cycle to obtain a new sample of the output voltage, the effective sample rate varies somewhat around this value. The digital control loop compensator block diagram is shown in Figure 29. A new sample of output voltage is supplied to the compensator at the normalized maximum clock rate (fSMP(max)) , or fSW, whichever is lower. An updated output voltage demand signal, yk, is produced at the same clock rate. This voltage loop demand represents the required operating point on the modulator curves to keep the output voltage in regulation. The modulator sets the appropriate switching frequency and peak current demand depending on the load power. tSMP VSENSE 1 VO Sample VO - Error ek Voltage Loop PID Compensator Output yk To fSW and IPK(dem) Modulator + VREF(adj) VREF + KR(sec) + IPK(dem) Figure 29. Digital Voltage Control Loop Simplified Block Diagram The control loop PID gain factors are internally fixed values, optimized for flyback power stages in the range between 20 W and 130 W. The loop is designed to work with magnetizing inductance values in the range between 200 H and 1500 H. Assuming that the output capacitance value is chosen based on required ripple current rating, then loop stability is not a problem. Adding extra output capacitance does not degrade the loop performance and the resulting extra output hold-up improves transient response. The Typical Application section includes gain-phase measurements taken using the 65-W UCC28630EVM-572 evaluation module. 32 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) 8.3.9 Peak Current Mode Control The controller operates in peak current mode. The primary-side switch (MOSFET) current is sensed by a shunt resistor (RCS1) connected in series with the source of the FET as shown in Figure 30. The voltage that is developed across the sense resistor is connected to the CS pin of the controller. The device uses the current sense signal at the CS pin to terminate the PWM pulse according to the peak current demand of the modulator. The device automatically applies slope compensation as soon as the duty cycle of the DRV pin pulse exceeds 50%. This compensation provides stable operation up to maximum DRV duty cycle. The device applies this slope compensation as a downslope on the demand signal at the PWM comparator, so is not measureable at the CS pin. The device synchronizes the slope compensation signal to the PWM and is active only between 50% and 70% duty cycle, as shown in Figure 31. Normal operating range for the CS pin is between 0 mV and 800 mV. The RCS1 resistor should be scaled such that the peak current at maximum peak load and minimum bulk capacitor voltage produces a signal of approximately 800 mV peak at the CS pin. This resistor value is calculated in conjunction with the calculation of the required primary magnetizing inductance, as outlined in Notebook Adapter, 19.5 V, 65 W, section. 1 VSENSE HV 8 2 3 SD UCC28630 CS VDD 6 4 GND DRV 5 CCS RCS2 RCS1 Figure 30. Primary-Side Current Sensing Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 33 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) A nominal 100 ns of filtering that is internal to the CS pin helps filter the leading turn-on spike of current. Depending on PCB layout, an RC filter (RCS2 and CCS) may be required on the CS pin as shown in Figure 30 to filter noise and spikes. The capacitor CCS should be positioned as close as possible to pins 3 and 4 and tracked directly to the pins. Series resistor RCS2 should also be located close to pin 3 to minimize noise pick-up. RCS2 value should not exceed 20 k, because a larger value could be detected as a possible open circuit on the CS pin during the start-up pin-fault checks. The R-C filter time constant should not be excessive (timing between 100 ns and 200 ns is typical). Otherwise the filter reduces the measured peak current, and allows greater actual peak current to flow versus the modulator demand level. Such effects force the regulation loop to reduce the switching frequency to compensate, and at highest line, no load, this can lead to regulation difficulties if the control loop attempts to drop the frequency so far that it reaches the fMIN limit. 50% 70% 100 mVPP Peak Current Demand With Slope Compensation 30 mV/ s PWM Clock at 60 kHz Figure 31. Peak Current Demand with Slope Compensating Downslope 34 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) 8.3.10 IPEAK Adjust vs. Line The controller applies a line-dependent reduction in the peak-current demand to correct for the current overshoot due to the PWM and gate drive propagation delay, with the aim of delivering a constant peak current versus line at a given power level. This maintains approximately constant switching frequency versus line for a given power level (until the operation enters into CCM), improves regulation, reduces audio noise, and allows lower standby power at high line. If not corrected, the current overshoot could become significant at high line, where the inductor current di/dt is higher. This overshoot would cause a pronounced increase in transferred power per switching cycle at high line, because power is proportional to IPK2. The effect of the delay on the peak-current overshoot is illustrated in Figure 32. VBULK Frequency and Peak Current Modulator RG(off) IPK(dem) adjust vs. VBULK VBULK DRV S Q R Q Gate Driver LPRI RG(on) 5 + CS LEBs Filter 3 RCS1 CCS RCS2 IPK overshoot IPK overshoot IPK(dem) IPK(adj) Propagation delay Low line Propagation delay High line Figure 32. Peak-Current Demand Adjustment vs VBULK to Correct Prop Delay Overshoot For different power stage designs, the combination of primary magnetizing inductance LPRI, current sense resistance RCS and external MOSFET gate turn-off delay tOFF(ext), must be verified against Equation 17, to ensure that the internal peak-current compensation gain range is satisfied. The KLINE(adj) factor should be within the range indicated. If the external turn-off delay is too long, then the internal IPEAK adjustment factor is too low, and the adjustment at high line is not able to achieve the required level of over-shoot compensation. As noted previously, this could result in regulation difficulties at no-load, and may cause poor line and load regulation, or require an increase in output pre-load power. K LINE:adj ; = F R CS x kt PROP:gate ; + t OFF:ext ; oG P str J and < uwrJ LPRI where * where tPROP(gate) is the internal controller gate-drive turn-off propagation delay, given in Table 6. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 (17) 35 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) 8.3.11 Primary-Side Constant-Current Limit (CC Mode) In addition to the peak-current mode PWM function, the device also uses sensed current at the CS pin to estimate the secondary-side load current. The device samples the CS pin voltage and measures it in the middle of the on-time, which is effectively the average switch current during the on time, ISW(avg_on). This measurement scheme is the case during both DCM and CCM operational modes. The average switch current during the on time is scaled by the PWM duty cycle to give the IIN(avg) of the power stage. The power stage input power, PIN, can then be estimated as the product of (VIN x IIN(avg)). The CC mode operation regulates PIN to track (IOUT(lim) x VOUT), if PIN increases to reach PIN(lim), thereby achieving a regulated constant current as shown in Equation 18. VOUT x IOUT:lim ; = PIN:lim ; D VIN x IIN:avg ; x D PIN:lim ; x D IOUT = = = IOUT:lim ; VOUT VOUT PIN = VIN x IIN:avg ; = (18) (19) tSMP1 VO VO Sample VSENSE PLIM + ILIM x VO Error iek 1 VIN VIN Sample PIN Compute P=(VIN x ISW(MID))x(tON/tSW) Current loop PI compensator Output iyk To fSW and IPK(dem) Modulator PIN tSMP2 tON tSMP3 CS 3 ISW Sample tSW ISW(mid) Figure 33. Digital Current Control Loop Simplified Block Diagram 36 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) Assuming that the power stage efficiency does not change significantly with operating point, by regulating the input power in inverse proportion to output voltage, this regulates output current. This achieves a brick-wall CC characteristic, where the output current is regulated as the input voltage changes and as the output voltage rolls off, regardless of power stage operating mode (CCM or DCM). The CC mode protection eliminates the characteristic load current tail-out that is typically seen with peak-current mode control as output voltage collapses and operation goes deeper into CCM mode. NOTE As the output voltage decreases in CC mode, the VDD level also decreases. If the overload is severe, the drop in output voltage causes VDD to drop below the VDD(stop) UV level. This drop causes a shutdown for tRESET(long), as given in Table 6, followed by a restart attempt. The constant-current mode output current limit level (IOUT(lim)) is a function of both the RCS1 resistor and the transformer turns ratio. The device uses an internal reference and gain for the CC loop, KCC1 and KCC2, that set the CC IOUT(lim) point as a function of the chosen turns ratio, output voltage and current sense resistance as shown in Equation 20. IOUT:lim ; = 1 NP KCC1 x x N RCS1 NS KCC2 +VOUT x P NS (20) For the UCC28631, UCC28632 and the UCC28633 devices, the IOUT(lim) can be adjusted to be a percentage of the maximum value calculated by equation Equation 20. see CC-Mode IOUT(lim) Adjustment for more details. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 37 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) 8.3.12 Primary-Side Overload Timer (UCC28630 only) The internal overload timer in the UCC28630 uses the same output load current measurement that is used by the CC loop. This measurement tracks the power stage thermal stress, and protects the power stage against output overload. If the output is overloaded for too long such that the power stage would be over-stressed, then the PWM shuts down, and enters low-power mode for a time period of tRESET(long); thereafter the device discharges VDD to the VDD(reset) level and initiates a hiccup mode restart. The overload timer operates by taking an estimate of output current, squaring it (assuming the power stage losses are dominated by resistive I2 losses) to produce (K x I2OUT), where K is a scaling gain factor. The overload timer is constantly running at every load level, and accumulates at a rate dependent on the difference between (K x I2OUT) and the previous level of the timer. If (K x I2OUT) is greater than the previous timer level, the timer level continues to increase; if (K x I2OUT) is less than the previous timer level, then the timer level decreases. At any steady load, the overload timer level eventually settles at a level proportional to I2OUT. Because the overload timer level adjusts at a rate dependent on the difference between (K xI2OUT) and the previous level, the timer initially reacts faster to larger differences, but over time settles exponentially at a level proportional to (K x I2OUT). As shown in Figure 34, in both the first and second examples, the initial steady load allows the timer to integrate and settle at a level proportional to the load. The margin to the over-load trip level depends on the historical loading, lower prior average loading results in greater future over-load capability, and vice versa. The rate at which the timer reacts to different load steps is set by the chosen time constant (or response rate) per Table 1. The overload timer can cope with pulsed loads and loads with a complex waveform. Because the rate of increase and decrease also depends on the load change from the previous load, it also times out faster for bigger overloads, or allows a smaller overload to run for much longer. The overload timer operates in both normal CV mode and overload CC mode, or a dynamic mix of both modes. 38 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Feature Description (continued) PPEAK Load Power PTRIP Overload Timer Value Overload Trip Point Example 1: Operation at PRATED continuously; small load increase after long time causes overload timer to trip Time PPEAK Load Power PTRIP Overload Timer Value Overload Trip Point Time Example 2: Operation at low power continuously; step to peak load causes fastest overload timer ramp-up rate to trip level PPEAK Load Power PTRIP Overload Timer Value Overload Trip Point Example 3: Operation at low power continuously; repeated short-pulse steps to peak load excessive duty cycle causes eventual overload timer trip Time Figure 34. Overload Timer Example Waveforms Under Various Load Scenarios tSMP1 VO VSENSE PLIM(cc) ILIM x VO VO Sample PIN2 + X2 Block 1 VIN VIN Sample PIN Compute P=(VIN x ISW(MID)x(tON/tSW) PMEAS(cv) CC/CV Mode Detect Switch Overload Timer Integrator Overload Signal + To Fault Mgmt Block PTRIP2 tSMP2 tSMP3 CS 3 ISW Sample tON tSW ISW(MID) Figure 35. Overload Timer Block Diagram Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 39 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) 8.3.13 Overload Timer Adjustment (UCC28630 only) The UCC28630 overload timer trip level and time constant are both selectable from a defined list of combinations. The user can select the overload timer trip level as a percentage of the rated continuous nominal power, PNOM (see Figure 41), and the timer response speed. The available choices are detailed in Table 1. Table 1. Overload Timer Adjustment RPROG PROGRAMMING RESISTOR (k) (E96 series values) TIMER CONTINUOUS OPERATION PTRIP/PNOM (%) TIME CONSTANT AT 200% of PNOM OR IN CC MODE (ms) Open, or > 47 160 1000 20.0 160 500 12.7 160 150 9.31 135 1000 7.32 135 500 6.04 135 150 5.11 110 1000 4.42 110 500 3.92 110 150 The desired pull-down resistance on the DRV pin sets the required overload parameters, as shown in Figure 36. The controller measures the resistance value on the DRV pin at start-up using a low-level test voltage (400 mV to ensure it is well below the lowest possible power MOSFET gate threshold voltage) and sensing the current that flows. Thus, based on the resistance RPROG, the required set of timer parameters can be chosen. 1 VSENSE HV 8 2 3 SD UCC28630 CS VDD 6 4 GND 5 DRV RPROG Figure 36. Overload Timer Setting Adjustment (with programming pull-down resistor on DRV pin) To ensure that the sensed current does not sit close to an interval boundary, the resistor values listed in Table 1 (or the closest value possible) should be used. These recommended resistor values position the test current in the center of each interval. 40 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 8.3.14 CC-Mode IOUT(lim) Adjustment For the UCC28631, UCC28632, UCC28633 and UCC28634, the pull-down programming resistor on the DRV pin, as shown in Figure 36, sets the desired CC-Mode limit. The available CC-Mode levels are listed in Table 2, where the CC limit is given as a percentage of the maximum allowed value from Equation 20. Table 2. CC-Mode Levels RPROG (k) CC LIMIT Open or > 47 100% 20 90% 12.7 80% 9.31 75% 7.32 70% 6.04 65% 5.11 60% 4.43 55% 3.92 50% 8.3.15 Fault Protections The controller has several built-in fault protections. Most faults are subject to internal persistence filtering to avoid false-tripping due to noise or spurious glitches from external events. When a fault is detected and persists for the corresponding filter delay time, the device terminates and disables the PWM drive signal. No PWM activity occurs if the fault (pin faults for example) is detected at start-up . Table 3 lists all fault sources, persistence delays and the associated response (latching or auto-restart). In the case of auto-restart (sometimes called hiccup-mode) faults, the device enters low-power mode for a time period of tRESET(long) (or tRESET(short) in the case of AC line UV fault and X-capacitor discharge), then discharges the VDD pin to the VDD(reset) level, followed by a restart attempt. The device continues in a repeating shutdowndelay-restart loop until the fault is removed. Once the fault clears, the controller restarts automatically, there is no need to remove and re-apply AC input voltage to the system. Latching faults do not allow any PWM restart attempts until the AC input voltage is removed. In this case the controller enters low-power mode. During low-power mode, the device regulates the VDD pin between two levels VDD(latch_hi) and VDD(latch_lo), as given in Table 6, using the start-up HV current source. This regulation keeps the controller biased to maintain the latched fault condition as long as AC voltage is present at the input. When the device loses AC input voltage during latched-fault mode, the controller resets, and restarts when the AC input is re-applied. If there is an open-feedback fault due to an open or short on the VSENSE pin or associated external resistor divider on the aux winding, the output voltage is protected against an over-voltage condition. If the openfeedback fault occurs before power-up, the fault will be detected by VSENSE pin- fault protection (see next section 9.3.16), and the controller will not generate any PWM drive signal. This prevents any possible output OV due to this open-feedback fault condition. If the open-feedback occurs after power-up, when the power stage is already operating, the open-feedback condition can cause Vout to increase. In this case, the VDD level will also increase in proportion to Vout (they will track based on the Flyback transformer turns ratio). When the VDD rail reaches the VDD(ovp) protection threshold, the PWM will be disabled, and the controller will go to fault mode, as described above. The VDD(ovp) protection is used as an indirect back-up OV protection mechanism for the main output under running open-feedback fault conditions. The level of output OV depends on the ratio of the normal VDD regulation level to the VDD(ovp) level. Note that UCC28630/1/2/3 use VDD(ovp) trip level of 17.5 V nominal, whereas the UCC28634 uses a lower VDD(ovp) of 14.85 V nominal, to ensure a lower/tighter level of output OV under VSENSE open-feedback conditions. As a result, the user must be careful to choose the number of turns in the transformer aux winding to ensure that the normal VDD regulation is below the VDD(ovp) protection level, to avoid false-triggering of the VDD(ovp) protection. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 41 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Table 3. Fault Sources and Associated Responses RESPONSE FILTER DELAY TIME UCC28630 UCC28631, UCC28632, UCC28633 UCC28634 FAULT TYPE TYPICAL CAUSE VDD OV Excessive transformer leakage; system board fault 125 s (1) Latching Auto-restart Auto-restart VDD UV Insufficient VDD capacitor; system board fault 125 s (1) Auto-restart Auto-restart Auto-restart Auto-restart Auto-restart Auto-restart AC brownout AC voltage removal or extended dip OverTemp Internal TJ(max) reached 125 s (1) Latching Auto-restart Auto-restart SD pin low External NTC over-temperature event 125 s (1) Latching Auto-restart Auto-restart Auto-restart N/A N/A Latching Auto-restart Auto-restart Overload timer Excessive load power for too long Output OV VSENSE pin DRV pin CS pin Internal fault (1) (2) (3) 42 40 ms Programmable (2) System board fault; system output voltage back-driven excessively 125 s Short or open detected at start-up No filter (3) Latching Latching Auto-restart Short detected at start-up No filter (3) Latching Latching Auto-restart Short or open detected at start-up No filter (3) Latching Latching Auto-restart No filter (3) Latching Latching Auto-restart Internal chip diagnostics fault detected (1) The filter delay time is either 125 s or 2 PWM periods, whichever is longer. The overload timer delay can be programmed as shown in Table 1. Because these faults are only identified before PWM commences, noise filtering is not required. Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 8.3.16 Pin-Fault Detection and Protection The controller includes protection against most practical pin faults. These faults include open pins, pins shorted to adjacent pins, pins shorted to GND and pins shorted to VDD. The device performs pin fault checking at startup, before the PWM is enabled. Table 4 summarizes the response to pin faults. Most faults cause either a latched shut-down, or failure to start-up. For UCC28634, all pin-faults are non-latching. A short-circuit from the HV pin (pin 8) to the VDD pin (pin 6) is unlikely to occur, because pin 7 is not included in the package. The HV pin and tracking requires additional PCB spacing in any event to meet creepage requirements. However, if such a fault does occur, the device continues to charge the VDD capacitor through the HV pin external series resistor, and the power supply starts up and appears to operate normally. But because the HV and VDD pins are shorted, the internal HV current source cannot switch-out the external HV resistor, so it always dissipates power. This condition results in a large increase in no-load standby power. A 200-k external HV resistor, dissipates 66 mW at 115 VAC, and 265 mW at 230 VAC. At load levels where the X-capacitor discharge function is operational, the short to VDD appears to be an AC-disconnect event, and causes the device to cycle on and off. Table 4. Pin Faults and Associated Responses PINS NAME OPEN ADJACENT SHORT GND SHORT VDD SHORT NO. VSENSE 1 Latched fault Latched fault Latched fault No start-up SD 2 Normal operation Latched fault Latched fault Latched fault CS 3 Latched fault Latched fault Latched fault No start-up GND 4 Device fails, power supply damaged Latched fault N/A No start-up DRV 5 Hiccup fault No start-up Latched fault No start-up VDD 6 No start-up No start-up No start-up N/A no pin 7 N/A N/A N/A N/A HV 8 No start-up N/A No start-up Fault not detected/Hiccup fault Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 43 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 8.3.17 Over-Temperature Protection The controller has built-in thermal protection. If the controller junction enters an over-temperature condition, the controller shuts down. The fault response (latching or auto recovery) depends on the device variant, per Table 3. There is 10C hysteresis in the over-temperature trip point, the controller only restarts if the junction temperature has dropped by at least 10C below the trip level. 8.3.18 External Fault Input An external fault input signal may be applied to the controller SD (shutdown) pin. This signal forces the controller into fault mode. To trigger the fault, the voltage on this pin should be pulled below the fault trip threshold. A typical application is shown in Figure 37, where this pin is used to shut down the controller in the event of an over-temperature event as detected by a NTC (negative temperature coefficient) thermistor. The device pulls up the SD pin internally using a current source. As temperature rises, the external NTC resistance decreases, reducing the voltage on the pin. When the pin voltage drops to the fault trip threshold, the controller enters fault mode. The fault response (latching or recovery) depends on the device variant, per Table 3. VSENSE HV 4V5 1 8 210 mA SD UCC28630 2 RADJ NTC R1 at 25C R2 at TTRIP CS + Over Temperature 6 3 to + GND VDD 2.0 V DRV 4 5 Figure 37. Fault Interface to SD Pin The required trip resistance can be calculated from the internal trip voltage and pull-up current source. Nominally, this is 9.5 k. Choose the NTC should so that it can achieve this value of resistance at the desired hot-spot trip temperature. If the NTC resistance is too low at the required trip temperature, connect a standard chip resistor in series to bring the total resistance up to 9.5 k. The device internally filters the SD pin with persistence delay as listed in Table 3. An external filter capacitor is not normally necessary. However, if an application uses an external filter capacitor, the value should be limited to 1 nF maximum. A larger value may impact the useful life of the controller. 44 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 8.3.19 External SD Pin Wake Input (except UCC28633) During low-power modes (when fSW < fSMP(max)), the device disables the internal pull-up on the SD pin. This action allows the pin voltage to fall to GND, and the SD pin then functions as a transient wake-up input. In this case, if the pin rises above the wake threshold while the device is in low-power sleep mode, the device wakes and starts PWM pulses immediately. This feature is useful for applications that require a faster response to load transients from zero or near-zero load, where a wake-up signal can be appropriately coupled to the SD pin from the secondary side. Figure 38 describes a typical secondary-side wake circuit and coupling of the wake signal to the controller on the primary side. This circuit uses a TL103W component which is an integrated reference plus two op-amps in a convenient SOIC-8 package. Both op-amps are connected to the same internal 2.5-V TL431 type reference, with a 3-resistor divider chain allowing each op-amp to monitor a different level. The upper op-amp output is low as long as the device is regulating the output voltage normally. If a sufficiently large load transient occurs while the primary-side controller is in sleep mode, the output voltage drops below a transient wake level. The upper opamp output goes high, driving current through the low-cost wake signal opto-coupler. On the primary side, the wake opto-coupler pulls up the SD pin above the wake threshold and forces PWM switching as a reaction to the load transient. The lower op-amp section monitors the output voltage and its output goes low only when the output voltage is above a minimum enable threshold for the secondary-side wake-up monitor. This action is necessary so that under certain conditions, such as a start-up sequence or short-circuit condition (when the output voltage is already below the transient wake level) that the secondary-side circuit does not continually drive the wake optocoupler, which could activate an SD pin fault during pin-fault checking at start-up. VOUT RPULLUP HV VSENSE 8 LED 1 UCC28630 Wake-up signal 2.2 V SD + CS + 2 + VDD 6 TL103W + 3 DRV to 2.5 V GND 5 4 Figure 38. Typical Secondary-Side Voltage Monitor and Wake-Up Circuit for Interfacing to the SD Pin Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 45 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 8.3.20 External Wake Input at VSENSE Pin (UCC28633 Only) The UCC28633 device variant supports fast PSR transient response via the VSENSE pin. When the loop demand drives the modulator frequency below approximately fSMP(max), the controller enters a low-power sleep mode for a portion of the switching cycle. The sleep interval varies, depending on the switching frequency commanded. The sleep interval is longer for lower switching frequency, and longest at fSW(min). For conventional PSR controllers, if a load transient occurs during this sleep interval, the controller will not react until the next timed wake-up, during which the output voltage can drop significantly, depending on the size of the load step and the amount of output capacitance. The UCC28633 can respond to fast transient wake signal coupled to the VSENSE pin. If the wake signal exceeds an internal pin threshold VSENSE(wake) while the controller is in sleep mode, the sleep interval is terminated and PWM activity commences within a typical delay time of tWAKE. This dramatically improves the response to heavy load transients from zero load, or very light load. If the switching frequency is above fSMP(max), the controller never enters sleep mode, so wake response on the VSENSE pin never enabled. The commencement of any sleep interval in the controller is delayed until the resonant ringing on the VENSE pin has decreased below the VSENSE(wake) threshold for at least 2 s. Once the ringing has decreased, the wake response is enabled, and the sleep interval commences. VOUT VAC EMC Filter UCC24650 5 WAKE VDD 1 GND 2 UCC28633 1 VSENSE HV 8 2 SD to 3 CS VDD 6 4 GND DRV 5 Figure 39. UCC24650 Secondary-Side Voltage Monitor and Wake-Up Circuit 46 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 The wake signal at the VSENSE pin can be generated using a secondary side low power voltage monitor such as UCC24650, as shown in Figure 39. Further details can be found in the datasheet for UCC24650. This secondary-side monitor uses the switching activity on the secondary winding to trigger refresh of an internal sample-and-hold circuit to measure and record the system output voltage at the VDD pin. Thereafter, if the actual output voltage, sensed at the VDD pin, drops by WAKE% (see UCC24650 detailed datasheet specifications) of the previously sampled value, the WAKE pin is internally pulled low through a current-limited open-drain switch. As shown in Figure 39, the main output rectifier diode is positioned at the return side of the secondary winding, so that the GND-referenced UCC24650 WAKE function can be deployed. In effect, the WAKE pin shorts out the rectifier diode for a short interval (see UCC24650 detailed datasheet specifications), to draw some current from the output capacitor through the transformer secondary winding. This sets up a low-level pulse of current that then rings resonantly in the power circuit magnetizing inductance and parasitic capacitance. The ringing causes a similar ringing voltage waveform on all transformer windings, including the bias/sense winding, which interfaces to the VSENSE pin. If the initial pulse of current drawn by the secondary WAKE pin is sufficient, then the ringing voltage at the VSENSE pin is large enough to exceed the VSENSE(wake) threshold. The UCC24650 datasheet Application Information section includes details of how to estimate the amplitude of the wake-pulse ringing at the WAKE pin. In some cases, especially at higher rated output power, the transformer magnetizing inductance is lower, while the total switch node capacitance tends to be higher. This reduces the transformer impedance, and can also result in reduced wake pulse amplitude. In these cases, the UCC24650 WAKE pin output can be augmented with an external PNP circuit Q1, R1 and R2, as shown in Figure 40. In this case, when the WAKE pin pulls low, Q1 turns on, and draws more current through the secondary winding. A current limiting resistor R1 is recommended in series with either collector or emitter. Effectively R1 swamps the UCC24650 internal WAKE pin resistance, RWAKE. A pull-up resistor R2 from base to emitter is also required, to ensure that the WAKE pin is adequately pulled up/down during normal switching activity to properly trigger the internal sample and hold on the VDD pin. The external PNP device Q1 must have at least the same voltage rating as the main rectifier diode. VOUT VAC EMC Filter R1 Q1 R2 UCC24650 5 WAKE VDD 1 GND 2 UCC28633 1 VSENSE HV 8 2 SD t o 3 CS VDD 6 4 GND DRV 5 Figure 40. Augmented UCC24650 Secondary-Side Voltage Monitor and Wake-Up Circuit Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 47 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 8.3.21 Mode Control and Switching Frequency Modulation The flyback controller supports applications that require a wide range of operating power levels. This range can include effectively zero output power in standby conditions, up to a maximum rated continuous power, and then beyond this, to a mode of peak operating power for a limited time. The modulator operates in multiple modes to support these power requirements in an efficient way. In some regions, the modulator operates in AM mode at fixed frequency, where the device adjusts the amplitude of the peak current to regulate the output. In other regions, the modulator operates in FM mode at fixed peak current, where the device adjusts the switching frequency to regulate the output. By adjusting only peak current or frequency, (depending on operating region) the control loop smoothly regulates the power flow of the power stage. The shape of the modulator gain curve helps counteract the increasing power stage gain as load is decreased. In the high-power region of the modulator, the device adjusts both peak current and frequency together, to allow higher power delivery with a modest increase in peak current. In this high-power region, the power stage typically transitions into continuous-conduction mode (CCM), particularly at low line. The combination of up to 2x frequency increase and 1.25x peak current increase in CCM allows up to 2x peak power delivery capability for a given transformer size. Figure 41 provides details regarding the modulator peak current (in mV at the CS pin) and switching frequency variation vs power demand level. The frequency adjusts from a minimum of 200 Hz up to a maximum of 120 kHz. The peak-current sense voltage at the CS pin varies from 172 mV to 800 mV. Table 5 summarizes the modulator breakpoints and corresponding percentage power levels. 800 150 640 120 Frequency (kHz) 400 VCS(pk) (mV) 60 170 30 0.2 0% P0 0.025% PNOM 12.5% P1 30% P2 45% P3 70% P4 0 100% P5 Control Loop Demand Level 3.5% PNOM 20% PNOM 40% PNOM 100% PNOM >=200% PNOM Approximate Power Level Figure 41. Modulator Modes and Frequency Variations with Power Level 48 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 For no load and very light loads (P0 to P1 region) the modulator operates in a pulse frequency modulation (PFM) mode. In PFM mode, the device maintains a constant peak current in the transformer magnetizing inductance, so that the energy transferred in each switching cycle is fixed. The magnetic sensing, fixed-point sampling scheme requires that the device always imposes a minimum peak current. This minimum peak-current demand naturally results in a minimum transformer magnetizing volt-second product that the device maintains across the input line voltage range. Ensuring a minimum on-time magnetizing volt-seconds also ensures a balancing volt-second flyback interval, during which the device guarantees the availability of the output voltage sample. Magnetic Sensing: Power Stage Design Constraints outlines the transformer design constraints necessary to comply with the minimum on-time and minimum required volt-seconds. In the P0 to P1 region, the energy transfer per switching cycle is maximized, which in turn minimizes the switching frequency and associated switching and drive losses, to improve efficiency. However, due to concerns about audible noise in this region, the peak current VCS(min) in this region is limited to 22% of the peak VCS(max) at the maximum demand level. This peak-current derating maintains the transformer peak flux density to 22% of the peak, to minimize transformer-induced audible noise. Assuming a maximum peak flux density of typically 300 mT at highest peak current, this derating sets the peak flux level at approximately 65 mT in the light-load region. Empirically, this flux level greatly reduces magnetic audible noise for a variety of power levels and transformer designs. In this region, the use of sleep modes (where most of the device internal blocks are powered down in between switching cycles) minimizes the controller power consumption. Minimizing controller power consumption helps reduce total standby power consumption, and also greatly eases the bias design constraints. For higher loads above P1 (P1 to P2 region), the device fixes the modulator frequency at a low value above the audible range, while the peak switch current ramps up from the minimum level, to deliver the increased output power. Maintaining a fixed low-switching frequency while ramping peak current, minimizes switching losses to provide good light-load efficiency. For higher loads above P2 (P2 to P3 region), the device maintains a constant peak-switch current, while the modulator frequency ramps to its nominal operating value. The normal heavy load (between 40% and 100% of rated) operating power range lies between P3 and P4. In this region the device maintains a constant switching frequency at the nominal value fSW(nom), and the peak switch current ramps to achieve increased output power. Fixed-frequency operation at nominal operating power results in consistent EMI and transient load step performance. Table 5. Frequency and Peak-Current Modulator Operating Ranges and Breakpoints MODULATOR BREAKPOINT DEMAND LEVEL (%) APPROXIMATE POWER LEVEL % of PNOM (mV) PO0 0 0.025 172 VCS(min) 0.200 fSW(min) PO1 12.5 3.5 172 VCS(min) 30 fSW(LL) PO2 30 20 400 VCS(nom) 30 fSW(LL) PO3 45 40 400 VCS(nom) 60 fSW(nom) PO4 70 100 640 VCS(bcm) 60 fSW(nom) PO5 100 > 200 800 VCS(max) 120 fSW(max) Copyright (c) 2014-2017, Texas Instruments Incorporated VCS PEAK FREQUENCY fSW (kHz) Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 49 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com The peak-power range lies between P4 and P5. In this region the transformer can operate in CCM depending on loading and line voltage. By increasing the frequency appropriately, higher average input current can be processed for the same peak current, so the transformer size does not need to increase substantially for a highrated transient peak power. The modulator does, however, also increase the peak current in this region of operation, requiring a modest increase in transformer size, but this allows a larger transient peak power to be delivered. The modulator control loop adjusts both the frequency and peak current according to the power demand so that the increased frequency and peak current meets the load demand. Figure 42 shows the modulator gain curve, specifically the non-linear modulator gain vs load. At very light loads, the modulator gain remains low, to help counteract the effect of the higher power stage gain as the load resistance increases. This low gain helps stabilize the magnetic regulation loop in the light load territory, where the output voltage sample rate drops with decreasing switching frequency. At heavier loads, the modulator gain progressively and smoothly increases to help improve transient response. When the switching frequency increases above the maximum magnetic sense sample rate (fSMP(max)), the magnetic sense voltage control sample rate is clamped. >=200% PNOM 100 V Power Level 380 V 75 V 100% PNOM Linear Gain DCM Operation Up to Prated 0% 0.025% PNOM Peak Power Region DCM/CCM Operation (Line dependent) 25% 50% 70% 100% 14% PNOM 47% PNOM 100% PNOM >=200% PNOM Control Loop Demand Level Approximate Power Level Figure 42. Modulator Gain Curves vs Bulk Capacitor Voltage 50 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 8.3.22 Frequency Dither For EMI (except UCC28632) To help ease EMI compliance of the system, the device dithers the switching frequency over time. This dithering of frequency is active only above the light-load region threshold (PLL(%)) point on the modulator curve. In the light load regions, frequency dither is disabled. The frequency dither follows a repeating pattern, in the sequence: {(fNOM), (fNOM + 6.7%), (fNOM + 6.7%), fNOM), (fNOM - 6.7%), (fNOM - 6.7%), (fNOM), . . . .} The controller dwells at each frequency for 1 ms. The pattern repeats every 6 ms, as shown graphically in Figure 43. NOTE The device always dithers frequency between 6.7% and -6.7% at every operating point in the modulator. The dither frequency delta is not an absolute delta, it scales with actual operating frequency, depending on the exact operating point value. (fNOM + 6.7%) 6 ms fNOM (fNOM - 6.7%) Figure 43. Frequency Dither Pattern Details In order to balance the power flow and reduce and output ripple as a consequence of frequency dithering, the device automatically adjusts peak-current demand in inverse-proportion to the square-root of the frequency dither deviation. Thus, since the power flow (in DCM) is given by (1/2 x L x I2 x fSW), this balances the power flow, and cancels the output ripple as a consequence of frequency dithering. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 51 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 8.4 Device Functional Modes 8.4.1 Device Internal Key Parameters The application designer requires some key device internal parameters in order to calculate the required power stage components and values for a given design specification . Table 6 summarizes the key parameters. Table 6. Key Internal Device Parameters PARAMETER DESCRIPTION VALUE UNIT Minimum AC mains input RMS voltage to allow initial start-up, or restart, UCC28630, UCC28631, UCC28632, UCC28633 80 VAC Minimum AC mains input RMS voltage to allow initial start-up, or restart, UCC28634 68 VAC Minimum AC mains input RMS voltage below which PWM stops, UCC28630, UCC28631, UCC28632, UCC28633 65 VAC Minimum AC mains input RMS voltage below which PWM stops, UCC28634 58 VAC tUV(delay) Delay time for which AC mains must remain below ACOFF level to disable PWM, i.e. brownout delay time 40 ms tRESET(short) Delay time in sleep mode before restart is initiated - applies to ACUV, X-capacitor discharge responses 500 ms tRESET(long) Delay time in sleep mode before restart is initiated - applies to all other auto-restart faults 1,000 ms fSW(uv) Switching frequency used during initial 3-cycle exploratory pulses for ACON detection at start-up 15 kHz tON(max_uv) Maximum on-time used during initial 3-cycle exploratory pulses for ACON detection at start-up 2.3 s KLINE Device internal line sense gain factor 49.25 KCC1 Device internal CC mode gain factor 44.5 KCC2 Device internal CC mode offset factor 69.5 fSMP(max) Maximum magnetic sense sample rate; in effect when fSW > fSMP(max) 16 kHz VDD(latch_hi) Upper VDD regulation level during latched fault mode 10 V VDD(latch_lo) Lower VDD regulation level during latched fault mode 8 V tON(hv) HV current source on-time during X-capacitor sampling 20 s tSMP(hv) HV current source sample repetition rate during X-capacitor sample burst 1 ms tWAIT(hv) HV current source wait-time between X-capacitor sampling bursts 200 ms PLL(%) Light-load region threshold as % of PNOM VDD(sc) VDD short-circuit threshold below which charging current is limited 1.0 V tPROP(gate) Internal PWM comparator + latch + gate driver aggregate delay 100 ns tSTART(del) Internal start-up initialization delay 3 ms VSENSE(wake) VSENSE pin wake threshold for fast transient response (UCC28633 only) 0.8 V ACON ACOFF 52 Submit Documentation Feedback 12.5% Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The UCC2863x device is a highly integrated primary-side-regulated (PSR) flyback controller, supporting magnetically-sensed output voltage regulation via the transformer bias winding. This sensing eliminates the need for a secondary-side reference, error amplifier and opto-isolator for output voltage regulation. The device delivers accurate output voltage static load and line regulation, and accurate control of the output constant-current limit. The fixed-point magnetic sampling scheme allows operation in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The combination of the sampling scheme and high current gate driver source and sink capability, makes this device ideal for high power flyback converters up to 100 W and beyond. The modulator adjusts both frequency and peak current in different load regions to maximize efficiency throughout the operating range. The control approach improves performance (efficiency, size and cost) and can reduce transformer size and cost by allowing operation in CCM with FM during peak overload conditions. The modulator supports peak-to-average transient overload power up to 200% of the nominal average rating. 9.2 Typical Application 9.2.1 Notebook Adapter, 19.5 V, 65 W This design example describes the PWR572 EVM design and outlines the design steps required to design a constant-voltage, constant-current flyback converter for a 19.5-V/65-W notebook adapter. For all equations and design steps, refer to Table 6 for definitions and values of key internal device parameters that are relevant for calculations of external component values. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 53 TP2 MAG J1 C14 1000pF MAG 88VAC - 230VAC 0.5A - 1.5A 2 1 GND TP3 ES1D-13-F 200V D1 NEUTRAL TP4 39213150000 V1 4.70 R1 C2 22F VDD TP11 C1 0.33F D10 VDD C3 1F 3 4 F1 2 1 C4 0.1F R2 100k ACB L1 RLTI-1099 4.5mH ACA DRV 100k R3 D2 1N4007 1000V 4 5 6 8 - 2 ~ ~ + NT1 Net-Tie -VPRI 1 CS SD 4 3 2 1 STARPT GND RLTI-1098 C7 27F 1 L2 47.7H 3 C6 120pF C15 10pF R5 1.00k 0 R6 DANGER HIGH VOLTAGE GND TP5 BR1 800V VSENSE UCC28630D DRV VDD HV U1 D3 1N4007 1000V 3 LINE TP1 -VPRI t Submit Documentation Feedback C5 100F RT1 470k of net 100 R4 STARPT R8 39k DRV R9 180k C8 0805 R12 1206 R7 22.6k MAG HV TP6 Minimize copper area -VPRI VDC 47.0 R11 STARPT 0 R20 D4 BAV70-V R10 3.90k 100V D5 D6 C16 10pF R13 4.7 MAG R15 100k 1 +VSW MURS160-13-F CS D9 1SMB5949BT3G 100V D8 1SMB5947BT3G 82V 2 2 6 1 5 4 R16 0.2 11 10 9 8 also High voltage Net of VSW net Minimize copper area RLTI-1100 T1 TP7 GND Q1 STF13NM60ND 600V -VPRI -VPRI 3 54 0603 C10 R17 1206 NTST30100CTG 100V D7 C9 2200pF -VPRI Connect 2 pins of bobbin to Vsec and Ret nets VSEC RET C11 680F R18 8.20k LED1 Green TP8 TP9 RET TP10 +VOUT C13 1F +VOUT +VOUT 1 2 3 4 5 J4 C12 680F J2 OUTPUT R/A SOCKET 1 2 18.5V - 20.5V 0A - 7A UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Typical Application (continued) 9.2.2 UCC28630 Application Schematic Figure 44. Typical Application Circuit for 19.5-V / 65-W Adapter Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Typical Application (continued) 9.2.3 Design Requirements Table 7. Design Requirements DESIGN PARAMETER TARGET VALUE Output voltage 19.5 V Rated (continuous) output power 65 W Peak (transient) output power 130 W Peak (transient) output power duration 2 ms Input AC voltage range 88 VRMS to 264 VRMS Typical efficiency 88% Minimum bulk voltage at 88 VAC/47 Hz and rated (continuous) output power 82 V 9.2.4 Detailed Design Procedure 9.2.4.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the UCC2863x device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 9.2.4.2 Input Bulk Capacitance and Minimum Bulk Voltage The required bulk capacitance value depends on the target minimum bulk capacitor ripple voltage at minimum AC input line, minimum line frequency and on the power level of interest. As a way of estimating, use 1.5-F to 2-F per Watt of rated, continuous power to achieve approximately 70 V to 80 V minimum at 88 VRMS input. This case indicates a required bulk capacitance of between approximately 100 F and 130 F. Alternatively, the required capacitance may be explicitly calculated for a specific set of requirements using Equation 21. CBULK = VBULK:min ; POUT 1 x L0.5+ x sin-1 F GM N D 3/42 x VAC:min ; 2 2 k2 x VAC:min ; F VBULK:min ; o x fLINE:min ; (21) Using the parameters in Table 7, this calculates a required CBULK of 130 F. To help reduce differential mode (DM) emissions for conducted EMC compliance, the bulk capacitance has been split into two separate capacitors C5 and C7 in Figure 44, with a small DM choke L2 inserted between the capacitors. The total resulting capacitance of 127 F is close to the required minimum requirement per Equation 21, and the design results in a small decrease in the actual bulk capacitor minimum ripple voltage. Next, verify that the choice of bulk capacitance satisfies the X-capacitor discharge constraints for rate of discharge by the load when X-capacitor sampling is inactive, per Equation 5. The bulk capacitance should be less than the value calculated by Equation 22. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 55 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com P 2 @ NOMA x PLL(%) x tDIS 2:65 x 0.125; x 1 D CBULK Q = Lsux JF :3732 F 602; kVAC:pk ; 2 F VSELV2 o 56 Submit Documentation Feedback (22) Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 9.2.4.3 Transformer Turn Ratio Choose the transformer primary-to-secondary-side turns ratio based on the allowed voltage stress for the output rectifier, or the primary MOSFET. For 19.5-V charger designs, it is valid to choose a turns ratio that allows the use of a more efficient 100-V Schottky rectifier. VAC:pk _max ; NP = NS kVREV:rated ; x %Deratingo F :VOUT + VRECT ; (23) For a good Schottky diode with 100-V reverse rating, VREV(rated), the rectifier forward voltage drop, VRECT, can be expected to be in the range of 0.4 V to 0.5 V at 3 A to 5 A, at practical operating temperatures in the region of 100C. Allowing an 85% derating on the rectifier reverse voltage stress, Equation 23 indicates a required turns ratio of 5.734 for a maximum AC peak voltage of 373 V (264 VRMS). Choose the bias winding turns ratio to set the nominal bias voltage for the device VDD pin. Use an initial VBIAS(target) of 12 V. NB VBIAS:target ; + VF = NS :VOUT + VRECT; where * VF is the forward voltage drop of the rectifier on the bias winding. (24) For a typical 0.7-V bias-diode drop, this equation calculates to 0.6366. When the transformer size and type are chosen, the actual turns values can be calculated. Because the turns need to be rounded to integer values, the actual turns ratios achieved deviates from these targets. Check the final ratios to ensure that the secondary-side Schottky rectifier stress and the bias winding nominal level are acceptable. Adjust the specific turns counts to meet the target ratios. 9.2.4.4 Transformer Magnetizing Inductance Match the power stage design to the modulator curves by ensuring that the boundary conduction mode (BCM - boundary of operation between DCM and CCM) point coincides with the minimum bulk-capacitor voltage at minimum line, at rated output power. This choice results in DCM operation at all line voltages for all loads up to continuous rated load, and minimizes power loss and EMC impacts due to output rectifier reverse recovery during CCM operation. This design choice allows operation to extend into the CCM region of operation as required to deliver the transient peak load. To achieve this design target, the required primary magnetizing inductance, LPRI is calculated from Equation 25. In this equation, the value of FSW(nom) is 60 kHz, taken from the modulator curve region P3 to P4, in Table 5. The value of VBULK(min) is the value that occurs with the actual used bulk capacitance of 127 F. 1 LPRI = 2 P 1 1 2 x @ RATED A x L + M x fSW:nom ; VBULK:min ; NP D x :VOUT +VRECT ; NS (25) This calculates a value of 257 H. Round the value to 260 H. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 57 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 9.2.4.5 Current Sense Resistor RCS In addition to choosing LPRI value to map the rated power to the target BCM point at minimum bulk voltage, choose the RCS value according to Equation 26. This calculation ensures that the resulting peak current, in conjunction with the chosen value of magnetizing inductance, and the 60-kHz modulator frequency, delivers the required input power to meet the rated output load power, at minimum bulk voltage ripple. R CS = 2x @ VCS:bcm ; PRATED 1 1 AxL + M VBULK:min ; NP D x :VOUT + VRECT ; NS where * VCS(bcm) is the modulator peak-current sense level at point P4 (640 mV) (26) This equation calculates a value of 207 m. Use the nearest standard E24 value of 200 m. 9.2.4.6 Transformer Constraint Verification As outlined in Magnetic Sensing: Power Stage Design Constraints, there are constraints on the ratio of RCS/LPRI to ensure the design is consistent with the required volt-seconds for output sampling at minimum load, and with the controller tON(min) at high line. Per Equation 15 and Equation 16, limit the ratio of RCS/LPRI. VCS:min ; RCS NS 1 172 mV 6 1 Q x x = x x :VOUT + VRECT; say Js LPRI NP tOUT:smp ; 34 :19.5 V + 0.4 V; {rr (27) and, VCS:min ; 1 172 mV R CS Q x = VIN:pk _max ; LPRI t ON:min ; 373 V x 0.6 Js yyr (28) In this case, the ratio equates to 769, so both constraints are met. 58 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 9.2.4.7 Transformer Selection and Design After determining the value of current sense resistor RCS, determine the maximum peak current at maximum demand point on the modulator. Accommodate for the IPEAK adjustment for frequency dithering. Use this value when calculating the margin for core saturation. In this case, IPK(sat) calculates to 4.13 A. IPK:sat ; = VCS:max ; x 3/4106.7% RCS (29) In subsequent calculations of required primary turns etc, the average maximum peak current, IPK(max) , during the frequency dither period should be used, which calculates to 4.0 A. IPK:max ; = VCS:max ; R CS (30) Knowing IPK(max), LPRI and the turns ratio, the choice of transformer size and core shape and type dictates the required number of primary, secondary and bias turns, and the size of the air-gap. Various trade-offs, design preferences, and transformer design targets (size, cost, target losses, etc.) influence the specific choice of transformer core in any given design. In the case of the UCC28630EVM-572 (PWR572 EVM), core area-product geometry was used to choose the minimum core size available to meet the power level. The core geometry factor Kg is a figure-of-merit that reflects the core power capability, in terms of its physical size, shape and design. It combines the core effective cross-sectional area, Ae, winding window area, Aw, and the mean length per turn (MLT) of wire around the core. KG = Ae 2 x AW MLT (31) Estimate the required design core geometry, KG(des), using the required transformer inductance LPRI, maximum peak current IPK(max), allowed maximum core flux density Bmax and a target copper loss budget, PCU. K G:des ; = LPRI 2 x IPK:sat ; 2 x ITOT 2 x OCU Bmax 2 x K U x PCU where * * cu is the resistivity of Copper (approximately 1.7 x 10-8 m at room temperature, 2.2 x 10-8 m at 100C), Ku is a winding window utilization factor that accounts for the percentage of the window that is occupied by Copper (32) Ku can often be as low as 25%, due to the fill factor (gaps between wires), wire insulation (especially for tripleinsulated wire), and the need for insulating tapes and EMC shielding layers. The estimate of the required core geometry needs an estimate of the aggregate total winding current ITOT. The analysis models the flyback transformer primary and secondary windings as a single lumped non-isolated inductor (such as a single winding buck inductor), only for the purpose of sizing the required core winding window to achieve the target copper loss. In this case, the secondary-side current amplitude reflects to the primary side so that aggregate total primary current. ITOT can be estimated in Equation 33. d ITOT = IPK x dW3 + IPK x SECW3 where * * d is the primary on-time duty cycle dSEC is the secondary-side flyback period duty cycle (33) At rated power and minimum bulk capacitor voltage, the inductance LPRI has been chosen to achieve boundarymode conduction, therefore the duty cycle is given in Equation 34. d= NP x :VOUT + VRECT ; NS FVBULK:min ; + NP x :VOUT + VRECT;G NS (34) and dSEC = 1 F d (35) Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 59 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com At the boundary conduction point, the primary peak current IPK is at the level set by the modulator, VCS(bcm). So from Equation 33, ITOT becomes Equation 36. ITOT = VCS:bcm ; 3/43R CS I NP x :VOUT +VRECT ; VBULK:min ; I N NS x I + N (c) NP NP I FVBULK:min ; + x :VOUT +VRECT ;G FVBULK:min ; + x :VOUT +VRECT ;GN NS NS I O (36) Equation 36 calculates ITOT as 2.6 A. Thus the required design KG(des), assuming KU of 25%, Bmax of 315 mT and a target of 1-W copper loss, is shown in Equation 37. K G:des ; = txr JH2 x 4.132 x 2.62 x 2.2 x 10-8 0.3152 x 0.25 x 1.0 (37) -12 Equation 37 indicates that this design requires a core size and shape with a KG of more than 6.9 x 10 . A review of commonly used cores indicated that the RM10/I core set meets this requirement. With Ae of 96.6 mm2, Aw of 44.2 mm2 and mean length per turn (MLT) of 52 mm, KG(RM10) is 7.9 x 10-12, giving some margin over the design target. KG:RM10 ; = (96.6 x 10-6 )2 x (44.2 x 10-6 ) = 7.932 x 10-12 (52 x 10-3 ) (38) With the chosen core, the actual primary, secondary-side and bias turns can be calculated. The required primary turns depend on the allowed Bmax. For most power ferrites, a value in the region of 315 mT is commonly used. NP = LPRI x IPK:max ; txr J x 4.0 = = 34.18 0.315 x 96.6 J Bmax x Ae (39) Round NP to 34. Now the required secondary-side turns can be calculated, using the previously calculated turns ratio per Equation 23. NS = NP = 5.93 5.734 (40) Again, NS is rounded to 6. Due to the integer rounding of the turns count, ensure that the actual turns ratio is within 5% of original target (if outside this range, secondary-side rectifier or primary MOSFET stress may be too high). NP NS = 98.8% 5.734 (41) From Equation 24, the required bias turns can be calculated using Equation 42. NB = VBIAS:target ; + VF 12 + 0.7 x NS = x 6 = 3.82 :VOUT + VRECT ; 19.5 + 0.45 (42) Again, NB is rounded to 4. The effect of integer scaling in the turns is verified by calculating the expected bias voltage versus target. VBIAS = :VOUT + VRECT; x 4 NB F VF=:19.5 + 0.45; x F 0.7 = 12.6 V 6 NS (43) The VBIAS target was 12 V, so this is acceptable. The required core inductance factor, AL, to achieve the target inductance can be calculated as in Equation 44. The transformer manufacturer uses this factor to gap the core center leg. AL = 60 LPRI NP 2 = txrJ = 225 nH 342 Submit Documentation Feedback (44) Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Finally, calculate the required air-gap length lg, based on the required inductance and the core geometry. lg = NP2 x J0 x ACENTRE lm F LPRI Jr where * * * * 0 is the permittivity of free-air r is the relative permeability of the chosen core ferrite material ACENTRE is the cross-sectional area of the core center leg lm is the core average magnetic path length (45) For the RM10/I core in 3C95 material (chosen for low core loss over a wide temperature range), the required airgap length is calaulated using Equation 46. lg = 342 x vN x 10-7 x 93.3 J 44.6 m F L wsv Jm txr J 5500 (46) Typically, the air-gap calculation in Equation 45 underestimates lg, due to flux fringing in the air-gap. The fringing causes the affective area of the air-gap Ag to be somewhat larger than the ferrite core center leg ACENTRE, depending on the gap length. This difference requires an increase in the required air-gap length to get the required inductance, which results in a further increase in fringing. However use Equation 45 to determine an initial value for lg, which can then be used to estimate Ag. For round centre legs, the increase in effective area within the gap can be estimated empirically from Equation 47 Ag = ACENTRE x F1+ lg DCENTRE 2 G L {uau J x l1+ 0.514 2 p = 102.31 mm2 10.9 where * DCENTRE is the center leg diameter (47) (For more information about this subject, download the paper Inductor and Flyback Transformer Design, Lloyd Dixon, TI Power Supply Design Seminar SLUP127). Because Equation 45 assumes that Ag equals ACENTRE, it must be modified using Equation 48. lg = F NP 2 x J0 x Ag Ag lm G F l x p LPRI Jr Ae (48) Re-iterating the air-gap calculation in Equation 49 . 342 x vN x 10F7 x 102.31 J 44.6 m 102.31 J lg = F G Fl x p L wxuar Jm 260 J 5500 96.6 J (49) Typically, after the second iteration above in Equation 48, the estimated air-gap is very close to the required value. Further iterations can be made, but should not be necessary. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 61 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 9.2.4.8 Slope Compensation Verification After choosing the current sense resistor, transformer inductance and transformer turns ratio, verify the required slope compensation against the fixed internal slope compensation. The worst case slope compensation requirement always occurs at the highest duty cycle operating point (at minimum bulk voltage level). For stability, the slope compensation should be at least 50% of the difference between the inductor up-slope and down-slope. [reference Bob Mammano TI Power Supply Design Seminar paper, 2001, SLUP173]. For a flyback converter, the difference in slopes in CCM is equal the operating duty cycle multiplied by the inductor current down-slope value. For example, for 50% dBULK(min) at minimum bulk capacitor voltage, the required slope compensation ramp is 25% of the inductor current down-slope. As listed in Table 7, the specified peak-load transient is 130 W for 2 ms. In a worst case, peak transient timing with respect to the AC phase, the VBULK minimum level dips to 65 V. This corresponds to a duty cycle of approximately 63.5% according to Equation 50. dBULK:min ; = NP x :VOUT + VRECT ; NS N FVBULK:min ; + P x :VOUT + VRECT ;G NS = 346 x :19.95; = 63.5% :65 + 346 x :19.95;; (50) The required slope compensation ramp is calculated at 63.5% duty cycle. NS x :VOUT + VRECT; 346 x 19.95 NP VCS (slope ) = 50% x dBULK:min ; x RCS x n r = 0.5 x 0.635 x 0.2 x F G = 27.6 mV/Js LPRI txr J (51) This value is within the 30 mV/s of internal slope compensation provided by the controller. 9.2.4.9 Power MOSFET and Output Rectifier Selection The initial design target proposed the use of a 100-V Schottky rectifier. The secondary-side reverse voltage stress can be verified using the final transformer design sh own in Equation 52. NS 6 VRECT:rev ; = l x VAC:pk _max ;p + :VOUT + VRECT; = x 373 + 19.95 = 85.8 V 34 NP (52) The value derived from Equation 52 is close to the original design target of 85 V. For 65-W load, the average DC output current is 3.35 A for 19.5-V output. However, to reduce losses, a much higher current rated diode is typically used, to yield a much lower forward voltage drop VRECT. As shown in Figure 44, a 30-A rated diode D7 is used in this case, with a forward drop of approximately 0.45 V at 3.5 A, 100C. For the primary-side MOSFET, the peak voltage stress can be estimated using Equation 53. VDS:max ; = VAC:pk _max ; + NP 34 x :VOUT + VRECT ; = 373 + x 19.95 = 486 V 6 NS (53) An allowance of at least 100 V must be added to this figure to account for the leakage inductance spike at turnoff. This voltage spike depends on the transformer implementation and the amount of leakage inductance, as well as the specific design of the snubber. A more aggressive snubber may reduce the voltage spike, but at the expense of higher losses in the snubber. A voltage rating of at least 600 V is recommended for the power MOSFET to allow for leakage. The MOSFET rms current at low line, rated load, can be estimated using Equation 54. IPRI:rms ; = VCS:bcm ; 3/43RCS NP x :VOUT + VRECT; NS 0.64 x = x 3/40.58 = 1.41 A N 3/43(R)0.2 FVBULK:min ; + P x :VOUT + VRECT ;G NS (54) As can be seen in Figure 44, the chosen MOSFET Q1 is a 13-A, 600-V device. 62 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 9.2.4.10 Output Capacitor Selection Select the output capacitor value on the basis of one of the following, depending on which one is the limiting factor: * Required ripple current rating to absorb the high secondary-side peak current * Required esr to achieve a target peak-peak ripple voltage * Required holdup capacitance to achieve target minimum output voltage for a specified load transient from no load when the device is switching at fSW(min) For flyback converters, ripple current rating often dictates the output capacitance value. The required ripple current rating can be calculated from Equation 55. 2 3 3 3 3 C E 3 VBULK:min ; VCS:bcm ; 3 NP E E FI 2 3 ICAP:rms ; =3E x x OUT E NS 3 E R CS E NP 3 3 x mVBULK:min ; + F x :VOUT + VRECT ;Gq 3 NS 3 I aE (55) At rated 65-W load, ICAP(rms) = 5.9 ARMS. Capacitors C11 and C13 in Figure 43 are chosen to meet this ripple requirement, (each capacitor has a 2.5-A minimum rating at 105C). Total output capacitance is 1360 F. 9.2.4.11 Calculation of CC Mode Limit Point Calculate the expected output constant-current (CC) limit point from Equation 20. As previously noted, KCC1 is 44.5 and KCC1 is 69.5. Thus, IOUT(lim) in this case is approximately calculated in Equation 56. IOUT:lim ; = 1 NP KCC1 1 34 44.5 x x = x x = 7.0 A NP 34 RCS 0.2 6 NS KCC2 + VOUT x A 69.5 + @19.5 x NS 6 Copyright (c) 2014-2017, Texas Instruments Incorporated (56) Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 63 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 9.2.4.12 VDD Capacitor Selection Size the VDD capacitor to supply sufficient IDD(run) current to the device during initial start-up, and also during the charging phase of the main output capacitors. During the charging phase the bias winding on the transformer must supply the bias power. When VDD reaches the VDD(start) threshold, the device consumes IDD(run) for tSTART(del) before the PWM switching commences. Thereafter, the bias current is the device current plus the MOSFET gate current. The VDD capacitor must support this higher level of current until the output is sufficiently charged that the bias winding rail has increased above the VDD(stop) level. Calculate the required bias capacitance from the total bias charge associated with the device run current during the tSTART(del) phase, plus the device run current during the output charge phase, plus the primary MOSFET gate charge current during the output charge phase. The time taken for the output charge phase to reach a sufficient level to supply the bias can be calculated from the size of the output capacitor, target output regulation voltage, and the difference between the available CC mode current limit and the maximum load current (assuming that the output capacitor has to be charged whilst also supplying full rated load current). Assume that the MOSFET is switched at 60 kHz throughout the charging phase. Combining these into one equation, the required VDD capacitor can be calculated as shown in Equation 57. CVDD= VDD:stop _max ; VOUT x COUT kIDD:run ; x tSTART:del ;o + kIDD:run ; + FSW:nom ; x Qg:tot ; o x l pxl p IOUT:lim ; F IO:max ; VBIAS:nom ; cVDD:start _min ; F VDD:stop _max ;g (57) This can be re-written with the explicit device values substituted: 8.5 VOUT x COUT : 8m x 3m;+k8m + 60 k x Qg:PKP ; o x l pxl p VBIAS:JKI ; IOUT:HEI ; F IO:I=T ; CVDD = :13.0 F 8.5; (58) For this EVM design, the MOSFET Qg(tot) is 30 nC, VBIAS(nom) is 12.6 V. IO(max) is 3.35 A, so this equates to: CVDD = 8.5 19.5 x suxrJ :8m x 3m; + :8m + 60 k x 30n; x @ Ax@ A 12.6 L sxar JF 7.0 F 3.35 :13.0 F 8.5; (59) Choose the next higher standard value, 22 F. Verify that the bias capacitance is sufficient to absorb all the X-capacitor energy when it has to be discharged, per Equation 3. From Figure 44, the value of X-capacitor is 330 nF. VAC:pk ; F VSELV 373 F 60 CVDD R CX x F G = 330 nF x l p = 15.9 JF 13 F 6.5 VDD:start _min ; F VDD:reset _max ; 64 Submit Documentation Feedback (60) Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 9.2.4.13 Magnetic Sense Resistor Network Selection The required values for the magnetic sense divider network are calculated from Equation 11 and Equation 12. For the RM10/I transformer used in the PWR572 EVM, the secondary-side to bias leakage inductance was measured and found to be approximately 4%. This figure can be reasonably estimated as the ratio of the inductance value measured across the secondary-side pins with the bias pins shorted together (primary winding should remain open-circuit), to the inductance value measured across the secondary-side pins with all other windings open: %LLK:sec _bias ; = LSEC:bias _short ; LSEC:bias _open ; (61) RA is calculated as shown in Equation 62. R A = RP x l NB 4 p x K LINE = 3.9 k3 x l p x 49.25 = 22.597 k3 34 NP (62) The nearest standard E96 value 22.6 k is selected. RB may then be calculated to set VOUT at 19.5 V. RB = RA N kVOUT x k1 F %LLK:sec _bias ; o + VRECT o x @ BWN A S L F 1M VOUT:ref ; = 22.6 k3 = 32.10 k3 :19.5 x :1 F 0.04; + 0.45; x :46; F 1p l 7.50 (63) The nearest E96 value is 32.4 k, which could be used, but results in some set-point regulation error. As shown in Figure 44, the setpoint may be fine-tuned by using two parallel resistors for RB. In this case use values of 39 k and 180 k, to give a net equivalent of 32.05 k, very close to the target value in Equation 63. Note that the pull-up diode to DRV pin should be a standard switching signal diode such as BAS21 or similar. The reverse recovery of the diode should be 100 ns or less. A slow-recovery diode clamps the VSENSE pin low for an initial portion of the flyback interval, and may impair or prevent the ability to take a valid output voltage sample. 9.2.4.14 Output LED Pre-Load Resistor Calculation As shown in Figure 44, the output power good LED1 and series resistor R18 form an output pre-load or minimum load. This pre-load is necessary in order to maintain regulation at no load, or when the power converter output is disconnected from the load system. Magnetic regulation relies on sensing the output voltage during switching cycles, so it is necessary to maintain a certain minimum switching frequency fSW(min) in order to continue sensing the output voltage. However, generating switching cycles at fSW(min) transfers energy to the output, which requires some load on the secondary-side to absorb this energy and prevent the output capacitors from being charged out of regulation. The minimum energy transferred at fSW(min) depends on the choice of magnetizing inductance LPRI and current sense resistor RCS. VCS:min ; 2 0.172 2 PPRELOAD:min ; = 0.5 x LPRI x l p x fSW:min ; = 0.5 x 260 JH x l p x 200 = 19.23 mW 0.2 R CS (64) In order to ensure that the control loop operates at a frequency above the minimum switching frequency, fSW(min) (to ensure that the loop has adjustment range up/down as required to maintain regulation), the recommended minimum pre-load is at least twice the value calculated in Equation 64. The required value of R18 can then be calculated, assuming a forward voltage drop of 1.8 V for the LED: RLED = VOUT 2 F VOUT x VLED 19.52 F 19.5 x 1.8 = = 8.97 k3 2 x P:preload _min ; 2 x 19.23m (65) Use the next lower E24 value of 8.2 k. For a design without an LED, a pre-load resistor of similar value is still required across the output voltage. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 65 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 9.2.5 External Wake Pulse Calculation at VSENSE Pin (UCC28633 Only) The typical application circuit of Figure 39 may be redrawn as a simplified equivalent circuit as shown in Figure 45. In this equivalent circuit, the capacitor CP is the total parasitic capacitance (MOSFET Coss, transformer capacitance, etc), and resistance RWAKE is the effective internal resistance of the UCC24650 WAKE pin to GND pin when the internal WAKE pull-down is active (see UCC24650 detailed datasheet specifications). If all the elements on the primary and secondary of the transformer are referred to the bias winding, this can be further simplified as in Figure 46. LP N P VOUT NS VBULK RWAKE CP NB RT VSENSE RB Figure 45. Simplified Equivalent Circuit of Wake Event with UCC24650 (NB/NS) x RWAKE RT (NB/NS) x VOUT + (NB/NP)2 x LP (NB/NP)2 x CP VSENSE RB ZLC(bias) Figure 46. Bias-Referred Simplified Equivalent Circuit of Wake Event with UCC24650 66 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Thus, knowing LP and CP, the power stage impedance ZLC(bias) (reflected to the bias winding) may be calculated from Equation 66, and the effective wake resistance can be referred to the bias winding using Equation 67. The wake pulse amplitude can be calculated from Equation 68. If CP is not known, it can be measured by observing the resonant ring period at the primary drain node, TRES, and calculating CP from Equation 69. Worst case values should be used to estimate the worst case minimum wake pulse amplitude at the VSENSE pin. It should also be noted that any filter cap on the VSENSE pin (including internal parasitic pin capacitance) adds an RC filter in conjunction with the Thevenin resistance of the VSENSE divider, RT, RB; this delays and further attenuate the wake pulse amplitude. Additionally, the internal wake comparator requires some over-drive to trip, and exhibits propagation delay that depends on the amount of overdrive. So some margin should be allowed in the wake pulse amplitude to ensure that the minimum wake pulse can adequately overdrive the internal wake comparator. A margin of at least 20% over the threshold VSENSE(wake) is recommended. 0$ 2 .2 <.%(>E=O ) = x l p %2 02 49#-' (>E=O ) = 49#-' 85'05' _9#-' (LG ) (66) 0$ 2 xl p 05 (67) <.%(>E=O ) 4$ 0$ =l p x l8176 x (1 F 9#-' %) x p x F G 4# + 4$ 05 <.%(>E=O ) + 49#-' (>E=O ) (68) 2 6NAO 1 %2 = l p x .2 2e (69) If the worst case wake pulse amplitude is too low, then the UCC24650 WAKE output can be augmented with an external PNP circuit Q1, R1 and R2, as shown in Figure 40. This circuit reduces the effective wake resistance to ground, so that a larger proportion of the output voltage appears across the transformer secondary pins when the UCC24650 WAKE activates. Using the UCC28630EVM-572, (TI Literature Number SLUUAX9) circuit parameters from Figure 44, the nominal wake pulse amplitude at the VSENSE pin can be estimated. Of course, the rectifying diode D7 in Figure 44 would need to be relocated to return end of the secondary winding (pins 10, 11) to allow UCC24650 to be deployed. From observation of the DCM ringing period, the period TRES was found to be 1.138 s. From Equation 69, CP is estimated: 6NAO 2 1 1.138a 2 1 %2 = l p x =l p x = 126 L( .2 2e 260a 2e (70) From Equation 66, the power circuit impedance is: .2 260a 0$ 2 4 2 <.%(>E=O ) = x l p = x l p = 19.9 : 126L 34 %2 02 (71) The WAKE pin resistance RWAKE can be determined form the UCC24650 datasheet; for now a nominal value of 400 is assumed. Referred to the bias winding (scaled by (NB/NS)2), this becomes 178 . Similarly WAKE% can be determined from the UCC24650 datasheet; for now, a value of 97% is assumed. From Equation 68, the wake pulse amplitude can be calculated: * Z LC bias RB * N * u VOUT u 1 'W AKE% u B u VSENSE N S (c) Z LC bias RW AKE bias (c) RA RB (c) 4 * 19 .9 * 32 .05 * u 19 .5 u 97 % u u 0.743V 6 (c) 19 .9 178 22 . 6 32 . 05 (c) (c) WAKE ( pk ) (72) In this case, the VSENSE wake pulse amplitude would be insufficient to trip the internal wake comparator. If the power stage had higher LP, or lower CP, a larger wake pulse would be produced. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 67 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Alternatively, the effective wake resistance RWAKE may be reduced by adding the PNP circuit per Figure 40. This has been verified using Q1 = FMMTA92 PNP transistor, R1= 100 and R2 = 2.2 k. A wake pulse amplitude of almost 2 VPK was produced at the VSENSE pin, giving generous margin to the internal threshold VSENSE(wake). The observed waveforms are shown in Figure 47 for a worst case 0% to 100% (65 W) load transient (where the PWM is at FMIN). The PWM is re-activated when VOUT has dropped by ~3%, rather waiting for the next timed wake-up (~5 ms later). Figure 48 shows a zoomed waveform of the wake pulsing ringing as measured on the bias winding. It can be seen that the peak level is approximately 3 VPK, which would produce a pulse of approximately 1.8 V at the VSENSE pin (scaled by VSENSE divider resistors RT and RB). As noted in Test and Debug Recommendations, the VSENSE pin should never be directly probed, doing so affects the regulation setpoint. Figure 47. Observed Output Voltage (Ch3) and Bias Winding (Ch4) (showing wake event generated by UCC24650) Figure 48. Zoom In of Wake-Pulse Ringing (observed across bias winding (ChB) generated by UCC24650) 68 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 9.2.6 Energy Star Average Efficiency and Standby Power Table 8 summarize the standby power, and Table 9 summarizes the average efficiency performance of the UCC28630EVM-572, (TI Literature Number SLUUAX9). Table 8. Standby Power Performance STANDBY POWER 115 VAC (mW) 230 VAC (mW) 57 60 Table 9. Average Efficiency Performance AVERAGE EFFICIENCY (INCLUDING OUTPUT 76-m CABLE DROP) LOAD LEVEL (%) 115 VAC (%) 230 VAC (%) 25 (16.25 W) 89.44 89.26 50 (32.5 W) 88.98 89.38 75 (48.75 W) 88.24 89.10 100 (65 W) 87.59 88.73 Average 88.6 89.1 Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 69 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 9.2.7 Application Performance Plots 70 Figure 49. Start-Up from 90-VAC, 3.35-A CC Load Figure 50. Start-Up from 230-VAC, 3.35-A CC Load Figure 51. Output Rise-Time, 90-VAC, 3.35-A CC Load Figure 52. Output Rise-Time, 230-VAC, 3.35 A CC Load Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 90 90 89 88 85 Efficiency (%) Efficiency (%) 87 86 85 84 80 75 83 82 70 115 VAC 81 230 VAC 80 0 10 20 30 40 50 60 230 VAC 65 70 Load Power (W) 115 VAC 0 1 2 3 4 5 6 Figure 53. Efficiency vs. Load/Line (cable drop included) 20 20 90 V/50 Hz 100 V/60 Hz 120 V/60 Hz 143 V/63 Hz 200 V/47 Hz 230 V/50 Hz 269 V/63 Hz 19.8 19.7 19.6 19.5 90 V/50 Hz 100 V/60 Hz 120 V/60 Hz 143 V/63 Hz 200 V/47 Hz 230 V/50 Hz 269 V/63 Hz 19.2 19.1 19 0 10 20 30 40 50 60 Output Power (W) 70 Output Voltage (V) Output Voltage (V) 19.8 19.3 8 C018 Figure 54. Zoom Light-Load Efficiency vs. Load/Line (cable drop included) 19.9 19.4 7 Load Power (W) C017 19.6 19.4 19.2 19 18.8 18.6 0 C019 Figure 55. Output Voltage Regulation vs. Line/Load (without cable drop) 10 20 30 40 50 60 70 Output Power (W) C020 Figure 56. Output Voltage Regulation vs. Line/Load (with cable drop included) 20 19 Output Voltage (V) 18 17 16 15 90 V/50 Hz 100 V/60 Hz 120 V/60 Hz 143 V/63 Hz 200 V/47 Hz 230 V/50 Hz 269 V/63 Hz 14 13 12 11 10 0 2 4 6 8 Output Current (A) 10 C021 Figure 57. CC Mode Regulation vs. Line Figure 58. Transient Step 5% to 50% Load, 115 VAC Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 71 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com Gain (dB) 25 0 50 30 40 60 20 90 15 120 10 150 5 180 0 210 5 240 10 270 15 300 20 330 25 360 10 100 Frequency (Hz) Submit Documentation Feedback 60 120 10 150 180 0 210 240 270 300 30 330 40 360 10 C022 30 90 20 1000 0 20 10 Figure 61. Measured Control Loop Gain/Phase at 300 VDC, Full Load 3.35 A 72 Gain Phase 30 Gain (dB) Gain Phase 30 Phase() 35 Figure 60. Transient Step 10% to 90% Load, 115 VAC Phase() Figure 59. Transient Step 50% to 100% Load, 115 VAC 100 Frequency (Hz) 1000 C023 Figure 62. Measured Control Loop Gain/Phase at 300 VDC, Light Load 0.2 A Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 9.3 Dos and Don'ts 9.3.1 Test and Debug Recommendations One important precaution must be noted during test and debug. Do not probe the VSENSE pin with an oscilloscope probe, meter or differential probe. Doing so adds excessive capacitance to the pin, delaying the pin rise-time, and causing the regulated system output voltage to increase. 10 Power Supply Recommendations The VDD power pin for the device requires the placement of low-esr noise-decoupling capacitance as directly as possible from the VDD pin to the GND pin. Ceramic capacitors with stable dielectric characteristics over temperature are recommended, such as X7R or better. Depending on the operating temperature range of the application, X5R may be acceptable, but the drop in capacitance value at high temperature and with applied DCbias may not be tolerable. Avoid dielectrics with poor temperature-stability. (such Y5V, Z5U) The recommended decoupling capacitors are a 1-F 1206-sized 50-V X7R capacitor, ideally with (but not essential) a second smaller parallel 100-nF 0603-sized 50-V X7R capacitor. Higher voltage rating parts can also be used. The use of 25-V rated parts is not recommended, due to the reduction in effective capacitance value with applied DC bias. In parallel with the ceramic noise-decoupling capacitor(s), a larger-capacitance energy storage capacitor is also required, per Equation 58. This energy-storage capacitor does not require low esr, and does not necessarily need to be located close to the device. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 73 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 11 Layout 11.1 Layout Guidelines 11.1.1 HV Pin * This pin is connected to the rectified AC input, and as such requires appropriate separation to other PCB traces to meet the application requirements for functional isolation; * This pin must have 200 k of external resistance to allow the line voltage to be sensed for the X-capacitor discharge block. At least two series resistors should be used to reduce the voltage across the pins of each resistor, with each resistor rated for at least 200 V; * The connection to the resistors that feed the HV pin should have separate dedicated rectifying diodes from the AC input lines, to avoid the DC filtering that the bulk capacitor provides after the main diode bridge; the lower section of the main diode bridge can be shared by the device and the power stage; * A filtering or noise-decoupling capacitor is not recommended, such a capacitor will degrade the X-capacitor sampling ability to distinguish AC from DC input. 11.1.2 VDD Pin * A 1-F ceramic decoupling capacitor is recommended, placed as close as possible between the VDD pin and GND, tracked directly to both pins. 11.1.3 VSENSE Pin * The tracking and layout of the VSENSE pin and connecting components is critical to minimizing noise pick-up and interference in the magnetic sensing block. (See Figure 63 for suggested component placement and tracking). Reduce the total surface area of traces on the VSENSE net to a minimum. * Because the resistance values of RA and RB are relatively high to minimize power dissipation, the high impedance makes the VSENSE pin potentially noise-sensitive. To minimize noise pick-up, locate resistors RA and RB as close as possible to the VSENSE pin, with RB in particular placed as directly as possible between VSENSE and GND pins; * Depending on layout, a small noise filter capacitor may be useful on the VSENSE pin, such as C15 shown in Figure 44. Connect this capacitor as directly as possible between the VSENSE and GND pins. Choose the value of this capacitor as small as possible, and no greater than 10 pF. A larger value significantly delays the voltage rise-time at the pin, and affects the regulation set-point; * In case of possible board faults that can pull the VSENSE pin below GND (such as R7 shorted), in order to protect the pin and limit possible negative current out of the pin, a series resistor R4 (as shown in Figure 44) and clamping diode from GND are recommended. Maintain the value of R4 between 100 and 500 . A larger value may affect regulation and line sense accuracy. * For correct line sense operation, the switched pull-up R10 and D4 must be added. The value of R10 must be 3.9 k to match the internal device gain. The switched pull-up diode and the GND clamping diode can be combined into a dual-diode common-cathode package, such as D4 as shown in Figure 44. 11.1.4 CS Pin * A small, external filter capacitor is recommended on the CS pin. Track the filter capacitor as directly as possible from the CS to GND pin. * Referring to Figure 44, a series resistor such as R5 is typically connected between the current sensing resistor R16 and the CS pin to form an R-C filter. A filter time constant between 100 ns and 200 ns is recommended. If the filter time constant is made too large, the filtering causes the transformer peak current to exceed the control loop demand level, which affects regulation and standby power. Place resistor R5 as close as possible to the CS pin. * Reduce the total surface area of traces on the CS net to a minimum. 74 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Layout Guidelines (continued) 11.1.5 SD Pin * Referring to Figure 44, the SD pin is connected to a temperature-sensing NTC RT1 in series with an adjust resistor R6. The NTC can be tracked to the required hot-spot location, or it can be wired with flying leads to the required hotspot. * Track the RT1 return to GND as directly as possible back to the GND pin of the device. RT1 should not be connected to a power GND track or plane, in order to minimize error in the trip level. * The device internally filters the SD pin, so an external filter capacitor is not usually required. If the application design requires an external capacitor, limit the value to 1 nF maximum. 11.1.6 DRV Pin * The DRV pin has high internal sink/source current capability. An external gate resistor is recommended. The value depends on the choice of power MOSFET, efficiency and EMI considerations. * As shown in Figure 44 an anti-parallel path formed by D5 and R13 are placed across the gate resistor R11 to allow turn-on and turn-off of the MOSFET to be independently adjusted. * A pull-down resistor (such as R15 in this example) on the gate of the external MOSFET is recommended to prevent the MOSFET gate from floating on if there is an open circuit error in the gate drive path. The value of R15 also affects the overload timer settings, so carefully choose the value of R15 according to Table 1. * Ensure that the noisy gate drive traces are routed away from the sensitive VSENSE pin and CS pin traces. 11.1.7 GND Pin * Connect decoupling and noise filter capacitors, as well as sensing resistors directly to the GND pin in a starpoint fashion, ensuring that the current-carrying power tracks (such as the gate drive return) are track separately to avoid noise and ground-drops that could affect the analogue signal integrity. 11.2 Layout Example RA To Bias winding UCC28630 ~100 Q VSENSE RB1 RB2 HV G10 pF SD G120 pF CS VDD GND DRV 3.9 lQ 100 nF 1 F To DRV pin Jumper/ link To CS resistor Figure 63. Recommended PCB Layout for Single-Sided Assembly Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 75 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.1.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the UCC2863x device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 12.2 Documentation Support 12.2.1 Related Documentation UCC28630EVM-572, 65-W Nominal, 130-W Peak, Primary-Side Regulated Adapter Module (Texas Instruments Literature Number SLUSAX9) 12.2.1.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 10. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY UCC28630 Click here Click here Click here Click here Click here UCC28631 Click here Click here Click here Click here Click here UCC28632 Click here Click here Click here Click here Click here UCC28633 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. 76 Submit Documentation Feedback Copyright (c) 2014-2017, Texas Instruments Incorporated Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 UCC28630, UCC28631 UCC28632, UCC28633, UCC28634 www.ti.com SLUSBW3D - MARCH 2014 - REVISED DECEMBER 2017 Community Resources (continued) Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2014-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 77 PACKAGE OPTION ADDENDUM www.ti.com 18-Jan-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) UCC28630D ACTIVE SOIC D 7 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28630 UCC28630DR ACTIVE SOIC D 7 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28630 UCC28631D ACTIVE SOIC D 7 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28631 UCC28631DR ACTIVE SOIC D 7 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28631 UCC28632D ACTIVE SOIC D 7 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28632 UCC28632DR ACTIVE SOIC D 7 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28632 UCC28633D ACTIVE SOIC D 7 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28633 UCC28633DR ACTIVE SOIC D 7 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28633 UCC28634D ACTIVE SOIC D 7 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28634 UCC28634DR ACTIVE SOIC D 7 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28634 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Jan-2018 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Jan-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC28630DR SOIC D 7 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC28631DR SOIC D 7 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC28633DR SOIC D 7 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC28634DR SOIC D 7 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Jan-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC28630DR SOIC D 7 2500 367.0 367.0 35.0 UCC28631DR SOIC D 7 2500 367.0 367.0 35.0 UCC28633DR SOIC D 7 2500 367.0 367.0 35.0 UCC28634DR SOIC D 7 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0007A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 8 1 .100 [2.54] 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X .050 [1.27] 4 5 B 7X .012-.020 [0.31-0.51] .010 [0.25] .150-.157 [3.81-3.98] NOTE 4 C A B .069 MAX [1.75] .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4220728/A 01/2018 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0007A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 7X (.061 ) [1.55] SYMM SEE DETAILS 1 8 7X (.024) [0.6] 4X (.050 ) [1.27] SYMM (.100 ) [2.54] 5 4 (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220728/A 01/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0007A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 7X (.061 ) [1.55] SYMM 1 8 7X (.024) [0.6] 4X (.050 ) [1.27] SYMM (.100 ) [2.54] 5 4 (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4220728/A 01/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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