NOTE: This product has been replaced with UT28F256QLE or
SMD 5962-96891 device types 09 and 10.
2
Standard Products
UT28F256QL Radiation-Hardened 32K x 8 PROM
Data Sheet
June 2005
www.aeroflex.com/radhard
FEATURES
Programmable, read-only, asynchronous, radiation-
hardened, 32K x 8 memory
- Supported by industry standard programmer
45ns and 40ns maximum address access time (-55 oC to
+125 oC)
TTL compatible input and TTL/CMOS comp atible output
levels
Three-state data bus
Low operating and standby current
- Operating: 80mA maximum @25MHz
Derating: 3mA/MHz
- Standby: 1.5mA maximum (post-rad)
Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883, Method 1019
- Total dose: 100Krad to 1Megarad(Si)
- LETTH(0.25) ~ 57 MeV-cm2/mg
- SEL Immune >110 MeV-cm2/mg
- No upsets >70 MeV-cm2/mg
QML Q & V compliant part
- AC and DC testing at factory
No post program conditioning
Packaging options:
- 28-lead 50-mil center flatpack (0.490 x 0.74)
VDD: 5.0 volts + 10%
Standard Microcircuit Drawing 5962-96891
PRODUCT DESCRIPTION
The UT28F256QL amorphous silicon ViaLinkTM PROM is a
high performance, asynchronous, radiation-hardened,
32K x 8 programmabl e memory device. The UT28F256 QL
PROM features fully asychronous operation requiring no
external clocks or timing strobes. An advanced radiation-
hardened twin-well CMOS process technology is used to
implement the UT28F256QL. The combination of radiation-
hardness, fast access time, and low power consumption make the
UT28F256QL ideal for high speed systems designed for
operation in radiation environments.
DECODER MEMORY
ARRAY
SENSE AMPLIFIER
PROGRAMMING
CONTROL
LOGIC DQ(7:0)
A(14:0)
CE
PE
OE
Figure 1. PROM Block Diagram
3
DEVICE OPERATION
The UT28F256QL has three control inputs: Chip Enable (CE),
Program Enable (PE ), and Output Enable (OE); fifteen address
inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). CE
is the device enable input that controls chip selection, active, and
standby modes. Asserting CE causes IDD to rise to its active value
and decodes the fifteen address inputs to select one of 32,768
words in t he memory. PE controls program an d read operations.
During a read cycle, OE must be asserted to enable the outputs.
PIN NAMES
Table 1. Device Operation Truth Table 1
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
ABSOLUTE MAXIMUM RATINGS 1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
2. Test per MIL-STD-883, Method 1012, infinite heat sink.
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
V
DD
PE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A(14:0) Address
CE Chip Enable
OE Output Enable
PE Program Enable
DQ(7:0) Data Input/Data Output
OE PE CE I/O MODE MODE
X 1 1 Three-state Standby
0 1 0 Data Out Read
100 Data In Program
1 1 0 Three-state Read 2
SYMBOL PARAMETER LIMITS UNITS
VDD DC supply voltage -0.3 to 6.0 V
VI/O Voltage on any pin -0.5 to (VDD + 0.5) V
TSTG Storage temperature -65 to +150 °C
PDMaximum power dissipatio n 1.5 W
TJMaximum junction temperature +175 °C
ΘJC Thermal resistance, junction-to-case 23.3 °C/W
IIDC input current
±
10 mA
4
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 5.0V
±
10%; -55°C < TC < +125°C)
Notes:
* Post-radiation pe rfo rm ance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si).
1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Derates at 3.2mA/MHz.
SYMBOL PARAMETER LIMITS UNITS
VDD Positive supply voltage 4.5 to 5.5 V
TCCase temperature range -55 to +125 °C
VIN DC input voltage 0 to VDD V
SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM UNIT
VIH High-level input voltage (TTL) 2.4 V
VIL Low-level input voltage (TTL) 0.8 V
VOL1 Low-level output voltage IOL = 4.0mA, VDD = 4.5V (TTL) 0.4 V
VOL2 Low-level output voltage IOL = 200µA, VDD = 4.5V (CMOS) VSS + 0.10 V
VOH1 High-level output voltage IOH = -200µA, VDD = 4.5V (CMOS) VDD -0.1 V
VOH2 High-level output voltage IOH = -2.0mA, VDD = 4.5V (TTL) 2.4 V
CIN 1Input capacitance , all inputs
except PE
Input Capacitance PE
ƒ = 1MHz, VDD = 5.0V
VIN = 0V
15
20
pF
CIO 1 Bidirectional I/O capacitance ƒ = 1MHz, VDD = 5.0V
VOUT = 0V
15 pF
IIN Input leakage current VIN = 0V to VDD, all pins except PE
VIN = VDD, P E only
-5 +5
132 µA
µA
IOZ Three-state output leakage
current VO = 0V to VDD
VDD = 5.5V
OE = 5.5V
-20 20 µA
IOS 2,3 Short-circuit output current VDD = 5.5V, VO = VDD
VDD = 5.5V, VO = 0V -120 120 mA
mA
IDD1(OP)5Supply current operating
@25.0MHz (40ns product)
@22.2MHz (45ns product)
TTL inputs levels (IOUT = 0), VIL =
0.2V
VDD, PE = 5.5V 80
75 mA
mA
IDD2(SB)
post-rad Supply current standby CMOS input levels VIL = VSS +0.25V
CE = VDD - 0.25 VIH = VDD - 0.25V 1.5 mA
5
READ CYCLE
A combination of PE greater than VIH(min), and CE less than
VIL(max) defines a read cycle. Read access time is measured
from the latter of device enable, output enable, or valid address
to valid data output.
An address access read is initiated by a change in address inputs
while the chip is enabled with OE asserted and PE deasserted.
Valid data appears on data output, DQ(7:0), after the specified
tAVQV is satisfied. Outputs remain active througho ut the ent ire
cycle. As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum read
cycle time.
The chip enable-controlled access is initiated by CE going active
while OE remains asserted, PE remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
tELQV is satisfied, the eight-bit word addressed by A(14:0)
appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active
while CE is asserted, PE is deasserted, and the addresses are
stable. Read access time is tGLQV unless tAVQV or tELQV have
not been satisfied.
AC CHARACTERISTICS READ C YCLE (Post-Radiation)*
(VDD = 5.0V
±
10%; -55°C < TC < +125°C)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads (Si).
1. Functional test.
2. Three-state is defined as a 200mV change from steady-state output voltage.
SYMBOL PARAMETER 28F256-45
MIN MAX 28F256-40
MIN MAX UNIT
tAVAV1Read cycle time 45 40 ns
tAVQV Read access time 45 40 ns
tAXQX2Output hold time 0 0 ns
tGLQX2OE-controlled output enable time 0 0 ns
tGLQV OE-controlled access time 15 15 ns
tGHQZ OE-controlled output three-state time 15 15 ns
tELQX2 CE-controlled ou tput enable time 0 0 ns
tELQV CE-controlled access time 45 40 ns
tEHQZ CE-controlled output three-state time 15 15 ns
6
RADIATION HARDNESS
The UT28F256QL PROM incorpo rates special design and
layout features which allow operation in high-level radiation
environments. Aeroflex Colorado Springs has developed
special low-temperature processing techniques designed to
enhance the total-dose radiation hardness of both the gate oxide
and the field oxide while maintain ing the circuit density and
reliability. For transient radiation hardness and latchup
immunity, UTMC builds all radiation-hardened products on
epitaxial wafers using an advanced twin-tub CMOS process. In
addition, UTMC pays special attention to power and ground
distribution during the design phase, minimizing dose-rate upset
caused by rail collapse.
RADIATION HARDNESS DESIGN SPECIFICATIONS 1
Note:
1. The PROM will not latchup during radiation exposure under recommended operating conditions.
Figure 2. PROM Read Cycle
tAVAV
tAVQV
tELQV
tGLQV
tAVQV
tAXQX
tEHQZ
tGHQZ
A(14:0)
CE
OE
DQ(7:0) tGLQX
tELQX
Total Dose 1E6 rad(Si)
Latchup LET Threshold >110 MeV-cm2/mg
Memory Cell LET Threshold >100 MeV-cm2/mg
Logic Onset LET >57 MeV-cm2/mg
SEU Cross Section 3.1E-12 cm2/bit
Error rate - geosynchronous orbit, Adams 90% worst case environment 2.0E-20 errors/bit day
7
Notes:
1. 50pF including scope probe and test socket.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(TTL input = 1.5V).
90%
Figure 3. AC Test Loads and Input Waveforms
Input
Pulses
10%
< 5ns < 5ns
TTL
0V
3.0V
330 ohms
V
REF
=1.73V
50pF 90%
10%
8
0.015
0.008
0.015
0.008 PIN NO. 1 ID. 6
26 PLACES
0.050 BSC
e
E1
0.550 MAX
-B-
7
S1
(4) PLACES
0.000 MIN.
7
-D-
-C-
A
0.115
0.045
0.045
0.026 L
0.370
0.250
E2
0.180 MIN E3
0.030 MIN
E
0.520
0.460
-H-
c
0.009
0.004
0.040
0.022
0.015 28 PLACES
-A-
HA-B D5
SS
0.010 M
HA-B D
5
SSM
0.036
TOP VIEW
END VIEW
b
k
k
Q
Figure 5. 28-Lead 50-mil Center Flatpack (0.490 x 0.74)
Notes:
1. All exposed metalized areas to be plated per MIL-PRF-38535.
2. The lid is connected to V
SS
.
3. Lead finishes are in accordance with MIL-PRF-38535.
4. Dimension letters refer to MIL-STD-1835.
5. Lead position and coplanari ty are not measured.
6. ID mark symbol is vendor option.
7. With solder, increase maximum by 0.003.
8. Total weight is approximately 2.4 grams.
D
0.740 MAX
9
ORDERING INFORMATION
256KQL PROM: SMD
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Case Outline:
(X) = 28-lead Flatpack
Class Designator:
(Q) = Class Q
(V) = Class V
Device Type
(05) = 45ns Access T i me, TTL inputs, CMOS/TTL compatible outputs
(06) = 40ns Access T i me, TTL inputs, CMOS/TTL compatible outputs
(07) = 45ns Access Time, TTL inputs, CMOS/TTL compatible outputs Extended Indust rial Temp
(-40
c
C to +125
o
C)
(08) = 40ns Access Time, TTL inputs, CMOS/TTL compatible outputsExtended Industrial Temp
(-40
c
C to +125
o
C)
Drawing Number: 96891
Total Dose:
(F) = 3E5 rad s(Si)
(G) = 5E5 rads(Si)
(H) = 1E6 rads(Si)
(R) = 1E5 rads(Si)
Federal Stock Class Designator: No options
5962 * 96891 * * * *
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
4. Device types 07 and 08 available with total dose of 1E5 rads(Si) or 3E5 rads(Si).
10
2
56KQL PROM
UT **** *** - * * * * * *
Total Dose:
( ) = Total dose characteristics neither tested nor guaranteed
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Screening:
(C) = Mil Temp
(P) = Prototype
(W) = Ex ten de d In du strial Te m p (-40
c
C to +125
o
C)
Package Type:
(U) = 28-lead Flatpack
Access Time:
(40) = 40ns access time, TTL compatible inputs, CMOS/TTL compatible outputs
(45) = 45ns access time, TTL compatible inputs, CMOS/TTL compatible outputs
Device Type Modifier:
(T) = TTL compatible inputs and CMOS/TTL compatible outputs
Device Type:
(28F256QL) = 32Kx8 One Time Programmable PROM
N
otes:
1. Lead finish (A,C, or X) must be specified.
2
. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3
. Military Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Radiation characteristics are neither tested nor
guaranteed and may not be specified.
4
. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices have prototype assembly and are tested at 25°C only. Radiation
characteristics are neither tested nor guaranteed and may not be specified. Lead finish is gold only.
11
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Aeroflex Colorado Springs, Inc. reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
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