LM337T - Motorola / Freescale Semiconductor

MCM6729D

MOTOROLA FAST SRAM

256K x 4 Bit Fast Static Random

Access Memory

The MCM6729D is a 1,048,576 bit static random access memory organized

as 262,144 words of 4 bits. Static design eliminates the need for external clocks

or timing strobes.

Output enable (G) is a special control feature that provides increased system

flexibility and eliminates bus contention problems.

This device meets JEDEC standards for functionality and revolutionary pinout,

and is available in a 400 mil plastic small–outline J–leaded package.

•Single 5 V ±10% Power Supply

•Fully Static — No Clock or Timing Strobes Necessary

•All Inputs and Outputs Are TTL Compatible

•Three State Outputs

•Fast Access Times: 8, 10, 12 ns

•Center Power and I/O Pins for Reduced Noise

BLOCK DIAGRAM

ROW

DECODER

MEMORY

MATRIX

512 ROWS x 512 x 4

COLUMNS

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

AA A A A

VSS

A A A A

Order this document

by MCM6729D/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6729D

WJ PACKAGE

400 MIL SOJ

CASE 857A–02

VCC

VSS VCC

VSS

NC A

NC NC

A Address Input. . . . . . . . . . . . . . . . . . . . .

EChip Enable. . . . . . . . . . . . . . . . . . . . . .

WWrite Enable. . . . . . . . . . . . . . . . . . . .

GOutput Enable. . . . . . . . . . . . . . . . . . .

DQ Data Input/Output. . . . . . . . . . . . . . .

VCC + 5 V Power Supply. . . . . . . . . . . .

VSS Ground. . . . . . . . . . . . . . . . . . . . . . .

NC No Connection. . . . . . . . . . . . . . . . . .

PIN NAMES

10/9/96

 Motorola, Inc. 1996

MCM6729D

2MOTOROLA FAST SRAM

TRUTH TABLE (X = Don’t Care)

EG W Mode VCC Current Output Cycle

H X X Not Selected ISB1, ISB2 High–Z —

L H H Output Disabled ICCA High–Z —

L L H Read ICCA Dout Read Cycle

L X L Write ICCA High–Z Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating Symbol Value Unit

Power Supply Voltage VCC – 0.5 to + 7.0 V

Voltage Relative to VSS for Any Pin Except

VCC Vin, Vout – 0.5 to VCC + 0.5 V

Output Current Iout ±30 mA

Power Dissipation PD1.2 W

Temperature Under Bias Tbias – 10 to + 85 °C

Operating Temperature TA0 to + 70 °C

Storage Temperature — Plastic Tstg – 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could af fect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply V oltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V

Input High Voltage VIH 2.2 — VCC + 0.3** V

Input Low Voltage VIL – 0.5*— 0.8 V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, V in = 0 to VCC) Ilkg(I) —±1.0 µA

Output Leakage Current (E = VIH, Vout = 0 to VCC) Ilkg(O) —±1.0 µA

Output Low Voltage (IOL = + 8.0 mA) VOL —0.4 V

Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V

POWER SUPPLY CURRENTS

Parameter Symbol 6729D–8 6729D–10 6729D–12 Unit Notes

AC Active Supply Current (Iout = 0 mA) (VCC = max, f = fmax) ICCA 195 165 155 mA 1, 2, 3

Active Quiescent Current (E = VIL, VCC = max, f = 0 MHz) ICC2 90 90 90 mA

AC Standby Current (E = VIH, VCC = max, f = fmax) ISB1 60 60 60 mA 1, 2, 3

CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V,

Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V) ISB2 20 20 20 mA

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).

2. All addresses transition simultaneously low (LSB) and then high (MSB).

3. Data states are all zero.

This device contains circuitry to protect the in-

puts against damage due to high static voltages

or electric fields; however, it is advised that nor-

mal precautions be taken to avoid application of

any voltage higher than maximum rated volt-

ages to these high–impedance circuits.

This BiCMOS memory circuit has been de-

signed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established. The circuit is in a test

socket or mounted on a printed circuit board

and transverse air flow of at least 500 linear feet

per minute is maintained.

MCM6729D

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter Symbol Typ Max Unit

Address Input Capacitance Cin — 6 pF

Control Pin Input Capacitance Cin — 6 pF

Input/Output Capacitance CI/O — 8 pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ±10%, TA = 0 to +70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE TIMING (See Notes 1 and 2)

6729D–8 6729D–10 6729D–12

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle T ime tAVAV 8 — 10 — 12 — ns 3

Address Access Time tAVQV — 8 — 10 — 12 ns

Enable Access T ime tELQV — 8 — 10 — 12 ns

Output Enable Access T ime tGLQV — 4 — 5 — 6 ns

Output Hold from Address Change tAXQX 3 — 3 — 3 — ns

Enable Low to Output Active tELQX 3 — 3 — 3 — ns 4,5,6

Output Enable Low to Output Active tGLQX 0 — 0 — 0 — ns 4,5,6

Enable High to Output High–Z tEHQZ — 4 — 5 — 6 ns 4,5,6

Output Enable High to Output High–Z tGHQZ — 4 — 5 — 6 ns 4,5,6

NOTES:

1. W is high for read cycle.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from

device to device.

5. T ransition is measured 200 mV from steady–state voltage with load of Figure 1b.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E = VIL, G = VIL).

8. Addresses valid prior to or coincident with E going low.

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.5 V

(a) (b)

5 pF

+5 V

OUTPUT

255

Ω

480

Ω

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time. On the other hand, responses

from the memory are specified from the de-

vice point of view. Thus, the access time is

shown as a maximum since the device never

provides data later than that time.

TIMING LIMITS

Figure 1. AC Test Loads

MCM6729D

4MOTOROLA FAST SRAM

READ CYCLE 1 (See Note 7)

Q (DATA OUT)

A (ADDRESS)

DATA VALIDPREVIOUS DATA V ALID

tAVAV

tAXQX

tAVQV

READ CYCLE 2 (See Note 8)

tEHQZ

DATA VALID

tGHQZ

tAVAV

tELQX

tELQV

E (CHIP ENABLE)

Q (DATA OUT)

A (ADDRESS)

tAVQV

tGLQX

tGLQV

G (OUTPUT ENABLE)

MCM6729D

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

6729D–8 6729D–10 6729D–12

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Time tAVAV 8 — 10 — 12 — ns 3

Address Setup T ime tAVWL 0 — 0 — 0 — ns

Address Valid to End of Write tAVWH 8 — 9 — 10 — ns

Address Valid to End of Write,

G High tAVWH 7 — 8 — 9 — ns

Write Pulse Width tWLWH,

tWLEH 8 — 9 — 10 — ns

Write Pulse Width, G High tWLWH,

tWLEH 7 — 8 — 9 — ns

Data Valid to End of Write tDVWH 4 — 5 — 6 — ns

Data Hold T ime tWHDX 0 — 0 — 0 — ns

Write Low to Data High–Z tWLQZ — 4 — 5 — 6 ns 4,5,6

Write High to Output Active tWHQX 3 — 3 — 3 — ns 4,5,6

Write Recovery Time tWHAX 0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. T ransition is measured 200 mV from steady–state voltage with load of Figure 1b.

5. This parameter is sampled and not 100% tested.

6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.

WRITE CYCLE 1

DATA VALID

tDVWH

tAVWL

tAVWH

tAVAV

tWHAX

tWLWH

tWHDX

tWLQZ

tWHQX

HIGH–Z HIGH–Z

A (ADDRESS)

W (WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

tWLEH

MCM6729D

6MOTOROLA FAST SRAM

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)

6729D–8 6729D–10 6729D–12

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write Cycle Time tAVAV 8 — 10 — 12 — ns 3

Address Setup T ime tAVEL 0 — 0 — 0 — ns

Address Valid to End of Write tAVEH 7 — 8 — 9 — ns

Enable to End of Write tELEH,

tELWH 7 — 8 — 9 — ns 4,5

Data Valid to End of Write tDVEH 4 — 5 — 6 — ns

Data Hold T ime tEHDX 0 — 0 — 0 — ns

Write Recovery Time tEHAX 0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.

5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.

WRITE CYCLE 2

tEHDX

tDVEH

tEHAX

tELWH

tELEH

tAVEL

tAVEH

DATA VALID

tAVAV

HIGH–Z

A (ADDRESS)

W (WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix

Part Number

Package (WJ = 400 mil SOJ)

Full Part Numbers — MCM6729DWJ8 MCM6729DWJ10 MCM6729DWJ12

MCM6729DWJ8R MCM6729DWJ10R MCM6729DWJ12R

Shipping Method (R = Tape and Reel, Blank = Rails)

Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns)

MCM 6729D WJ XX X

MCM6729D

MOTOROLA FAST SRAM

PACKAGE DIMENSIONS

32–LEAD

400 MIL SOJ

CASE 857A–02

0.25 (0.010) A B

S S S

0.17 (0.007) A B

S S S

0.17 (0.007) B A

S S S

0.17 (0.007) B A

S S S

32 17

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

20.83

10.03

3.26

0.41

2.24

0.67

0.89

0.76

11.05

9.27

0.77

21.08

10.29

3.75

0.50

2.48

0.81

1.14

11.30

9.52

1.01

0.820

0.395

0.128

0.016

0.088

0.026

0.035

0.030

0.435

0.365

0.030

0.830

0.405

0.148

0.020

0.098

0.032

0.045

0.445

0.375

0.040

1.27 BSC

0.64 BSC

0.050 BSC

0.025 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. TO BE DETERMINED AT PLANE -T-.

4. DIMENSION A & B DO NOT INCLUDE MOLD

PROTRUSION. MOLD PROTRUSION SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

5. DIMENSION A & B INCLUDE MOLD MISMATCH AND

ARE DETERMINED AT THE PARTING LINE.

D32 PL

DETAIL Z

S RADIUS

-B-

F32 PL

NOTE 3

DETAIL Z

-A-

0.10 (0.004)

SEATING

PLANE

-T-

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”

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MCM6729D/D

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