Transmit VGA for Use with RF DACs and Transceivers ADL6317 Data Sheet FEATURES GENERAL DESCRIPTION Transmit VGA for RF DAC, transceiver, and SoC to power amplifier interface RF output frequency range: 1500 MHz to 3000 MHz Internal balun with bias-tee to supply RF DAC outputs Integrated VVA attenuation range with on-chip DAC: 20.5 dB 2-stage high linearity amplifiers RF DSA attenuation range: 15.5 dB with 0.5 dB step resolution 50 differential inputs and 50 single-ended output Fully programmable via a 4-wire SPI Single 5 V supply 38-terminal, 10.5 mm x 5.5 mm LGA The ADL6317 is a transmit variable gain amplifier (VGA) that provides an interface from radio frequency digital-to-analog converters (RF DACs), transceivers, and systems on a chip (SoC) to power amplifiers. Integrated balun and hybrid couplers allow high performance RF capability in the frequency range of 1500 MHz to 3000 MHz. To optimize performance vs. power level, the ADL6317 includes a voltage variable attenuator (VVA), high linearity amplifiers, and a digital step attenuator (DSA). All of the devices integrated into the ADL6317 are programmable via a 4-wire serial port interface (SPI). The ADL6317 is manufactured on an advanced silicon germanium (SiGe), bipolar complementary metal oxide semiconductor (BiCMOS) process. APPLICATIONS 2G/3G/4G/long-term evolution (LTE) in FDD/TDD broadband communication systems Table 1. Related Devices in Transmit VGA Family Parameter ADL6316 ADL6317 Frequency Range (MHz) 500 to 1000 1500 to 3000 FUNCTIONAL BLOCK DIAGRAM GND GND TXEN CS SDI SCLK FUSE BLOCK SERIAL PORT INTERFACE MUXOUT SDO TEMPERATURE SENSOR ANALOG MUX ADC GND VVA_ANALOG CS5 CS4 3.3V LDO GND 1.8V SPI LDO GND GND GND DSA VVA IN_N AMP2 AMP1 RFOUT DAC GND VVA IN_P DSA AMP1 AMP2 GND VDAC GND GND GND GND V50AMP1 GND V33FUSE V50AMP2 GND 20829-001 GND ADL6317 GND Figure 1. Rev. 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Technical Support www.analog.com ADL6317 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Programmability Guide ................................................................. 16 Applications ...................................................................................... 1 Signal Path Modes ...................................................................... 16 General Description ......................................................................... 1 Auxiliary Mux Control .............................................................. 16 Functional Block Diagram .............................................................. 1 Serial Port Interface (SPI) ......................................................... 18 Revision History ............................................................................... 2 Device Setup .................................................................................... 19 Specifications .................................................................................... 3 Applications Information ............................................................. 21 Digital Logic Timing .................................................................... 4 Linearity Optimization .............................................................. 21 Absolute Maximum Ratings ........................................................... 6 Performance and Power Optimization ................................... 21 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Adjacent and Alternate Channel Power Ratios on LTE Operation .................................................................................... 21 Pin Configuration and Function Descriptions ............................ 7 Layout .......................................................................................... 22 Typical Performance Characteristics ............................................. 8 Characterization Setups................................................................. 23 Theory of Operation ...................................................................... 14 Register Summary .......................................................................... 24 RF Input Balun with DAC Interface Network ....................... 14 Register Details ............................................................................... 25 Quadrature Hybrid .................................................................... 14 Outline Dimensions ....................................................................... 38 RF Signal Chain .......................................................................... 14 Ordering Guide .......................................................................... 38 Basic Connections .......................................................................... 15 REVISION HISTORY 5/2020--Revision B: Initial Version Rev. B | Page 2 of 38 Data Sheet ADL6317 SPECIFICATIONS V50AMP1 = V50AMP2 = 5 V, TA = 25C, input power (PIN) = -25 dBm (-25 dBm per tone for two tones), VVA attenuation = 0 dB, DSA attenuation = 0 dB, source resistance (RS) = load resistance (RL) = 50 , unless otherwise noted. Table 2. Parameter FREQUENCY RANGE 1850 MHz Power Gain Output 1 dB Compression Point (OP1dB) Output Second-Order Intercept (OIP2) Output Third-Order Intercept (OIP3) Second Harmonic (HD2) Third Harmonic (HD3) Noise Figure (NF) 2150 MHz Power Gain OP1dB OIP2 OIP3 HD2 HD3 NF 2600 MHz Power Gain OP1dB OIP2 OIP3 HD2 HD3 NF RF INPUT/OUTPUT CHARACTERISTICS Input Impedance Return Loss Output Impedance Return Loss Gain Flatness VOLTAGE VARIABLE ATTENUATOR Range Gain Settling Time DSA Attenuation Range Resolution Gain Settling Time Test Conditions/Comments Min 1500 Typ Max 3000 Units MHz 33.7 25.7 49.2 40.9 82.1 47.2 6.0 dB dBm dBm dBm dBc dBc dB 33.6 24.8 51.8 38.4 76.1 48.8 6.0 dB dBm dBm dBm dBc dBc dB 34.0 22.8 53.8 34.5 84.6 50.7 5.5 dB dBm dBm dBm dBc dBc dB Differential Inband, 2150 MHz 50 -18 dB Single-ended Inband, 2150 MHz Deviation from best linear fit at 1850 MHz, 2150 MHz, and 2600 MHz Over 100 MHz bandwidth Over 150 MHz bandwidth Via 12-bit integrated DAC or external analog voltage on VVA_ANALOG pin 50 -17.4 dB 0.1 0.2 dB dB 20.5 386.8 dB ns 1.681 s 15.5 0.5 304.4 195.0 dB dB ns ns Minimum attenuation to maximum attenuation by VVA DAC Maximum attenuation to minimum attenuation by VVA DAC Minimum attenuation to maximum attenuation Maximum attenuation to minimum attenuation Rev. B | Page 3 of 38 ADL6317 Data Sheet Parameter DIGITAL LOGIC Input Voltage High (VIH) Low (VIL) Input Current High (IIH) Low (IIL) Output Voltage At 1.8 V High (VOH) Test Conditions/Comments Min Typ Max Units 0.68 V V -100 100 A A SCLK, SDI, CS, CS4, CS5, TXEN 1.07 SDO Register 0x121, Bit 4 = 0x0 Output high current (IOH) = -100 A or -1 mA static load Output low current (IOL) = 100 A or 1 mA static load Register 0x121, Bit 4 = 0x1 IOH = -100 A or -1 mA static load IOL = 100 A or 1 mA static load Low (VOL) At 3.3 V High (VOH) Low (VOL) POWER SUPPLY Voltage Supply Current 1.5 V 0.2 V 0.2 V V 2.7 4.75 5.0 435 310 6 High performance mode Low power mode Power Down Current 5.25 V mA mA mA DIGITAL LOGIC TIMING Table 3. Parameter fSCLK tPWH tPWL tDS tDH tDCS tDV Description Maximum serial clock rate, 1/tSCLK Minimum period that SCLK is in logic high state Minimum period that SCLK is in logic low state Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Setup time between falling edge of CS and rising edge of SCLK Maximum time delay between falling edge of SCLK and output data valid for a read operation Min Timing Diagrams DATA TRANSFER CYCLE INSTRUCTION CYCLE CS CHIP ID ADDRESS SDI R/W CS5 CS4 0 0 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7N D6 0 D5 0 Figure 2. Serial Port Interface Register Timing, MSB First Rev. B | Page 4 of 38 D3 0 D20 D1 0 D0 0 20829-002 SCLK Typ 25 10 10 5 5 10 5 Max Unit MHz ns ns ns ns ns ns Data Sheet ADL6317 tSCLK tPWH t PWL SCLK tDCS CS tDS SDI R/W CS5 CS4 0 0 0 0 A_MSB A7 A2 A1 A_LSB D_MSB D6 D5 D1 D_LSB 20829-003 tDH Figure 3. Timing Diagram for the Serial Port Interface Register Write SCLK SDI R/W CS5 CS4 0 0 0 0 A_MSB A7 A2 A1 A_LSB DON'T CARE DON'T CARE D_MSB D6 DON'T CARE DON'T CARE DON'T CARE D1 D_LSB tDV SDO Figure 4. Timing Diagram for Serial Port Interface Register Read Rev. B | Page 5 of 38 D5 20829-004 CS ADL6317 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter V50AMP1, V50AMP2 V33FUSE VDAC VVA_ANALOG CS, SCLK, SDI, SDO, CS4, CS5, TXEN RF Input Power (IN_N, IN_P) at 50 Operating Temperature Range (Measured at Exposed Pad) Junction Temperature Range Storage Temperature Range Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating -0.3 V to +5.5V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V 10 dBm -40C to +105C JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the conduction thermal resistance from junction to case where the case temperature is measured at the bottom of the package. The thermal resistance values specified in Table 5 are simulated based on JEDEC specifications (unless specified otherwise) and should be used in compliance with JESD51-12. -40C to +125C -65C to +150C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 5. Thermal Resistance1, 2 Package Type CC-38-1 JA 21.4 JC BOTTOM 7.6 Unit C/W For JC BOTTOM, the case bottom is controlled at105C and the case top is controlled at 100C. 2 Using enhanced heat removal (for example, PCB, heat sink, and airflow) techniques to improve thermal resistance values. 1 ESD CAUTION Rev. B | Page 6 of 38 Data Sheet ADL6317 GND TXEN CS SDI SCLK SDO MUXOUT GND VVA_ANALOG CS5 CS4 NIC GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 38 37 36 35 34 33 32 31 30 29 28 27 26 1 25 2 24 3 ADL6317 4 TOP VIEW (Not to Scale) EPAD1 GND 6 8 21 20 9 10 11 12 13 14 15 16 17 18 19 GND GND GND NIC 7 22 EPAD2 NOTES 1. NIC = NOT INTERNALLY CONNECTED. THIS PIN HAS NO PHYSICAL CONNECTION WITHIN THE CHIP. 2. EXPOSED PAD 1. EPAD1 IS INTERNALLY CONNECTED TO EPAD2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR ELECTRICAL AND THERMAL PURPOSES. 3. EXPOSED PAD 2. EPAD2 IS INTERNALLY CONNECTED TO EPAD1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR ELECTRICAL AND THERMAL PURPOSES. 20829-005 5 23 GND GND RFOUT GND GND GND NIC GND V50AMP1 GND V33FUSE NIC V50AMP2 NIC GND GND GND IN_N IN_P VDAC Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 2, 6, 7, 8, 9, 12, 14, 19, 20, 21, 22, 24, 25, 26, 31, 38 3 4 5 Mnemonic GND Description Ground. IN_N IN_P VDAC 10, 11, 16, 18, 27 13 15 NIC V50AMP1 V33FUSE 17 23 28, 29 V50AMP2 RFOUT CS4, CS5 30 32 33 34 35 36 37 VVA_ANALOG MUXOUT SDO SCLK SDI CS TXEN EPAD1 RF Input, Negative. RF Input, Positive. Supply Voltage for External RF DAC. This pin can be left open during operation without the RF DAC. No Internal Connection. These pins have no physical connection within the chip. Amplifier 1 Analog Power Supply (5.0 V). VCO Low Dropout (LDO) Regulator Bypass. This pin is optionally 3.3 V when the 3.3 V LDO regulator is off. Amplifier 2 Analog Power Supply (5.0 V). RF Output. Chip Select. Connect these pins to ground. Refer to the Multiple Chip Operation to Share SPI Bus section for information about the connections in a multiple chip operation. Analog Voltage Control for VVA. Test Mux Output. Serial Port Data Output. Serial Port Clock Input. Serial Port Data Input. Serial Port Latch Enable Input. Amplifier Enable, DSA Attenuation, and Trim Value Selection. Exposed Pad 1. EPAD1 is internally connected to EPAD2. The exposed pad must be connected to ground for electrical and thermal purposes. Exposed Pad 2. EPAD2 is internally connected to EPAD1. The exposed pad must be connected to ground for electrical and thermal purposes. EPAD2 Rev. B | Page 7 of 38 ADL6317 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 31 29 ATTENUATION (dB) 27 23 21 19 17 15 13 VVA_ATTEN[11:0] = 0 (Decimal) 9 7 FREQUENCY (MHz) 0 20829-007 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 5 ATTENUATION (dB) GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 20829-008 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1500 1600 Figure 8. Gain vs. Frequency for Various Supplies 4 6 2900 3000 2700 2800 2500 2600 2300 2400 2100 2200 1900 8 10 12 14 16 18 20 22 24 26 28 30 32 Figure 10. Attenuation vs. DSA_ATTEN_x[4:0] at 1850 MHz, 2150 MHz, and 2600 MHz, VVA Attenuation = 0 dB SUPPLY VOLTAGE = 4.75V SUPPLY VOLTAGE = 5.00V SUPPLY VOLTAGE = 5.25V FREQUENCY (MHz) 2 DSA_ATTEN_x[4:0] (Decimal Code) Figure 7. Gain vs. Frequency, 100 VVA_ATTEN[11:0] Steps 35.00 34.75 34.50 34.25 34.00 33.75 33.50 33.25 33.00 32.75 32.50 32.25 32.00 31.75 31.50 31.25 31.00 30.75 30.50 30.25 30.00 FREQUENCY = 1850MHz FREQUENCY = 2140MHz FREQUENCY = 2600MHz 0 500 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 FREQUENCY = 1850MHz 0.8 FREQUENCY = 2140MHz 0.7 FREQUENCY = 2600MHz 0.6 0.5 0.4 0.3 0.2 0.1 0 1000 1500 2000 2500 3000 3500 VVA_ATTEN[11:0] (Decimal Code) VVA VOLTAGE (V) GAIN (dB) 25 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 20829-010 VVA_ATTEN[11:0] = 4000 (Decimal) 33 11 2000 Figure 9. Gain vs. Frequency for Various Temperatures 20829-011 35 1700 FREQUENCY (MHz) Figure 6. Gain vs. Frequency, 0.5 dB DSA Steps 20829-009 FREQUENCY (MHz) TC = -20C TC = +40C TC = +105C 1500 20829-006 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 DSA_ATTEN_x[4:0] = 31 (Decimal) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1800 GAIN (dB) DSA_ATTEN_x[4:0] = 0 (Decimal) 1600 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1500 GAIN (dB) V50AMP1 = V50AMP2 = 5 V, TA = 25C, input power= -25 dBm (-25 dBm per tone for two tones), VVA attenuation = 0 dB, DSA attenuation = 0 dB, RS = RL = 50 , unless otherwise noted. Figure 11. Attenuation and VVA Voltage vs. VVA_ATTEN[11:0] at 1850 MHz, 2150 MHz, and 2600 MHz, DSA Attenuation = 0 dB) Rev. B | Page 8 of 38 ADL6317 30 3000 20829-015 2800 2900 2600 2700 2500 2300 2400 2100 2200 2000 1800 1900 60 TC = -20C TC = +40C TC = +105C 58 56 54 26 52 25 50 42 3000 FREQUENCY (MHz) 20829-016 2900 2800 2700 2600 2500 1500 3000 FREQUENCY (MHz) 20829-013 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 30 1700 32 15 1800 34 16 1600 36 17 1500 38 18 2400 40 19 2300 20 44 2200 21 46 2100 22 OIP3 (dBm) OIP2 (dBm) TC = +105C TC = +40C TC = -20C 48 2000 23 1900 24 1800 OIP3/OIP2 (dBm) 27 1700 28 1600 29 Figure 16. OIP3/OIP2 vs. Frequency for Various Temperatures Figure 13. OP1dB vs. Frequency for Various Temperatures 60 50 58 48 56 46 54 44 42 52 40 48 46 44 42 OIP3 (dBm) OIP3 (dBm) OIP2 (dBm) VVA ATTENUATION = 0dB VVA ATTENUATION = 10dB VVA ATTENUATION = 20.5dB 38 36 34 32 3000 2900 2800 2700 2600 20829-014 FREQUENCY (MHz) 2500 2400 2300 2200 20 2100 22 30 2000 24 32 1900 26 34 1800 36 1700 28 1600 30 38 1500 40 FREQUENCY = 1850MHz FREQUENCY = 2150MHz FREQUENCY = 2600MHz TC = +105C TC = +40C TC = -20C INPUT POWER (dBm) Figure 14. OIP3/OIP2 vs. Frequency at Various VVA Attenuation Values, DSA Attenuation = 0 dB 20829-017 50 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 OP1dB (dBm) 1600 FREQUENCY (MHz) Figure 15. OIP3/OIP2 vs. Frequency at Various DSA Values, VVA Attenuation = 0 dB Figure 12. OP1dB vs. Frequency for Various Supplies OIP3/OIP2 (dBm) OIP3 (dBm) OIP2 (dBm) DSA ATTENUATION = 0dB DSA ATTENUATION = 8dB DSA ATTENUATION = 15.5dB 1500 3000 FREQUENCY (MHz) 20829-012 2800 2900 2700 2500 2600 2400 2200 2300 2000 2100 1900 1700 1800 1500 OIP3/OIP2 (dBm) SUPPLY VOLTAGE = 4.75V SUPPLY VOLTAGE = 5.00V SUPPLY VOLTAGE = 5.25V 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 1700 30.0 29.5 29.0 28.5 28.0 27.5 27.0 26.5 26.0 25.5 25.0 24.5 24.0 23.5 23.0 22.5 22.0 21.5 21.0 20.5 20.0 1600 OP1dB (dBm) Data Sheet Figure 17. OIP3 vs. Input Power for Various Temperatures at 1850 MHz, 2150 MHz, and 2600 MHz Rev. B | Page 9 of 38 ADL6317 Data Sheet 60 60 58 55 52 48 46 44 42 FREQUENCY = 1850MHz FREQUENCY = 2150MHz FREQUENCY = 2600MHz TC = +105C TC = +40C TC = -20C 40 38 36 34 INPUT POWER (dBm) 15 10 55 GAIN (dB), OP1dB (dBm), OIP3 (dBm), OIP2 (dBm), NOISE FIGURE (dB) 60 22 20 18 16 14 TC = +105C TC = +40C TC = -20C VVA ATTENUATION = 0dB VVA ATTENUATION = 10dB VVA ATTENUATION = 20.5dB 8 6 4 OIP2 (dBm) 50 45 30 25 15 10 3000 NOISE FIGURE (dB) 0 20829-019 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 0 1700 OP1dB (dBm) 20 0 FREQUENCY (MHz) GAIN (dB) 35 5 Figure 19. Noise Figure vs. Frequency for Various Temperatures at Various VVA Values, DSA Attenuation = 0 dB OIP3 (dBm) 40 2 1600 NOISE FIGURE (dB) Figure 21. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation, DSA Attenuation = 0 dB, Frequency = 1850 MHz 28 1500 OP1dB (dBm) 20 VVA ATTENUATION (dB) 24 NOISE FIGURE (dB) 25 30 10 GAIN (dB) 30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DSA ATTENUATION (dB) Figure 22. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation, VVA Attenuation = 0 dB, Frequency = 1850 MHz 60 15 14 GAIN (dB), OP1dB (dBm), OIP3 (dBm), OIP2 (dBm), NOISE FIGURE (dB) 12 55 TC = +105C TC = +40C TC = -20C DSA ATTENUATION = 0dB DSA ATTENUATION = 8dB DSA ATTENUATION = 15.5dB 13 11 NOISE FIGURE (dB) 35 0 Figure 18. OIP2 vs. Input Power for Various Temperatures at 1850 MHz, 2150 MHz, and 2600 MHz 12 OIP3 (dBm) 40 10 9 8 7 6 5 4 3 2 45 40 35 25 10 NOISE FIGURE (dB) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 20829-020 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 0 1600 OP1dB (dBm) 15 0 1500 GAIN (dB) 20 5 Figure 20. Noise Figure vs. Frequency for Various Temperatures at Various DSA Values, VVA Attenuation = 0 dB OIP3 (dBm) 30 1 FREQUENCY (MHz) OIP2 (dBm) 50 VVA ATTENUATION (dB) Figure 23. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation, DSA Attenuation = 0 dB, Frequency = 2150 MHz Rev. B | Page 10 of 38 20829-023 30 45 5 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 32 20829-018 OIP2 (dBm) 50 OIP2 (dBm) 50 20829-022 54 20829-021 GAIN (dB), OP1dB (dBm), OIP3 (dBm), OIP2 (dBm), NOISE FIGURE (dB) 56 Data Sheet ADL6317 60 250 1.4 230 1.3 210 1.2 190 1.1 170 1.0 150 0.9 130 0.8 110 0.7 90 0.6 5 70 0.5 0 50 0.4 OIP2 (dBm) 50 OIP3 (dBm) 35 GAIN (dB) 30 OP1dB (dBm) 25 20 20829-027 150 130 140 120 110 90 100 DSA ATTENUATION (dB) 80 10 11 12 13 14 15 16 60 9 70 8 40 7 50 6 20 5 30 4 0 3 10 2 -20 -10 1 -30 NOISE FIGURE (dB) -40 10 -50 15 0 JUNCTION TEMPERATURE (C) Figure 24. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation, VVA Attenuation = 0 dB, Frequency = 2150 MHz Figure 27. Proportional to Absolute Temperature (PTAT) ADC Code and PTAT Voltage vs. Junction Temperature 60 START TIME OIP2 (dBm) 55 STOP TIME 386.81ns 50 45 40 OIP3 (dBm) 35 1 30 25 GAIN (dB) 20 OP1dB (dBm) 2 15 10 NOISE FIGURE (dB) 5 20829-025 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VVA ATTENUATION (dB) Figure 25. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation, DSA Attenuation = 0 dB, Frequency = 2600 MHz CH1 800mV 1M -741mV CH2 980mV 50 1.36V M200ns T 10.3004000s 20829-028 GAIN (dB), OP1dB (dBm), OIP3 (dBm), OIP2 (dBm), NOISE FIGURE (dB) PTAT VOLTAGE (V) 40 PTAT ADC CODE 45 20829-026 GAIN (dB), OP1dB (dBm), OIP3 (dBm), OIP2 (dBm), NOISE FIGURE (dB) 55 Figure 28. VVA Gain Settling Time, Minimum to Maximum VVA Attenuation START TIME STOP TIME 60 1.6813s OIP2 (dBm) 50 45 1 40 OIP3 (dBm) 35 GAIN (dB) 30 2 OP1dB (dBm) 25 20 15 10 NOISE FIGURE (dB) 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DSA ATTENUATION (dB) CH1 800mV 1M -741mV CH2 980mV 50 1.36V 20829-024 0 Figure 26. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation, VVA Attenuation = 0 dB, Frequency = 2600 MHz M500ns T 11.6497800 20829-029 GAIN (dB), OP1dB (dBm), OIP3 (dBm), OIP2 (dBm), NOISE FIGURE (dB) 55 Figure 29. VVA Gain Settling Time, Maximum to Minimum VVA Attenuation Rev. B | Page 11 of 38 ADL6317 Data Sheet START TIME START TIME STOP TIME STOP TIME 54.5ns 304.40ns 1 1 2 M100ns T 10.1981000s CH1 700mV 1M -689mV 1.45V CH2 980mV 50 Figure 30. DSA Gain Settling Time, Minimum to Maximum DSA Attenuation START TIME 20829-033 CH1 700mV 1M -585mV CH2 980mV 50 1.58V 20829-030 2 M20.0ns 10.0359600s T Figure 33. TXEN Response Time Measured from Amplifier 1 and Amplifier 2 Enabled (DSA = 0 dB) to Amplifier 1 and Amplifier 2 Disabled (DSA = 15.5 dB) 0.5 STOP TIME 195.05ns DNL ERROR (dB)/INL ERROR(dB) 0.4 1 2 0.3 0.2 0.1 DNL 0 -0.1 -0.2 -0.3 INL M50.0ns T 10.1197170s -0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 DSA_ATTEN_x[4:0] (Decimal Code) Figure 31. DSA Gain Settling Time, Maximum to Minimum DSA Attenuation START TIME 20829-034 CH1 700mV 1M -585mV CH2 980mV 50 1.58V 20829-031 -0.4 Figure 34. DSA Gain Step Error, Frequency = 1850 MHz 0 STOP TIME WITHOUT TUNING, OPTIMUM ABOVE 2.1GHz WITH TUNING TO OPTIMIZE FOR 1.8GHz TO 2.1GHz WITH TUNING TO OPTIMIZE BELOW 1.8GHz -5 182.97ns RETURN LOSS (dB) -10 1 2 -15 -20 -25 -30 -35 M50.0ns 10.1197170s T -45 1.4 1.6 1.8 2.0 2.2 2.4 FREQUENCY (GHz) Figure 32. TXEN Response Time, Measured from Amplifier 1 and Amplifier 2 Disabled (DSA Attenuation = 15.5 dB) to Amplifier 1 and Amplifier 2 Enabled, (DSA Attenuation = 0 dB) 2.6 2.8 3.0 20829-036 CH1 700mV 1M -585mV CH2 980mV 50 1.58V 20829-032 -40 Figure 35. Return Loss of Differential RF Input S11 from 1.5 GHz to 3 GHz Rev. B | Page 12 of 38 Data Sheet ADL6317 FREQUENCY (MHz) Figure 36. Return Loss of Single-Ended RF Output S22 from 1.5 GHz to 3 GHz Figure 37. Amplifier 1 and Amplifier 2 Supply Current vs. Frequency for Various Temperatures Rev. B | Page 13 of 38 20829-037 3000 2900 3.0 2800 2.8 2700 2.6 2600 2.4 2500 2.2 2400 2.0 FREQUENCY (GHz) 2300 1.8 2200 1.6 2100 1.4 1500 -30 20829-136 -25 AMPLIFIER 2 CURRENT AMPLIFIER 1 CURRENT TC = +105C TC = +40C TC = -20C 2000 -20 1900 -15 1800 -10 1700 AMPLIFIER 1 AND AMPLIFIER 2 SUPPLY CURRENT (mA) RETURN LOSS (dB) -5 250 245 240 235 230 225 220 215 210 205 200 195 190 185 180 175 170 165 160 155 150 1600 0 ADL6317 Data Sheet THEORY OF OPERATION RF SIGNAL CHAIN The ADL6317 is a highly integrated transmit VGA used to interface an RF DAC to the power amplifier in a transmitter. The ADL6317 targets high dynamic range multicarrier transmitter designs. The RF path includes a 20.5 dB VVA, the first stage of the fixed gain amplifier, a 15.5 dB DSA, and the second stage of the fixed gain amplifier (see Figure 38). The ADL6317 has two modes of control of the VVA attenuation: internal analog control using an integrated 12-bit DAC and external analog control. For internal control, use Register 0x104, Bits[3:0] and Register 0x103, Bits[7:0] to set the attenuation. The digital bits are double buffered to avoid major carrier glitch. For this reason, Register 0x104 must be written before Register 0x103. For external analog control of the VVA, a control voltage is applied to the VVA_ANALOG pin (Pin 30). Sample register writes for VVA control are shown in Figure 38. The ADL6317 offers multiple gain control options with an integrated 20.5 dB VVA, on-chip DAC control or external voltage control, a high linearity amplifier, an RF DSA with a 15.5 dB attenuation range in 0.5 dB steps, followed by the second stage high linearity amplifier. Putting all the building blocks of the ADL6317 together, the signal path through the device starts with differential inputs converted to singled-ended by the integrated balun and this single-ended signal is then quadrature coupled by the internal quadrature hybrid. Table 7. Register Writes for the Control of VVA Next, the integrated VVA, Amplifier 1, DSA, and Amplifier 2 optimize the RF signal amplitude for performance before the RF signal passes through the output quadrature hybrid. All the integrated building blocks of the ADL6317 are programmable via the SPI. RF INPUT BALUN WITH DAC INTERFACE NETWORK The ADL6317 converts a single-channel, 50 , input differential signal to a single-ended signal via the integrated balun. Wideband matching allows the DAC to operate over a frequency range from 1500 MHz to 3000 MHz, and a bias tee is included to provide dc bias for the RF DAC. Addres s 0x105 Bits 0x104 [3:0] 0x103 [7:0] Settings 00 10 User defined User defined [1:0] Description DAC to VVA VVA_ANALOG (Pin 30) to VVA 12-bit DAC code to set VVA attenuation; first, write to Register 0x104, Bits[3:0], and then to Register 0x103, Bits[7:0] Next, the fixed gain amplifier is used in a quadrature balanced configuration. The DSA provides a 15.5 dB range with 0.5 dB step resolution. The digital 5-bit DSA attenuation control is found in Bits[4:0] of Register 0x102 and Register 0x112. Finally, the second stage fixed gain amplifier is used in a quadrature balanced configuration. QUADRATURE HYBRID Integrated quadrature hybrids at the RF input and RF output allow wideband performance gain and match with a low input and output reflection coefficient to the RF DAC and PA. REGISTER 0x102, BITS[4:0] (TXEN = 0) REGISTER 0x112, BITS[4:0] (TXEN = 1) BALUN AMP DSA AMP QUADRATURE HYBRID POWER UP DEFAULT IN GRAY DAC VVA_ANALOG 30 VVA QUADRATURE HYBRID 0 VVA CONTROL 2 VVA_SRC REGISTER 0x105, BITS[1:0] Figure 38. RF Signal Chain Rev. B | Page 14 of 38 20829-038 VVA_ATTEN, BITS[11:0] = REGISTER 0x104, BITS[3:0] AND REGISTER 0x103, BITS[7:0] Data Sheet ADL6317 BASIC CONNECTIONS V50AMP1 C9 0.1F AGND C12 10PF AGND V50AMP2 C8 0.1F AGND VDAC C11 10pF AGND R11 1 C5 270PF 560 V33FUSE C14 0.1F AGND C6 1F AGND 5 VDAC 13 V50AMP1 IN_N 3 IN_N 4 IN_P 28 CS4 IN_P AGND 29 CS5 17 V50AMP2 VVA_ANALOG 30 15 V33FUSE 23 RFOUT 32 MUXOUT U1 SDO 33 ADL6317 SCLK 34 SDI 35 36 CS TXEN 37 AGND C13 0.1F AGND RFOUT MUXOUT SDO SCLK SDI CS TXEN 20829-039 1 2 6 7 8 9 12 14 19 20 21 22 24 25 26 31 38 EPAD1 EPAD2 10 11 16 18 27 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NIC NIC NIC NIC NIC AGND VVA_ANALOG AGND Figure 39. Basic Connections Table 8. Basic Connections Functional Blocks 5V Pin No. 13, 17 Mnemonic V50AMP1, V50AMP2 Description Amplifier analog supply voltage, 5V Decoupling 15 V33FUSE 3.3 V LDO regulator decoupling RF Inputs 5 VDAC Supply voltage for external RF DAC 3, 4 IN_N, IN_P Differential RF inputs VVA RF Output 30 23 VVA_ANALOG RFOUT External VVA control voltage input Single-ended RF output Serial Port 33 34 35 36 SDO SCLK SDI CS SPI data output SPI clock SPI data input Chip select active low Auxiliary Mux 32 MUXOUT Mux output Chip Selection Mode Control 28, 29 37 CS4, CS5 TXEN Ground 1, 2, 6 to 9, 12, 14, 19 to 22, 24 to 26, 31, 38 Not applicable GND Chip selection Amplifier enable, DSA attenuation, and trim value selection Ground EPAD1, EPAD2 Exposed pads Exposed Pad Rev. B | Page 15 of 38 Basic Connection Decouple these pins via 10 pF and 0.1 F capacitors to ground. Ensure that the decoupling capacitors are located close to the pins. Decouple this pin via 0.1 F and 1 F capacitors to ground. Ensure that the decoupling capacitors are located close to the pin. VDAC can be left open during operation without the RF DAC. Connect the IN_N and IN_P pins to an RF DAC or transceiver output in differential configuration. Voltage input pin to control VVA attenuation. Connect RF output to power meter, network analyzer, noise figure meter, or spectrum analyzer. 1.8 V to 3.3 V tolerant logic levels. 1.8 V to 3.3 V tolerant logic levels. 1.8 V to 3.3 V tolerant logic levels. 1.8 V to 3.3 V tolerant logic levels. Connect mux output to multimeter, oscilloscope, or spectrum analyzer. Connect these pins to ground. 1.8 V to 3.3 V tolerant logic levels. Connect these pins to the ground of the PCB. The exposed thermal pads are on the bottom of the package. Solder the exposed pads to the PCB ground. EPAD1 and EPAD2 are internally connected to each other. ADL6317 Data Sheet PROGRAMMABILITY GUIDE Viewing the register map at the highest level, the registers are subdivided into the major functional blocks, as shown in Table 9. See the Register Summary section for a complete list of all the registers on the ADL6317. The controls of each mode of operation reside in a designated subsection of the register map. Each operational mode includes individual control of the enables of the amplifier blocks, DSA attenuation, and power mode. Control of these functions reside in Register 0x102 and Register 0x107 to Register 0x10A for TXEN = 0 mode, or Register 0x112 and Register 0x117 to Register 0x11A for TXEN = 1 mode. The specific mode selected by the logic level on the TXEN pin (Pin 37) determines the state of the registers (see Table 11). Table 9. Memory Map Functional Groups Register Address 0x000 to 0x011 0x100 to 0x101, 0x106 0x103 to 0x105 0x10B, 0x11B 0x102, 0x107 to 0x10A Functional Blocks Analog Devices, Inc., SPI configuration Signal path enable VVA source, VVA attenuation Amplifier 2 optimization DSA attenuation, amplifier enable, amplifier trim, TXEN = 0 mode DSA attenuation, amplifier enable, amplifier trim, TXEN = 1 mode Auxiliary mux selection, SPI supply control ADC clock, temperature readback VVA and DSA attenuation readback 0x112, 0x117 to 0x11A 0x120 to 0x121 0x127 to 0x129 0x146 to 0x148 Table 11. Control Registers for the Modes Register Address 0x102 0x112 0x107 0x117 0x108 0x118 0x109 0x119 0x10A 0x11A SIGNAL PATH MODES The ADL6317 has two signal path modes. This feature allows two predefined modes of operation to be controlled by TXEN, a realtime external pin with no SPI latency. Table 10 shows the hardware configuration to select the desired mode. Mode TXEN = 0 TXEN = 1 Function Block DSA attenuation DSA attenuation Amplifier 1 optimization Amplifier 1 optimization Amplifier 1 enable Amplifier 1 enable Amplifier 2 optimization Amplifier 2 optimization Amplifier 2 enable Amplifier 2 enable Signal Path Enable The signal path enable bits are located in Register 0x100, Register 0x108, Register 0x118, Register 0x10A, and Register 0x11A. Figure 40 shows a breakdown of the individual blocks that the particular enable bit controls. Table 10. Mode Selection and Setup Registers TXEN (Pin 37) 0 1 Mode TXEN = 0 TXEN = 1 TXEN = 0 TXEN = 1 TXEN = 0 TXEN = 1 TXEN = 0 TXEN = 1 TXEN = 0 TXEN = 1 Enable, Setup Register 0x102, 0x107 to 0x10A 0x112, 0x117 to 0x11A AUXILIARY MUX CONTROL The ADL6317 has multiple auxiliary mux control blocks that allow various modes of operation and monitoring points (see Figure 41 and Table 12). GND TXEN CS SDI SCLK SDO MUXOUT 3 GND FUSE BLOCK CS4 GND 2 TEMPERATURE SENSOR ANALOG MUX ADC SERIAL PORT INTERFACE GND VVA_ANALOG CS5 3.3V LDO 1.8V SPI LDO GND GND 6 5 7 4 GND DSA VVA IN_N AMP1 AMP2 1 RFOUT DAC GND DSA VVA IN_P AMP1 AMP2 GND VDAC GND GND GND 1: DAC_EN 2: AMUX_BG_EN 3: ADC_EN 4: DSA_EN 1x V50AMP1 GND GND V33FUSE 5: VVA_EN 6: AMP1_EN_x 1 7: AMP2_EN_x 1 = 0 (LOGIC LEVEL = 0) , 1 (LOGIC LEVEL = 1) ON TXEN PIN (PIN 37) Figure 40. Signal Path Enable Block Diagram Rev. B | Page 16 of 38 V50AMP2 GND 20829-040 GND Data Sheet ADL6317 (REGISTER 0x104, BITS[ 3:0], REGISTER 0x103, BITS[7:0]) = VVA_ATTEN, BITS[11:0] DAC PIN 30 00 VVA_CTRL VVA_ANALOG AMUX_2_SEL = REGISTER 0x120, BIT 3 10 PTAT VVA_SRC = REGISTER 0x105, BITS[1:0] 0 AD_COUT, BITS[7:0] ADC 1 000 ADC INPUT 001 ADC CLOCK 002 ADC INPUT 0 1 AMUX_3_SEL = REGISTER 0x120, BITS[6:4] 1.8V LDO OUTPUT 2 3.3V LDO OUTPUT 3 MUXOUT PIN 32 AMUX_1_SEL = REGISTER 0x120, BITS[2:0] 20829-041 POWER-UP DEFAULTS IN GRAY Figure 41. Auxiliary Mux Block Diagram Table 12. Auxiliary Mux Programming Guide Bit Name AMUX_3_SEL Register Address Register 0x120, Bits[6:4] Setting 000 001 010 011 100 101 110 111 AMUX_2_SEL Register 0x120, Bit 3 0 1 AMUX_1_SEL Register 0x120, Bits[2:0] 000 001 010 011 100 101 110 111 Description ADC input, VVA_CTRL, and ADC clock selection on mux. VVA_CTRL is the internal control voltage signal to control VVA attenuation. VVA_CTRL. ADC input. ADC clock. Not used. Not used. Not used. Not used. Not used. ADC input selection. PTAT to ADC input. VVA_CTRL to ADC input. Select mux output. PTAT. Output of AMUX_3_SEL. 1.8 V LDO output. 3.3 V LDO output. GND. GND. Not used. Not used. Rev. B | Page 17 of 38 ADL6317 Data Sheet The SPI of the ADL6317 allows the user to configure the device for specific functions or operations via a 4-wire SPI port. This interface provides users with added flexibility and customization. The serial port interface consists of four control lines: SCLK, SDI, SDO, and CS. The timing requirements for the SPI port are shown in Table 3. The ADL6317 protocol consists of a read/write bit, six chip select ID bits, and nine register address bits, followed by eight data bits. Both the address and data fields are organized with the MSB first and end with the LSB by default. Register 0x000 to Register 0x00B. The ADL6317 always accepts writes for these registers regardless of the six MSBs of the address. The ADL6317 only accepts reads for addresses where the six MSBs are equal to the chip ID, including Register 0x000 to Register 0x00B. Figure 42 shows how to configure the chip ID and the CS5 and CS4 pins to share a 4-wire SPI. The CS5 and CS4 settings are shown in gray in Figure 42. 4-WIRE SPI CS, SDI, SDO, SCLK The ADL6317 input logic level for the write cycle is with a 1.8 V logic level (see the digital logic parameter in Table 2). On a read cycle, the SDO is configurable for 1.8 V (default) or 3.3 V output levels by setting SPI_1P8_3P3_CTRL bit (Register 0x121, Bit 4). ADL6317 DEVICE 0 CHIP ID = 000000 CS5 PIN CS4 PIN CS5 PIN CS4 PIN 1.8V Multiple Chip Operation to Share SPI Bus Multiple ADL6317 devices, up to four, can be addressed using the same 4-wire SPI, which means no extra CS line for each device. For this capability, the chip ID bits of the ADL6317 are reserved as the chip ID (see the SPI interface port as shown in Figure 2). ADL6317 DEVICE 2 CHIP ID = 100000 ADL6317 ADL6317 DEVICE 3 CHIP ID = 110000 DEVICE 1 CHIP ID = 010000 CS5 PIN 1.8V 1.8V The ADL6317 ignores any writes to addresses where the six MSBs are not equal to the chip ID, with the exception of Rev. B | Page 18 of 38 CS4 PIN CS5 PIN CS4 PIN 1.8V Figure 42. Multiple Chip Configuration to Share SPI Bus 20829-042 SERIAL PORT INTERFACE (SPI) Data Sheet ADL6317 DEVICE SETUP The recommended sequence of steps to set up the ADL6317 is as follows: 1. 2. 3. Set up the SPI interface. See Table 13. Set up the common parameters, including auxiliary mux control. See Table 14 and Table 15. Set up the operating mode. See Table 16 to Table 19. a. Set the attenuation on the DSA. b. Enable or disable the amplifiers. c. Set the amplifier reference currents. d. Set the amplifier for linearity optimization. e. Measure the internal temperature. Table 13. SPI Interface Setup Address 0x000 0x001 0x00A Setting 0x99 0x00 0x00 Notes Soft reset, MSB first, SDO active (4-wire SPI) Single instruction, master/slave readback, soft reset, and master/slave transfer Scratch pad Table 14. Signal Path Trim Addres s 0x100 0x101 0x106 0x105 0x104 0x103 Setting 0xFF 0x01 0x00 0x00 0x0F 0xFF Description Enable the DAC, auxiliary mux band gap, ADC, bias generator, DSA, and VVA Enable IP3 optimization and 3.3 V LDO regulator Disable the bias current, IBIAS, via the EN_IBIASGEN_RESISTOR bit (default setting) VVA control source from DAC Attenuation of VVA at minimum attenuation, highest four bits of 12-bit word Attenuation of VVA at minimum attenuation, lowest eight bits of 12-bit word Table 15. Auxiliary Mux Control Address 0x120 0x121 Setting 0x00 0x00 Description PTAT to ADC input, PTAT on mux output Set SPI SDO voltage to 1.8 V Table 16. Power-Down Mode Setup, TXEN = Logic Level 0 Address 0x102 0x107 0x108 0x109 0x10A Setting 0x1F 0x80 0x80 0x80 0x80 Description 15.5 dB attenuation on DSA Set Amplifier 1 reference current, IREF (TRM_AMP1_IREF_0), for low power mode Disable Amplifier 1 Set Amplifier 2 IREF (TRM_AMP2_IREF_0) for low power mode Disable Amplifier 2 Table 17. Normal Operating Mode Setup, TXEN = Logic Level 1 Address 0x112 0x117 0x118 0x119 0x11A Setting 0x00 0x82 0x81 0x82 0x81 Description 0 dB attenuation on DSA Set Amplifier 1 IREF (TRM_AMP1_IREF_1) Enable Amplifier 1 Set Amplifier 2 IREF (TRM_AMP2_IREF_1) Enable Amplifier 2 Table 18. Linearity Optimization Address 0x10B 0x11B Setting 0x02 0x02 Description Set the TRM_AMP2_CB bit Set the TRM_AMP2_IP3 bit Rev. B | Page 19 of 38 ADL6317 Data Sheet Table 19. Internal Temperature Measurement from ADC Conversion Address 0x000 0x100 0x127 0x120 0x00A 0x00A 0x00A 0x00A 0x00A 0x129 Setting 0x18 0xFF 0x20 0x00 0xCC 0xCC 0xCC 0xCC 0xCC Not applicable Description Make SDO active Enable ADC Enable ADC clock divider and set ADC clock frequency PTAT to ADC input, PTAT on mux output Register dummy write Register dummy write Register dummy write Register dummy write Register dummy write Read temperature from ADC Rev. B | Page 20 of 38 Data Sheet ADL6317 APPLICATIONS INFORMATION LINEARITY OPTIMIZATION PERFORMANCE AND POWER OPTIMIZATION The linearity in the ADL6317 can be optimized through the TRM_AMP2_IP3 (Register 0x11B, Bits[1:0]) and TRM_AMP2_CB (Register 0x10B, Bits[1:0]) settings. Set the IP3_OFF bit (Register 0x101, Bit 1) 0x00 for OIP3 optimization. The TRM_AMP2_IP3 bits control the switches in the second amplifier that enables optimal third-order distortion cancellation and optimal OIP3. The TRM_AMP2_CB bits control the common base bias current on the transistor and allows additional linearity optimization. The ADL6317 provides another level of control to optimize power or performance. In applications where performance is critical, the ADL6317 offers performance optimization at the expense of power consumption. However, if low power is the priority, the ADL6317 offers tuning options in the amplifier blocks of the chip to further reduce power consumption. 45 ADJACENT AND ALTERNATE CHANNEL POWER RATIOS ON LTE OPERATION TRM_AMP2_IP3 = 0 TRM_AMP2_IP3 = 1 TRM_AMP2_IP3 = 2 TRM_AMP2_IP3 = 3 44 43 42 Figure 44 shows the adjacent and alternate channel power ratios (CPR) for the ADL6317 using 5 MHz single-carrier LTE. The adjacent CPR is -70.4 dB and the alternative CPR is -72.9 dB at an RF of 1850 MHz. The adjacent and alternate CPR performance varies over output power. On the ADL6317, the output power can be varied by adjusting the input power, the VVA attenuation, or the DSA attenuation. Figure 45 to Figure 47 show the adjacent and alternate CPR performance vs. output power for the different methods of controlling the ADL6317. 41 40 OIP3 (dBm) 39 38 37 36 35 34 33 32 31 3000 20829-043 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 30 1500 Table 20 shows that the potential power optimization vs. performance can fine tune the reference current on RF amplifier settings. FREQUENCY (MHz) Figure 43. OIP3 vs. RF Frequency for Various TRM_AMP2_IP3 Settings, TRM_AMP2_CB = 0x02, TRM_AMP1_IREF_x and TRM_AMP2_IREF_x = 0x02 Figure 43 shows that the OIP3 is optimizable across the TRM_AMP2_IP3 settings. Figure 43 shows better than 1.5 dB OIP3 improvement that correlates to 3 dB improvement on IMD3 performance at below 1.9 GHz through linearity optimization. As shown in Figure 45, the optimum adjacent and alternate CPR can be achievable at an output power of +8 dBm, which corresponds to an input power of -24.6 dBm driving the ADL6317 where the internal VVA is set to 0 dB, and the DSA is set to 0 dB attenuation. Figure 46 and Figure 47 show adjacent and alternate CPR performance vs. output power that is adjusted by VVA attenuation and by DSA attenuation, respectively, with -17.2 dBm of input power. Figure 45 to Figure 47 show below -65 dB adjacent and alternate CPR performance at below +10 dBm output power, and there is gradual degradation above +10 dBm from the contribution to the adjacent and alternate CPR performance of the second stage RF amplifier. When fixing the VVA attenuation and sweeping the DSA, the adjacent and alternate CPR performance remains constant below 6 dBm output power (see Figure 47). Table 20. Power Optimization vs. Performance at 1850 MHz, VVA Attenuation= 0 dB, DSA Attenuation = 0 dB, TRM_AMP2_IP3 = 0x02 TRM_AMPx_IREF_1 Setting (Decimal), Register 0x117 and Register 0x119, Bits[3:0] 3 2 1 0 DC Power (W) 2.36 2.10 1.84 1.55 Rev. B | Page 21 of 38 Gain (dB) 33.1 33.1 33.1 32.8 OP1dB (dBm) 25.8 25.6 25.1 24.3 OIP3 (dBm) 40.3 40.3 39.2 36.9 NF (dB) 6.6 5.9 5.8 5.8 ADL6317 Data Sheet -30 -40 -73.3dBc -70.7dBc ADJACENT AND ALTERNATE CHANNEL POWER RATIO (dB) (10dB/DIV) -30 +5.0dBm -72.9dBc -20 -70.4dBc -10 -50 -60 -70 -80 -100 CENTER 1.85GHz #RES BW 30kHz VBW 30kHz SPAN 24.52MHz SWEEP 103.9ms 20829-044 -90 -60 -70 -80 0 2 4 6 8 10 12 14 16 OUTPUT POWER (dBm) 18 Figure 47. Adjacent and Alternate Channel Power Ratio vs. Output Power (POUT) by DSA Attenuation at 1850 MHz, LTE TM1.1, PIN = -17.2 dBm, VVA Attenuation = 0 dB -30 ADJACENT CPR ALTERNATE CPR LAYOUT -40 Solder the exposed pad on the underside of the ADL6317 to a low thermal and electrical impedance ground plane. This pad is typically soldered to an exposed opening in the solder mask on the evaluation board. Notice the use of 19 via holes on the exposed pad of the ADL6317-EVALZ evaluation board. Connect these ground vias to all other ground layers on the evaluation board to maximize heat dissipation from the device package. For more information on the ADL6317-EVALZ evaluation board, contact Analog Devices, Inc. -50 -60 -70 -80 -4 -2 0 2 4 6 8 10 12 14 16 18 OUTPUT POWER (dBm) 20829-045 ADJACENT AND ALTERNATE CHANNEL POWER RATIO (dB) -50 -90 -2 Figure 44. LTE Carrier, Adjacent and Alternate CPR at 1850 MHz, VVA Attenuation = 0 dB, DSA Attenuation = 11 dB, PIN = -17.2 dBm -90 -6 ADJACENT CPR ALTERNATE CPR -40 20829-047 0 Ensure that the decoupling capacitors are located close to the supply voltage pins. Figure 45. Adjacent and Alternate Channel Power Ratio vs. Output Power (POUT) by PIN at 1850 MHz, LTE Test Model 1.1 (TM1.1), VVA Attenuation = 0 dB, DSA Attenuation = 0 dB ADJACENT CPR ALTERNATE CPR -40 -50 20829-048 -60 -70 Figure 48. Evaluation Board Layout for the ADL6317-EVALZ -80 -90 -6 -4 -2 0 2 4 6 8 10 OUTPUT POWER (dBm) 12 14 16 18 20829-046 ADJACENT AND ALTERNATE CHANNEL POWER RATIO (dB) -30 Figure 46. Adjacent and Alternate Channel Power Ratio vs. Output Power (POUT) by VVA Attenuation at 1850 MHz, LTE TM1.1, PIN = -17.2 dBm, DSA Attenuation = 0 dB Rev. B | Page 22 of 38 Data Sheet ADL6317 CHARACTERIZATION SETUPS The primary setup used to characterize the ADL6317 is shown in Figure 49. The setup measures gain, HD2, HD3, OIP2, and OIP3. ROHDE & SCHWARZ SMA100A SIGNAL GENERATOR ROHDE & SCHWARZ SMA100A SIGNAL GENERATOR COMBINER KEITHLEY S46 SWITCH SYSTEM PC CONTROLLER RFIN 3dB 4-WIRE SPI PROGRAMMING ADL6317 BOARD SUPPLY EVALUATION BOARD AUXILIARY MUX 3dB RFOUT 20829-049 AGILENT PXA N9030B SPECTRUM ANALYZER Figure 49. General Characterization Setup Rev. B | Page 23 of 38 ADL6317 Data Sheet REGISTER SUMMARY Table 21. Register Summary Reg 0x000 Name ADI_SPI_ CONFIG REG_0X0001 Bits [7:0] Bit 7 SOFTRESET_ [7:0] SINGLE_ INSTRUCTION [7:0] [7:0] 0x011 0x012 0x013 0x100 CHIPTYPE PRODUCT_ ID_L PRODUCT_ ID_H SCRATCHPAD SPI_REV VARIANT_ FEOL BEOL_SIF SPARE_012 SPARE_013 SIG_PATH0_0 0x101 0x102 0x103 0x104 0x105 0x106 SIG_PATH1_0 SIG_PATH2_0 SIG_PATH3_0 SIG_PATH4_0 SIG_PATH5_0 SIG_PATH6_0 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x107 SIG_PATH7_0 [7:0] 0x108 SIG_PATH8_0 [7:0] 0x109 SIG_PATH9_0 [7:0] 0x10A SIG_PATHA_0 [7:0] 0x10B 0x112 0x117 SIG_PATHB_0 SIG_PATH2_1 SIG_PATH7_1 [7:0] [7:0] [7:0] 0x118 SIG_PATH8_1 [7:0] 0x119 SIG_PATH9_1 [7:0] 0x11A SIG_PATHA_1 [7:0] 0x11B 0x120 SIG_PATHB_1 AMUX_SEL [7:0] [7:0] 0x121 MULTI_FUNC_ CTRL_0111 ADC_ CONTROL_ ADC_EOC ADC_OUT GENERIC_ READBACK_2 GENERIC_ READBACK_3 GENERIC_ READBACK_4 [7:0] 0x001 0x003 0x004 0x005 0x00A 0x00B 0x010 0x127 0x128 0x129 0x146 0x147 0x148 Bit 0 SOFTRESET Reset 0x00 RW R/W MASTER_ SLAVE_ TRANSFER 0x00 R/W CHIPTYPE PRODUCT_ID[7:0] 0x00 0x00 R R [7:0] PRODUCT_ID[15:8] 0x00 R [7:0] [7:0] [7:0] SCRATCHPAD SPI_REV 0x00 0x00 0x00 R/W R R 0x01 0x00 0x00 0x40 R R R R/W 0x01 0x3F 0x00 0x00 0x00 0x00 R/W R/W R/W R/W R/W R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 0x20 0x00 R/W R/W R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 0x20 R/W R/W 0x00 R/W 0x00 R/W 0x00 0x00 0x00 R R R 0x00 R 0x00 R [7:0] [7:0] [7:0] [7:0] [7:0] Bit 6 LSB_ FIRST_ CSB_ STALL Bit 5 ENDIAN_ MASTER_ SLAVE_RB Bit 3 SDOACTIVE RESERVED Bit 2 ENDIAN Bit 1 LSB_ FIRST SOFT_RESET FEOL VARIANT SIF DAC_EN AMUX_ BG_EN BEOL SPARE_012 SPARE_013 EN_IBIASGEN DSA_EN ADC_EN VVA_EN RESERVED RESERVED IP3_OFF RESERVED LDO33_EN DSA_ATTEN_0 VVA_ATTEN[7:0] RESERVED VVA_ATTEN[11:8] RESERVED RESERVED BYPASS_TRM_ AMP1_IREF_0 BYPASS_TRM_ AMP1_EN_0 BYPASS_TRM_ AMP2_IREF_0 BYPASS_TRM_ AMP2_EN_0 RESERVED RESERVED VVA_SRC EN_IBIASGEN_ RESISTOR TRM_AMP1_ IREF_SEL_0 RESERVED TRM_AMP1_IREF_0 TRM_AMP2_ IREF_SEL_0 RESERVED TRM_AMP2_IREF_0 AMP1_EN_0 AMP2_EN_0 SPARE_10B RESERVED BYPASS_TRM_ RESERVED AMP1_IREF_1 BYPASS_TRM_ AMP1_EN_1 BYPASS_TRM_ RESERVED AMP2_IREF_1 BYPASS_TRM_ AMP2_EN_1 [7:0] AMP1_EN_1 TRM_AMP2_ IREF_SEL_1 RESERVED RESERVED RESERVED TRM_AMP2_CB DSA_ATTEN_1 TRM_AMP1_IREF_1 TRM_AMP1_ IREF_SEL_1 RESERVED SPARE_11B AMUX_3_SEL RESERVED ADC_CLOCK_ DIV_EN [7:0] [7:0] [7:0] [7:0] Bit 4 SDOACTIVE_ TRM_AMP2_IREF_1 AMP2_EN_1 TRM_AMP2_IP3 AMUX_1_SEL AMUX_2_ SEL SPI_1P8_ 3P3_CTRL ADC_MUX_ RESERVED SEL RESERVED TEMP_ADC_OUT VVA_ATTEN_RDBK[7:0] RESERVED AMUX_EX ADC_CLK_FREQ ADC_EOC VVA_ATTEN_RDBK[11:8] RESERVED DSA_ATTEN_RDBK Rev. B | Page 24 of 38 Data Sheet ADL6317 REGISTER DETAILS Address: 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] SOFTRESET_ (R/W) Soft Reset [0] SOFTRESET (R/W) Soft Reset [6] LSB_FIRST_ (R/W) LSB First [1] LSB_FIRST (R/W) LSB First [5] ENDIAN_ (R/W) Endian [2] ENDIAN (R/W) Endian [4] SDOACTIVE_ (R/W) SDO Active [3] SDOACTIVE (R/W) SDO Active Table 22. Bit Descriptions for ADI_SPI_CONFIG Bits 7 Bit Name SOFTRESET_ 6 LSB_FIRST_ 5 ENDIAN_ 4 SDOACTIVE_ 3 SDOACTIVE 2 ENDIAN 1 LSB_FIRST 0 SOFTRESET Description Soft Reset. 0: Reset not asserted. 1: Reset asserted. LSB First. 0: MSB first. 1: LSB first. Endian. 0: Little endian. 1: Big endian. SDO Active. 0: SDO inactive. 1: SDO active. SDO Active. 0: SDO inactive. 1: SDO active. Endian. 0: Little endian. 1: Big endian. LSB First. 0: MSB first. 1: LSB first. Soft Reset. 0: Reset not asserted. 1: Reset asserted. Rev. B | Page 25 of 38 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADL6317 Data Sheet Address: 0x001, Reset: 0x00, Name: REG_0X0001 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] SINGLE_INSTRUCTION (R/W) Single Instruction [0] MASTER_SLAVE_TRANSFER (R/W) Master Slave Transfer [6] CSB_STALL (R/W) CSB Stall [2:1] SOFT_RESET (R/W) Soft Reset [5] MASTER_SLAVE_RB (R/W) Master Slave Readback [4:3] RESERVED Table 23. Bit Descriptions for REG_0X0001 Bits 7 6 5 [4:3] [2:1] 0 Bit Name SINGLE_INSTRUCTION CSB_STALL MASTER_SLAVE_RB RESERVED SOFT_RESET MASTER_SLAVE_TRANSFER Description Single Instruction CS Stall Master Slave Readback Reserved Soft Reset Master Slave Transfer Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R R/W R/W Address: 0x003, Reset: 0x00, Name: CHIPTYPE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CHIPTYPE (R) Chip Type, Read Only Table 24. Bit Descriptions for CHIPTYPE Bits [7:0] Bit Name CHIPTYPE Description Chip Type, Read Only Reset 0x0 Access R Address: 0x004, Reset: 0x00, Name: PRODUCT_ID_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] PRODUCT_ID[7:0] (R) Product ID Low, Lower 8 Bits Table 25. Bit Descriptions for PRODUCT_ID_L Bits [7:0] Bit Name PRODUCT_ID[7:0] Description Product ID Low, Lower 8 Bits Reset 0x0 Access R Address: 0x005, Reset: 0x00, Name: PRODUCT_ID_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] PRODUCT_ID[15:8] (R) Product ID High, Higher 8 Bits Table 26. Bit Descriptions for PRODUCT_ID_H Bits [7:0] Bit Name PRODUCT_ID[15:8] Description Product ID High, Higher 8 Bits Reset 0x0 Rev. B | Page 26 of 38 Access R Data Sheet ADL6317 Address: 0x00A, Reset: 0x00, Name: SCRATCHPAD 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] SCRATCHPAD (R/W) Scratchpad. Used by Software to test read and write Table 27. Bit Descriptions for SCRATCHPAD Bits [7:0] Bit Name SCRATCHPAD Description Scratchpad. Used by Software to test read and write. Reset 0x0 Access R/W Address: 0x00B, Reset: 0x00, Name: SPI_REV 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] SPI_REV (R) SPI Register Map Revision Table 28. Bit Descriptions for SPI_REV Bits [7:0] Bit Name SPI_REV Description SPI Register Map Revision Reset 0x0 Access R Address: 0x010, Reset: 0x00, Name: VARIANT_FEOL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] FEOL (R) Front end of line (FEOL) [3:0] VARIANT (R) Variant Table 29. Bit Descriptions for VARIANT_FEOL Bits [7:4] [3:0] Bit Name FEOL VARIANT Description Front end of line (FEOL) Variant Reset 0x0 0x0 Access R R Address: 0x011, Reset: 0x01, Name: BEOL_SIF 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7:4] SIF (R) Serial Interface Version [3:0] BEOL (R) Back end of line (BEOL) Version Table 30. Bit Descriptions for BEOL_SIF Bits [7:4] [3:0] Bit Name SIF BEOL Description Serial Interface Version Back end of line (BEOL) Version Reset 0x0 0x1 Access R R Address: 0x012, Reset: 0x00, Name: SPARE_0012 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] SPARE_012 (R) Spare Register 0x012 Table 31. Bit Descriptions for SPARE_0012 Bits [7:0] Bit Name SPARE_012 Description Spare Register 0x012 Rev. B | Page 27 of 38 Reset 0x0 Access R ADL6317 Data Sheet Address: 0x013, Reset: 0x00, Name: SPARE_013 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] SPARE_013 (R) Spare Register 0x013 Table 32. Bit Descriptions for SPARE_013 Bits [7:0] Bit Name SPARE_013 Description Spare Register 0x013 Reset 0x0 Access R Address: 0x100, Reset: 0x40, Name: SIG_PATH0_0 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7] DAC_EN (R/W) DAC Enable [1:0] RESERVED [6] AMUX_BG_EN (R/W) Auxiliary Mux Bandgap Enable [5] ADC_EN (R/W) ADC Enable [2] VVA_EN (R/W) VVA Enable [3] DSA_EN (R/W) DSA Enable [4] EN_IBIASGEN (R/W) Enable Bias Generator Table 33. Bit Descriptions for SIG_PATH0_0 Bits 7 Bit Name DAC_EN 6 AMUX_BG_EN 5 ADC_EN 4 EN_IBIASGEN 3 DSA_EN 2 VVA_EN [1:0] RESERVED Description DAC Enable. 0: Disable DAC. 1: Enable DAC. Auxiliary Mux Band Gap Enable. 0: Disable auxiliary mux band gap. 1: Enable auxiliary mux band gap. ADC Enable. 0: Disable ADC. 1: Enable ADC. Enable Bias Generator. 0: Disable bias generator. 1: Enable bias generator. DSA Enable. 0: Disable DSA. 1: Enable DSA. VVA Enable. 0: Disable VVA. 1: Enable VVA. Reserved. Rev. B | Page 28 of 38 Reset 0x0 Access R/W 0x1 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R Data Sheet ADL6317 Address: 0x101, Reset: 0x01, Name: SIG_PATH1_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7:2] RESERVED [0] LDO33_EN (R/W) 3.3V LDO Enable [1] IP3_OFF (R/W) Turn off linearization optim ization functionality for IP3 optim ization Table 34. Bit Descriptions for SIG_PATH1_0 Bits [7:2] 1 Bit Name RESERVED IP3_OFF 0 LDO33_EN Description Reserved. Turn off linearization optimization functionality for IP3 optimization. 0: Turn on linearization optimization functionality. 1: Turn off linearization optimization functionality. 3.3 V LDO Enable. 0: Disable 3.3 V LDO. 1: Enable 3.3 V LDO. Reset 0x0 0x0 Access R R/W 0x1 R/W Address: 0x102, Reset: 0x3F, Name: SIG_PATH2_0 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:5] RESERVED [4:0] DSA_ATTEN_0 (R/W) DSA Attenuator Setting 0 Table 35. Bit Descriptions for SIG_PATH2_0 Bits [7:5] [4:0] Bit Name RESERVED DSA_ATTEN_0 Description Reserved. DSA Attenuator Setting 0. 0: 0 dB. 1: 0.5 dB. 10: 1 dB. 11: 1.5 dB. 100: 2 dB. 101: 2.5 dB. 110: 3 dB. 111: 3.5 dB. 1000: 4 dB. 1001: 4.5 dB. 1010: 5 dB. 1011: 5.5 dB. 1100: 6 dB. 1101: 6.5 dB. 1110: 7 dB. 1111: 7.5 dB. 10000: 8 dB. 10001: 8.5 dB. 10010: 9 dB. 10011: 9.5 dB. 10100: 10 dB. 10101: 10.5 dB. 10110: 11 dB. 10111: 11.5 dB. Rev. B | Page 29 of 38 Reset 0x1 0x1F Access R R/W ADL6317 Bits Data Sheet Bit Name Description 11000: 12 dB. 11001: 12.5 dB. 11010: 13 dB. 11011: 13.5 dB. 11100: 14 dB. 11101: 14.5 dB. 11110: 15 dB. 11111: 15.5 dB. Reset Access Address: 0x103, Reset: 0x00, Name: SIG_PATH3_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] VVA_ATTEN[7:0] (R/W) VVA Attenuation DAC Setting Table 36. Bit Descriptions for SIG_PATH3_0 Bits [7:0] Bit Name VVA_ATTEN[7:0] Description VVA Attenuation DAC Setting Reset 0x0 Access R/W Reset 0x0 0x0 Access R R/W Address: 0x104, Reset: 0x00, Name: SIG_PATH4_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] VVA_ATTEN[11:8] (R/W) VVA Attenuation DAC Setting Table 37. Bit Descriptions for SIG_PATH4_0 Bits [7:4] [3:0] Bit Name RESERVED VVA_ATTEN[11:8] Description Reserved VVA Attenuation DAC Setting Address: 0x105, Reset: 0x00, Name: SIG_PATH5_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] RESERVED [1:0] VVA_SRC (R/W) VVA Voltage Source Table 38. Bit Descriptions for SIG_PATH5_0 Bits [7:2] [1:0] Bit Name RESERVED VVA_SRC Description Reserved VVA Voltage Source 00: DAC to VVA 10: Pin 30 to VVA Rev. B | Page 30 of 38 Reset 0x0 0x0 Access R R/W Data Sheet ADL6317 Address: 0x106, Reset: 0x00, Name: SIG_PATH6_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [0] EN_IBIASGEN_RESISTOR (R/W) Set Bias Generator to Use Resistor Reference [7:1] RESERVED Table 39. Bit Descriptions for SIG_PATH6_0 Bits [7:1] 0 Bit Name RESERVED EN_IBIASGEN_RESISTOR Description Reserved Set Bias Generator to Use Resistor Reference 0: Disable IBIAS 1: Enable IBIAS Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 0x0 0x0 Access R/W R R/W R/W Address: 0x107, Reset: 0x00, Name: SIG_PATH7_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BYPASS_TRM_AMP1_IREF_0 (R/W) Bypass Fused Value of TRM_AMP1_IREF_0 [3:0] TRM_AMP1_IREF_0 (R/W) Amplifier 1 IREF Trim 0 [6:5] RESERVED [4] TRM_AMP1_IREF_SEL_0 (R/W) Amplifier 1 IREF Trim Select 0 Table 40. Bit Descriptions for SIG_PATH7_0 Bits 7 [6:5] 4 [3:0] Bit Name BYPASS_TRM_AMP1_IREF_0 RESERVED TRM_AMP1_IREF_SEL_0 TRM_AMP1_IREF_0 Description Bypass Fused Value of TRM_AMP1_IREF_0 Reserved Amplifier 1 IREF Trim Select 0 Amplifier 1 IREF Trim 0 Address: 0x108, Reset: 0x00, Name: SIG_PATH8_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BYPASS_TRM_AMP1_EN_0 (R/W) Bypass Fused Value of AMP1_EN_0 Internal Trim Data [0] AMP1_EN_0 (R/W) Enable Am plifier 1 (TXEN=0) [6:1] RESERVED Table 41. Bit Descriptions for SIG_PATH8_0 Bits 7 [6:1] 0 Bit Name BYPASS_TRM_AMP1_EN_0 RESERVED AMP1_EN_0 Description Bypass Fused Value of AMP1_EN_0 Internal Trim Data Reserved Enable Amplifier 1 (TXEN = 0) Rev. B | Page 31 of 38 Reset 0x0 0x0 0x0 Access R/W R R/W ADL6317 Data Sheet Address: 0x109, Reset: 0x00, Name: SIG_PATH9_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BYPASS_TRM_AMP2_IREF_0 (R/W) Bypass Fused Value of TRM_AMP2_IREF_0 [3:0] TRM_AMP2_IREF_0 (R/W) Amplifier 2 IREF Trim 0 [6:5] RESERVED [4] TRM_AMP2_IREF_SEL_0 (R/W) Amplifier 2 IREF Trim Select 0 Table 42. Bit Descriptions for SIG_PATH9_0 Bits 7 [6:5] 4 [3:0] Bit Name BYPASS_TRM_AMP2_IREF_0 RESERVED TRM_AMP2_IREF_SEL_0 TRM_AMP2_IREF_0 Description Bypass Fused Value of TRM_AMP2_IREF_0 Reserved Amplifier 2 IREF Trim Select 0 Amplifier 2 IREF Trim 0 Reset 0x0 0x0 0x0 0x0 Access R/W R R/W R/W Address: 0x10A, Reset: 0x00, Name: SIG_PATHA_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BYPASS_TRM_AMP2_EN_0 (R/W) Bypass Fused Value of AMP2_EN_0 Internal Trim Data [0] AMP2_EN_0 (R/W) Enable Am plifier 2 (TXEN=0) [6:1] RESERVED Table 43. Bit Descriptions for SIG_PATHA_0 Bits 7 [6:1] 0 Bit Name BYPASS_TRM_AMP2_EN_0 RESERVED AMP2_EN_0 Description Bypass Fused Value of AMP2_EN_0 Internal Trim Data Reserved Enable Amplifier 2 (TXEN = 0) Reset 0x0 0x0 0x0 Address: 0x10B, Reset: 0x00, Name: SIG_PATHB_0 [7:2] SPARE_10B (R/W) Spare Register 0x10B 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [1:0] TRM_AMP2_CB (R/W) Am plifier 2 Com m on Base Trim Table 44. Bit Descriptions for SIG_PATHB_0 Bits [7:2] [1:0] Bit Name SPARE_10B TRM_AMP2_CB Description Spare Register 0x10B Amplifier 2 Common Base Trim Rev. B | Page 32 of 38 Reset 0x0 0x0 Access R/W R/W Access R/W R R/W Data Sheet ADL6317 Address: 0x112, Reset: 0x20, Name: SIG_PATH2_1 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 [7:5] RESERVED [4:0] DSA_ATTEN_1 (R/W) DSA Attenuator Setting 1 Table 45. Bit Descriptions for SIG_PATH2_1 Bits [7:5] [4:0] Bit Name RESERVED DSA_ATTEN_1 Description Reserved. DSA Attenuator Setting 1. 0: 0 dB. 1: 0.5 dB. 10: 1 dB. 11: 1.5 dB. 100: 2 dB. 101: 2.5 dB. 110: 3 dB. 111: 3.5 dB. 1000: 4 dB. 1001: 4.5 dB. 1010: 5 dB. 1011: 5.5 dB. 1100: 6 dB. 1101: 6.5 dB. 1110: 7 dB. 1111: 7.5 dB. 10000: 8 dB. 10001: 8.5 dB. 10010: 9 dB. 10011: 9.5 dB. 10100: 10 dB. 10101: 10.5 dB. 10110: 11 dB. 10111: 11.5 dB. 11000: 12 dB. 11001: 12.5 dB. 11010: 13 dB. 11011: 13.5 dB. 11100: 14 dB. 11101: 14.5 dB. 11110: 15 dB. 11111: 15.5 dB. Rev. B | Page 33 of 38 Reset 0x1 0x0 Access R R/W ADL6317 Data Sheet Address: 0x117, Reset: 0x00, Name: SIG_PATH7_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BYPASS_TRM_AMP1_IREF_1 (R/W) Bypass Fused Value of TRM_AMP1_IREF_1 [3:0] TRM_AMP1_IREF_1 (R/W) Amplifier 1 IREF Trim 1 [6:5] RESERVED [4] TRM_AMP1_IREF_SEL_1 (R/W) Amplifier 1 IREF Trim Select 1 Table 46. Bit Descriptions for SIG_PATH7_1 Bits 7 [6:5] 4 [3:0] Bit Name BYPASS_TRM_AMP1_IREF_1 RESERVED TRM_AMP1_IREF_SEL_1 TRM_AMP1_IREF_1 Description Bypass Fused Value of TRM_AMP1_IREF_1 Reserved Amplifier 1 IREF Trim Select 1 Amplifier 1 IREF Trim 1 Reset 0x0 0x0 0x0 0x0 Access R/W R R/W R/W Address: 0x118, Reset: 0x00, Name: SIG_PATH8_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BYPASS_TRM_AMP1_EN_1 (R/W) Bypass Fused Value of AMP1_EN_1 Internal Trim Data [0] AMP1_EN_1 (R/W) Enable Am plifier 1 (TXEN=1) [6:1] RESERVED Table 47. Bit Descriptions for SIG_PATH8_1 Bits 7 [6:1] 0 Bit Name BYPASS_TRM_AMP1_EN_1 RESERVED AMP1_EN_1 Description Bypass Fused Value of AMP1_EN_1 Internal Trim Data Reserved Enable Amplifier 1 (TXEN = 1) Reset 0x0 0x0 0x0 Access R/W R R/W Address: 0x119, Reset: 0x00, Name: SIG_PATH9_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BYPASS_TRM_AMP2_IREF_1 (R/W) Bypass Fused Value of TRM_AMP2_IREF_1 [3:0] TRM_AMP2_IREF_1 (R/W) Amplifier 2 IREF Trim 1 [6:5] RESERVED [4] TRM_AMP2_IREF_SEL_1 (R/W) Amplifier 2 IREF Trim Select 1 Table 48. Bit Descriptions for SIG_PATH9_1 Bits 7 [6:5] 4 [3:0] Bit Name BYPASS_TRM_AMP2_IREF_1 RESERVED TRM_AMP2_IREF_SEL_1 TRM_AMP2_IREF_1 Description Bypass Fused Value of TRM_AMP2_IREF_1 Reserved Amplifier 2 IREF Trim Select 1 Amplifier 2 IREF Trim 1 Reset 0x0 0x0 0x0 0x0 Access R/W R R/W R/W Address: 0x11A, Reset: 0x00, Name: SIG_PATHA_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] BYPASS_TRM_AMP2_EN_1 (R/W) Bypass Fused Value of AMP2_EN_1 Internal Trim Data [0] AMP2_EN_1 (R/W) Enable Am plifier 2 (TXEN=1) [6:1] RESERVED Table 49. Bit Descriptions for SIG_PATHA_1 Bits 7 [6:1] 0 Bit Name BYPASS_TRM_AMP2_EN_1 RESERVED AMP2_EN_1 Description Bypass Fused Value of AMP2_EN_1 Internal Trim Data Reserved Enable Amplifier 2 (TXEN = 1) Rev. B | Page 34 of 38 Reset 0x0 0x0 0x0 Access R/W R R/W Data Sheet ADL6317 Address: 0x11B, Reset: 0x00, Name: SIG_PATHB_1 2 3 4 5 6 7 0 1 0 0 0 0 0 0 0 0 [7:2] SPARE_11B (R/W) Spare Register 0x11B [1:0] TRM_AMP2_IP3 (R/W) Amplifier 2 IP3 Trim Table 50. Bit Descriptions for SIG_PATHB_1 Bits [7:2] [1:0] Bit Name SPARE_11B TRM_AMP2_IP3 Description Spare Register 0x11B Amplifier 2 IP3 Trim 00: Trim Mode 0 01: Trim Mode 1 10: Trim Mode 2 11: Trim Mode 3 Reset 0x0 0x0 Access R/W R/W Address: 0x120, Reset: 0x20, Name: AMUX_SEL 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 [7] RESERVED [2:0] AMUX_1_SEL (R/W) Select Mux Output [6:4] AMUX_3_SEL (R/W) ADC Input, VVA_CTRL, ADC Clock Selection on MUX [3] AMUX_2_SEL (R/W) ADC Input Selection Table 51. Bit Descriptions for AMUX_SEL Bits 7 [6:4] Bit Name RESERVED AMUX_3_SEL 3 AMUX_2_SEL [2:0] AMUX_1_SEL Description Reserved. ADC Input, VVA_CTRL, ADC Clock Selection on Mux. 000: VVA_CTRL. 001: ADC input. 010: ADC clock. 011 to 111: Not used. ADC Input Selection. 0: PTAT to ADC input. 1: VVA_CTRL to ADC input. Select Mux Output. 000: PTAT. 001: Output of AMUX_3_SEL. 010: 1.8 V LDO output. 011: 3.3 V LDO output. 100: GND. 101: GND. 110: Not used. 111: Not used. Reset 0x0 0x2 Access R/W R/W 0x0 R/W 0x0 R/W Address: 0x121, Reset: 0x00, Name: MULTI_FUNC_CTRL_0111 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] SPI_1P8_3P3_CTRL (R/W) SPI Supply Control [3:0] AMUX_EX (R/W) Auxiliary Mux External Table 52. Bit Descriptions for MULTI_FUNC_CTRL_0111 Bits [7:5] 4 Bit Name RESERVED SPI_1P8_3P3_CTRL [3:0] AMUX_EX Description Reserved SPI Supply Control 0: 1.8 V readback 1: 3.3 V readback Auxiliary Mux External Rev. B | Page 35 of 38 Reset 0x0 0x0 Access R R/W 0x0 R/W ADL6317 Data Sheet Address: 0x127, Reset: 0x00, Name: ADC_CONTROL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [2:0] ADC_CLK_FREQ (R/W) ADC Clock Frequency Division Ratio. Divided Down Gated Clock [5] ADC_CLOCK_DIV_EN (R/W) ADC Clock Divider Enable [3] RESERVED [4] ADC_MUX_SEL (R/W) ADC Clock Source Selection Table 53. Bit Descriptions for ADC_CONTROL Bits [7:6] 5 Bit Name RESERVED ADC_CLOCK_DIV_EN 4 ADC_MUX_SEL 3 [2:0] RESERVED ADC_CLK_FREQ Description Reserved. ADC Clock Divider Enable. 0: Disable ADC clock divider. 1: Enable ADC clock divider. ADC Clock Source Selection. 0: ADC clock from SCLK. 1: Not used. Reserved. ADC Clock Frequency Division Ratio. Divided Down Gated Clock. 000: ADC clock at SCLK/2. 001: ADC clock at SCLK/1. 010: ADC clock at SCLK/2. 011: ADC clock at SCLK/4. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x0 R R/W Address: 0x128, Reset: 0x00, Name: ADC_EOC 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:1] RESERVED [0] ADC_EOC (R) ADC End of Conversion (EOC) Table 54. Bit Descriptions for ADC_EOC Bits [7:1] 0 Bit Name RESERVED ADC_EOC Description Reserved ADC End of Conversion (EOC) Reset 0x0 0x0 Access R R Address: 0x129, Reset: 0x00, Name: ADC_OUT 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] TEMP_ADC_OUT (R) Temperature Sensor Output of Auxiliary MUX ADC Table 55. Bit Descriptions for ADC_OUT Bits [7:0] Bit Name TEMP_ADC_OUT Description Temperature Sensor Output of Auxiliary Mux ADC Reset 0x0 Access R Address: 0x146, Reset: 0x00, Name: GENERIC_READBACK_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] VVA_ATTEN_RDBK[7:0] (R) VVA Attenuation Setting Readback Table 56. Bit Descriptions for GENERIC_READBACK_2 Bits [7:0] Bit Name VVA_ATTEN_RDBK[7:0] Description VVA Attenuation Setting Readback Rev. B | Page 36 of 38 Reset 0x0 Access R Data Sheet ADL6317 Address: 0x147, Reset: 0x00, Name: GENERIC_READBACK_3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] VVA_ATTEN_RDBK[11:8] (R) VVA Attenuation Setting Readback Table 57. Bit Descriptions for GENERIC_READBACK_3 Bits [7:4] [3:0] Bit Name RESERVED VVA_ATTEN_RDBK[11:8] Description Reserved VVA Attenuation Setting Readback Reset 0x0 0x0 Access R R Address: 0x148, Reset: 0x00, Name: GENERIC_READBACK_4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] DSA_ATTEN_RDBK (R) DSA Attenuator Readback Table 58. Bit Descriptions for GENERIC_READBACK_4 Bits [7:6] [5:0] Bit Name RESERVED DSA_ATTEN_RDBK Description Reserved DSA Attenuator Readback Rev. B | Page 37 of 38 Reset 0x0 0x0 Access R R ADL6317 Data Sheet OUTLINE DIMENSIONS 8.40 REF 0.20 BSC 0.70 BSC 26 25 5.60 5.50 5.40 1.08 0.98 0.88 1 3.50 REF 0.70 BSC TOP VIEW PIN 1 INDICATOR C 0.30 x0.45 38 0.10 REF 3.50 BSC 20 6 19 7 BOTTOM VIEW 4.15 BSC 0.50 0.45 0.40 8.50 BSC 0.530 REF SIDE VIEW 0.498 0.448 0.398 PKG-006045 SEATING PLANE 0.45 0.40 0.35 FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 10-11-2018-A PIN 1 CORNER AREA 10.60 10.50 10.40 Figure 50. 38-Terminal Land Grid Array [LGA] (CC-38-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL6317ACCZ ADL6317ACCZ-R7 ADL6317-EVALZ 1 2 Temperature Range 2 -40C to +105C -40C to +105C Package Description 38-Terminal Land Grid Array [LGA] 38-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part Measured at the exposed pad. (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D20829-5/20(B) Rev. B | Page 38 of 38 Package Option CC-38-1 CC-38-1