Da t a s h e e t , V 2 . 0 , 2 8 F e b 2 0 0 0 PWM+PFC Combi IC TDA 16888 / TDA 16888G High Performance Power Combi Controller Power Conversion N e v e r s t o p t h i n k i n g . TDA 16888/ TDA 16888G Revision History: 2000-02-28 Datasheet Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com CoolMOSTM, CoolSETTM are trademarks of Infineon Technologies AG. Edition 2000-02-28 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen (c) Infineon Technologies AG 1999. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. High Performance Power Combi Controller 1 Overview 1.1 Features TDA 16888 PFC Section - - - - - - - - - IEC 1000-3 compliant Additional operation mode as auxiliary power supply Fast, soft switching totem pole gate drive (1 A) Dual loop control (average current and voltage sensing) Leading edge triggered pulse width modulation Peak current limitation Topologies of PFC preconverter are boost or flyback Continuous/discontinuous mode possible 94% maximum duty cycle P-DIP-20-5 P-DSO-20-1 /-6 /-7 PWM Section - - - - - - - Improved current mode control Fast, soft switching totem pole gate drive (1 A) Soft-start management Trailing edge triggered pulse width modulation Topologies of PWM converter are feed forward or flyback 50% maximum duty cycle to prevent transformer saturation fPWM = fPFC Type Ordering Code Package TDA 16888 Q67000-A9284-X201-K5 P-DIP-20-5 TDA 16888 G Q67000-A9310-A702 P-DSO-20-1 New type Version 2.0 3 28 Feb 2000 TDA 16888 Special Features - - - - - - - - - - High power factor Typical 50 A start-up supply current Low quiescent current (15 mA) Undervoltage lockout with internal stand-by operation Internally synchronized fixed operating frequency ranging from 15 kHz to 200 kHz External synchronization possible Shutdown of both outputs externally triggerable Peak current limitation Overvoltage protection Average current sensing by noise filtering 1.2 General Remarks The TDA 16888 comprises the complete control for power factor controlled switched mode power supplies. With its PFC and PWM section being internally synchronized, it applies for off-line converters with input voltages ranging from 90 V to 270 V. While the preferred topologies of the PFC preconverter are boost or flyback, the PWM section can be designed as forward or flyback converter. In order to achieve minimal line current gaps the maximum duty cycle of the PFC is about 94%. The maximum duty cycle of the PWM, however, is limited to 50% to prevent transformer saturation. Version 2.0 4 28 Feb 2000 TDA 16888 P-DIP-20-5 P-DSO-20-1 PFC IAC 1 20 AUX VS VREF 2 19 PFC VS PFC CC 3 18 PFC VC PFC CS 4 17 PFC FB GND S 5 16 ROSC PFC CL 6 15 PWM RMP GND 7 14 PWM IN PFC OUT 8 13 PWM SS VCC 9 12 SYNC 10 11 PWM CS PWM OUT PFC IAC VREF PFC CC PFC CS GND S PFC CL GND PFC OUT VCC PWM OUT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AUX VS PFC VS PFC VC PFC FB ROSC PWM RMP PWM IN PWM SS SYNC PWM CS AEP02486 AEP02461 Figure 1 Version 2.0 Pin Configuration (top view) 5 28 Feb 2000 TDA 16888 1.3 Pin Definitions and Functions Pin No. Symbol Function 1 PFC IAC AC line voltage sensing input 2 VREF 7.5 V reference 3 PFC CC PFC current loop compensation 4 PFC CS PFC current sense 5 GND S Ground sensing input 6 PFC CL Sensing input for PFC current limitation 7 GND Ground 8 PFC OUT PFC driver output 9 VCC Supply voltage 10 PWM OUT PWM driver output 11 PWM CS PWM current sense 12 SYNC Oscillator synchronization input 13 PWM SS PWM soft-start 14 PWM IN PWM output voltage sensing input 15 PWM RMP PWM voltage ramp 16 ROSC Oscillator frequency set-up 17 PFC FB PFC voltage loop feedback 18 PFC VC PFC voltage loop compensation 19 PFC VS PFC output voltage sensing input 20 AUX VS Auxiliary power supply voltage sense Version 2.0 6 28 Feb 2000 R2 VS M1 M2 M 3 D1 QM 2 V REF Voltage Reference 7.5 V (Output Disable) Power Management Undervoltage Lockout 11 V-14 V Z3 17.5 V 10 k 5V OP1 <_ 1 D2 OTA1 6V 12 16 SYNC ROSC + _ 13 PWM SS 7.4 V 5V D3 AUX VS 20 + _ OP2 0.45 V 0.4 V C5 1 30 A GND S 5 PWM Bias Control + _ PFC CS 4 OTA3 1.2 V OTA2 C1 C4 14 PWM IN Osc PFC CC 3 C6 + _ C2 C7 C8 R1 0.4 V 10 k 6V 5.5 V 15 PWM RMP R3 100 k 4V 5.5 V 1 V PFC VS 19 + _ + _ 7 + _ + _ 1 C10 V1 1.5 V + _ + _ + _ Version 2.0 + _ PFC VC 18 FF1 R S 11 PWM CS _ FF2 S R 1V C9 OP3 1 V + 5 & & + _ C3 PFC CL 6 D4 & & 7 GND VS Z2 VS Z1 VS 9 V CC AEB02357 10 PWM OUT PFC OUT 8 1.4 + _ PFC PFC IAC FB 1 17 TDA 16888 Block Diagram Figure 2 28 Feb 2000 TDA 16888 2 Functional Description Power Supply The TDA 16888 is protected against overvoltages typically above 17.5 V by an internal Zener diode Z3 at pin 9 (VCC) and against electrostatic discharging at any pin by special ESD circuitry. By means of its power management the TDA 16888 will switch from internal stand-by, which is characterized by negligible current consumption, to operation mode as soon as a supply voltage threshold of 14 V at pin 9 (VCC) is exceeded. To avoid uncontrolled ringing at switch-over an undervoltage lockout is implemented, which will cause the power management to switch from operation mode to internal stand-by as soon as the supply voltage falls below a threshold of 11 V. Therefore, even if the supply voltage will fall below 14 V, operation mode will be maintained as long as the supply voltage is well above 11 V. As soon as the supply voltage has stabilized, which is determined by the TDA 16888's power management and its soft-start feature at pin 13 (PWM SS), the PWM section will be enabled by means of its internal bias control. Protection Circuitry Both PFC and PWM section are equipped with a fast overvoltage protection (C6) sensing at pin 19 (PFC VS), which when being activated will immediately shut down both gate drives. In addition to improve the PFC section's load regulation it uses a fast but soft overvoltage protection (OTA2) prior to the one described above, which when being activated will cause a well controlled throttling of the multiplier output QM. In case an undervoltage of the PFC output voltage is detected at pin 19 (PFC VS) by comparator C4 the gate drive of the PWM section will be shut down in order to reduce the load current and to increase the PFC output voltage. This undervoltage shutdown has to be prior to the undervoltage lockout of the internal power management and therefore has to be bound to a threshold voltage at pin 9 (VCC) well above 11 V. In order to prevent the external circuitry from destruction the PFC output PFC OUT (pin 8) will immediately be switched off by comparator C2, if the voltage at pin 19 (PFC VS) drops to ground caused by a broken wire. In a similar way measures are taken to handle a broken wire at any other pin in order to ensure a safe operation of the IC and its adjoining circuitry. If necessary both outputs, PFC OUT (pin 8) and PWM OUT (pin 10), can be shutdown on external request. This is accomplished by shorting the external reference voltage at pin 2 (VREF) to ground. To protect the external reference, it is equipped with a foldback characteristic, which will cut down the output current when VREF (pin 2) is shorted (see Figure 4). Version 2.0 8 28 Feb 2000 TDA 16888 Both PFC and PWM section are equipped with a peak current limitation, which is realized by the comparators C3 and C9 sensing at pin 6 (PFC CL) and pin 11 (PWM CS) respectively. When being activated this current limitation will immediately shut down the respective gate drive PFC OUT (pin 8) or PWM OUT (pin 10). Finally each pin is protected against electrostatic discharge. Oscillator/Synchronization The PFC and PWM clock signals as well as the PFC voltage ramp are synchronized by the internal oscillator (see Figure 18). The oscillator's frequency is set by an external resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is integrated to guarantee a low current consumption and a high resistance against electromagnetic interferences. In order to ensure superior precision of the clock frequency, the clock signal CLK OSC is derived from a triangular instead of a saw-tooth signal. Furthermore to provide a clock reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillator's clock signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section respectively (see Figure 18). The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a steeply rising edge. This ramp has been reversed in contrast to the common practice, in order to simultaneously allow for current measurement at pin 5 (GND S) and for external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The oscillator can be synchronized with an external clock signal supplied at pin 12 (SYNC). However, since the oscillator's frequency is halved before being fed into the PFC and PWM section, a synchronization frequency being twice the operating frequency is recommended. As long as the synchronization signal is H the oscillator's triangular signal VOSC is interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However, as soon as the external clock changes from H to L the oscillator is released. Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied on principle only within the range from 0.66 fOSC to 2 fOSC. If the oscillator has to be synchronized over a wider frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has to be preferred to a synchronization by means of pin 12 (SYNC). Anyhow, please note, that pin 12 (SYNC) is not meant to permanently shutdown both PFC and PWM section. It can be used to halt the oscillator freezing the prevailing state of both drivers but does not allow to automatically shut them down. A shutdown can be achieved by shorting pin 2 (VREF) to ground, instead. Finally, In order to reduce the overall current consumption under low load conditions, the oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less than 0.4 V (disabled PWM section). Version 2.0 9 28 Feb 2000 TDA 16888 PFC Section At normal operation the PFC section operates with dual loop control. An inner loop, which includes OP2, C1, FF1 and the PFC's driver, controls the shape of the line current by average current control enabling either continuous or discontinuous operation. By the outer loop, which is supported by OP1, the multiplier, OP2, C1, FF1 and the PFC's driver, the PFC output voltage is controlled. Furthermore there is a third control loop composed of OTA1, OP2, C1, FF1 and the PFC's driver, which allows the PFC section to be operated as an auxiliary power supply even when the PWM section is disabled. With disabled PWM section, however, the PFC section is operated with half of its nominal operating frequency in order to reduce the overall current consumption. Based on a pulse-width-modulation, which is leading edge triggered with respect to the internal clock reference CLK OUT and which is trailing edge modulated according to the PFC ramp signal VPFC RMP and the output voltage of OP2 VPFC CC (see Figure 18), the PFC section is designed for a maximum duty cycle of ca. 94% to achieve minimal line current gaps. PWM Section The PWM section is equipped with improved current mode control containing effective slope compensation as well as enhanced spike suppression in contrast to the commonly used leading edge current blanking. This is achieved by the chain of operational amplifier OP3, voltage source V1 and the 1st order low pass filter composed of R1 and an external capacitor, which is connected to pin 15 (PWM RMP). For crosstalk suppression between PFC and PWM section a signal-to-noise ratio comparable to voltage mode controlled PWM's is set by operational amplifier OP3 performing a fivefold amplification of the PWM load current, which is sensed by an external shunt resistor. In order to simultaneously perform effective slope compensation and to suppress leading spikes, which are due to parasitic capacitances being discharged whenever the power transistor is switched on, the resulting signal is subsequently increased by the constant voltage of V1 and finally fed into the 1st order low pass filter. The peak ramp voltage, that in this way can be reached, amounts to ca. 6.5 V. By combination of voltage source V1 and the following low pass filter a basic ramp (step response) with a leading notch is created, which will fully compensate a leading spike (see Figure 12) provided, the external capacitor at pin 15 (PWM RMP) and the external current sensing shunt resistor are scaled properly. Version 2.0 10 28 Feb 2000 TDA 16888 The pulse-width-modulation of the PWM section is trailing edge modulated according to the PWM ramp signal VPWM RMP at pin 15 (PWM RMP) and the input voltage VPWM IN at pin 14 (PWM IN) (see Figure 18). In contrast to the PFC section, however, the pulsewidth-modulation of the PWM section is trailing edge triggered with respect to the internal clock reference CLK OUT in order to avoid undesirable electromagnetic interference of both sections. Moreover the maximum duty cycle of the PWM is limited to 50% to prevent transformer saturation. By means of the above mentioned improved current mode control a stable pulse-widthmodulation from maximum load down to no load is achieved. Finally, in case of no load conditions the PWM section may as well be disabled by shorting pin 13 (PWM SS) to ground. Version 2.0 11 28 Feb 2000 TDA 16888 3 Functional Block Description Gate Drive Both PFC and PWM section use fast totem pole gate drives at pin 8 (PFC OUT) and pin 10 (PWM OUT) respectively, which are designed to avoid cross conduction currents and which are equipped with Zener diodes (Z1, Z2) in order to improve the control of the attached power transistors as well as to protect them against undesirable gate overvoltages. At voltages below the undervoltage lockout threshold these gate drives are active low. In order to keep the switching losses of the involved power diodes low and to minimize electromagnetic emissions, both gate drives are optimized for soft switching operation. This is achieved by a novel slope control of the rising edge at each driver's output (see Figure 13). Oscillator The TDA 16888's clock signals as well as the PFC voltage ramp are provided by the internal oscillator. The oscillator's frequency is set by an external resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is integrated to guarantee a low current consumption and a high resistance against electromagnetic interferences. In order to ensure superior precision of the clock frequency, the clock signal CLK OSC is derived from the minima and maxima of a triangular instead of a saw-tooth signal (see Figure 18). Furthermore, to provide a clock reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillator's clock signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section respectively. The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a steeply rising edge, the latter of which is triggered by the rising edge of the clock reference CLK OUT. This ramp has been reversed in contrast to the common practice, in order to simultaneously allow for current measurement at pin 5 (GND S) and for external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The slope of the falling edge, which in conjunction with the output of OP2 controls the pulsewidth-modulation of the PFC output signal VPFC OUT, is derived from the current set by the external resistor at pin 16 (ROSC). In this way a constant amplitude of the ramp signal (ca. 4.5 V) is ensured. In contrast, the slope of the rising edge, which marks the minimum blanking interval and therefore limits the maximum duty cycle ton,max of the PFC output signal, is determined by an internal current source. In contrast to the PFC section the ramp signal of the PWM section is trailing edge triggered with respect to the internal clock reference CLK OUT to avoid undesirable electromagnetic interference of both sections. Moreover, the maximum duty cycle of the PWM is limited by the rising edge of the clock reference CLK OUT to 50% to prevent transformer saturation. Version 2.0 12 28 Feb 2000 TDA 16888 The oscillator can be synchronized with an external clock signal supplied at pin 12 (SYNC). As long as this clock signal is H the oscillator's triangular signal VOSC is interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However, as soon as the external clock changes from H to L the oscillator is released. Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied on principle only within the range from 0.66 fOSC to 2 fOSC. Please note, that the slope of the falling edge of the PFC ramp is not influenced by the synchronization frequency. Instead the lower voltage peak is modulated. Consequently, on the one hand at high synchronization frequencies fSYNC > fOSC the amplitude of the ramp signal and correspondingly its signal-to-noise ratio is decreased (see Figure 19). On the other hand at low synchronization frequencies fSYNC < fOSC the lower voltage peak is clamped to the minimum ramp voltage (typ. 1.1 V), that at least can be achieved (see Figure 20), which may cause undefined PFC duty cycles as the voltage VPFC CC at pin 3 (PFC CC) drops below this threshold. However, if the oscillator has to be synchronized over a wide frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has to be preferred to a synchronization by means of pin 12 (SYNC). In order to reduce the overall current consumption under low load conditions, the oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less than 0.4 V (disabled PWM section). Multiplier The multiplier serves to provide the controlled current IQM by combination of the shape of the sinusoidal input current IM1 derived from the voltage at pin 1 (PFC IAC) by means of the 10 k resistor R2, the magnitude of the PFC output voltage VM2 given at pin 18 (PFC VC) and the possibility for soft overvoltage protection VM3 (see Chapter Protection Circuitry ). By means of this current the required power factor as well as the magnitude of the PFC output voltage is ensured. To achieve an excellent performance over a wide range of output power and input voltage, the input voltage VM2 is amplified by an exponential function before being fed into the multiplier (see Figure 8). Voltage Amplifier OP1 Being part of the outer loop the error amplifier OP1 controls the magnitude of the PFC output voltage by comparison of the PFC output voltage measured at pin 17 (PFC FB) with an internal reference voltage. The latter is fixed to 5 V in order to achieve immunity from external noise. To allow for individual feedback the output of OP1 is connected to pin 18 (PFC VC). Version 2.0 13 28 Feb 2000 TDA 16888 Current Amplifier OP2 Being part of the inner loop the error amplifier OP2 controls the shape of the line current by comparison of the controlled current IQM with the measured average line current. This is achieved by setting the pulse width of the PFC gate drive in conjunction with the comparator C1. In order to limit the voltage range supplied at pin 4 (PFC CS) and at pin 5 (GND S), clamping diodes D1, D2 and D3 are connected with these pins and ground. To allow for individual feedback the output of OP2 is connected to pin 3 (PFC CC). Ramp Amplifier OP3 For crosstalk suppression between PFC and PWM section a signal-to-noise ratio comparable to voltage mode controlled PWMs is set by operational amplifier OP3 performing a fivefold amplification of the PWM load current, which is sensed by an external shunt resistor. In order to suppress leading spikes, which are due to parasitic capacitances being discharged whenever the power transistor is switched on, the resulting signal is subsequently increased by the constant voltage of V1 and finally fed into a 1st order low pass filter. By combination of voltage source V1 and the following low pass filter a step response with a leading notch is created, which will fully compensate a leading spike (see Figure 12) provided, the external capacitor at pin 15 (PWM RMP) and the external current sensing shunt resistor are scaled properly. Operational Transconductance Amplifier OTA1 The TDA 16888's auxiliary power supply mode is controlled by the fast operational transconductance amplifier OTA1. When under low load or no load conditions a voltage below 5 V is sensed at pin 20 (AUX VS), it will start to superimpose its output on the output QM of the multiplier and in this way will replace the error amplifier OP1 and the multiplier. At normal operation, however, when the voltage at pin 20 (AUX VS) is well above 5 V, this operational transconductance amplifier is disabled. Operational Transconductance Amplifier OTA2 By means of the operational transconductance amplifier OTA2 sensing at pin 19 (PFC VS) a fast but soft overvoltage protection of the PFC output voltage is achieved, which when being activated (VPFC VS > 5.5 V) will cause a well controlled throttling of the multiplier output QM (see Figure 9). Operational Transconductance Amplifier OTA3 In order to achieve offset compensation of error amplifier OP2 under low load conditions, that will not suffice to start OTA1, the operational transconductance amplifier OTA3 is introduced. It will start operation as soon as these conditions are reached, i.e. the voltage at pin 18 (PFC VC) falls below 1.2 V. Version 2.0 14 28 Feb 2000 TDA 16888 Comparator C1 The comparator C1 serves to adjust the duty cycle of the PFC gate drive. This is achieved by comparison of the output voltage of OP2 given at pin 3 (PFC CC) and the voltage ramp of the oscillator. Comparator C2 The comparator C2 serves to prevent the external circuitry from destruction by immediately switching the PFC output PFC OUT (pin 8) off, if the voltage at pin 19 (PFC VS) drops below 1 V due to a broken wire. Comparator C3 By means of this extremely fast comparator sensing at pin 6 (PFC CL) peak current limitation is realized. When being activated (VPFC CL < 1 V) it will immediately shut down the gate drive of the PFC section (pin 8, PFC OUT). In order to protect C3 against undervoltages at pin 6 (PFC CL) due to large inrush currents, this pin is equipped with an additional clamping diode D4. Comparator C4 This comparator along with the TDA 16888's power management serves to reset the PWM section's soft start at pin 13 (PWM SS). C4 becomes active as soon as an undervoltage (VPFC VS < 4 V) of the PFC output voltage is sensed at pin 19 (PFC VS). Comparator C5 Based on the status of the PWM section's soft start at pin 13 (PWM SS), the comparator C5 controls the bias of the entire PWM section. In this way the PWM section is switched off giving a very low quiescent current, until its soft start is released. Comparator C6 Overvoltage protection of the PWM section's input voltage sensed at pin 19 (PFC VS) is realized by comparator C6, which when being activated will immediately shut down both gate drives PFC OUT (pin 8) and PWM OUT (pin 10). Comparator C7 This comparator sensing at pin 13 (PWM SS) and at pin 15 (PWM RMP) controls the pulse width modulation of the PWM section during the soft start. This is done right after the PWM section is biased by comparator C5. Version 2.0 15 28 Feb 2000 TDA 16888 Comparator C8 The control of the pulse width modulation of the PWM section is taken over by comparator C8 as soon as the soft start is finished. This is achieved by comparison of the PWM output voltage at pin 14 (PWM IN) and the PWM voltage ramp at pin 15 (PWM RMP). Comparator C9 By means of this extremely fast comparator sensing at pin 11 (PWM CS) peak current limitation is realized. When being activated (VPWM CS > 1 V) it will immediately shut down the gate drive of the PWM section (PWM OUT). Comparator C10 By means of the threshold of 0.4 V the comparator C10 allows the PWM duty cycle to be continuously controlled from 0 to 50%. As long as the ramp voltage at pin 15 (PWM RMP) is below this threshold the gate drive of the PWM section (pin 10, PWM OUT) is turned off. Version 2.0 16 28 Feb 2000 TDA 16888 4 Electrical Characteristics 4.1 Absolute Maximum Ratings TA = - 25 to 85 C Parameter# Symbol Limit Values Unit Remarks min. max. VS IZ3 VVREF VROSC VSYNC VPFC FB VPFC IAC VAUX VS VPFC VS VPFC CL VPWM SS VPWM IN VPWM RMP VPWM CS VPFC VC IPFC VC IPFC CS IGND S VPFC CC IPFC CC IOUT - 0.3 VZ3 V VZ3 = Zener voltage of Z3 - 50 mA - - 0.3 8 V - 0.3 8 V VVREF < VS VROSC < VS - 0.3 8 V - - 0.3 8 V - - 0.3 15 V - - 0.3 8 V - - 0.3 8 V |IPFC VS| < 1 mA -1 3 V |IPFC CL| < 1 mA - 0.3 8 V VPWM SS < VVREF - 0.3 8 V - - 0.3 8 V VPWM RMP < VVREF - 0.3 3 V - - 0.3 8 V - - 20 20 mA - -5 5 mA - -5 5 mA - - 0.3 8 V - - 20 20 mA - - 100 100 mA - PFC/PWM OUT peak clamping current IOUT - mA VOUT = High PFC/PWM OUT peak clamping current IOUT - 500 - mA VOUT = Low Junction temperature TJ - 40 C - VCC supply voltage Zener current of Z3 VREF voltage ROSC voltage SYNC voltage PFC FB voltage PFC IAC voltage AUX VS voltage PFC VS voltage PFC CL voltage PWM SS voltage PWM IN voltage PWM RMP voltage PWM CS voltage PFC VC voltage PFC VC current PFC CS current GND S current PFC CC voltage PFC CC current PFC/PWM OUT DC current Version 2.0 200 150 17 28 Feb 2000 TDA 16888 4.1 Absolute Maximum Ratings (cont'd) TA = - 25 to 85 C Parameter# Storage temperature Thermal resistance Thermal resistance Symbol TS RthJA RthJA Limit Values Unit Remarks min. max. - 65 150 C - - 60 K/W P-DIP-20-5 - 70 K/W P-DSO-20-1 Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. To avoid destruction make sure, that for any pin except for pins PFC OUT and PWM OUT the currents caused by transient processes stay well below 100 mA. For the same reason make sure, that any capacitor that will be connected to pin 9 (VCC) is discharged before assembling the application circuit. In order to characterize the gate driver's output performance Figure 14, Figure 15, Figure 16 and Figure 17 are provided, instead of referring just to a single parameter like the maximum gate charge or the maximum output energy. 4.2 Operating Range Parameter VCC supply voltage Symbol VS IZ3 Zener current PFC/PWM OUT current IOUT IPFC IAC PFC IAC input current fOUT PFC/PWM frequency TJ Junction temperature Limit Values Unit Remarks min. max. 0 VZ3 V 0 50 mA VZ3 = Zener voltage of Z3 Limited by TJ,max -1 1.5 A - 0 1 mA - 15 200 kHz - - 25 125 C - Note: Within the operating range the IC operates as described in the functional description. In order to characterize the gate driver's output performance Figure 14, Figure 15, Figure 16 and Figure 17 are provided, instead of referring just to a single parameter like the maximum gate charge or the maximum output energy. Version 2.0 18 28 Feb 2000 TDA 16888 4.3 Characteristics Supply Section Parameter Symbol 1) Zener voltage Zener current Quiescent supply current VZ3 IZ3 IS Limit Values Unit Test Condition IZ3 = 30 mA VS 15.5 V2) VPWM SS = 0 V RROSC = 51 k CL = 0 V min. typ. max. 16.0 17.5 19.0 V - - 500 A - - 12 mA PFC enabled PWM disabled - - 15 mA VPWM SS = 6 V RROSC = 51 k CL = 0 F PFC enabled PWM enabled Supply current IS - - 40 mA VPWM SS = 6 V RROSC = 51 k CL = 4.7 nF PFC enabled PWM enabled 1) 2) See Figure 3 Design characteristics (not meant for production testing) Note: The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range TA from - 25 C to 85 C Typical values represent the median values, which are related to production processes. If not otherwise stated, a supply voltage of VS = 15 V is assumed. Version 2.0 19 28 Feb 2000 TDA 16888 Undervoltage Lockout Parameter Symbol Limit Values min. typ. max. Unit Test Condition Power up, rising voltage threshold1) VS,UP 13.0 14.0 14.5 V - Power down, falling voltage threshold1) VS,DWN 10.5 11.0 11.5 V - Power up, threshold current IS,UP - 23 100 A VS = VS,UP - 0.1 V VPFC CL < 0.3 V2) Stand-by mode 1) 2) See Figure 3 To ensure the voltage fallback of pin PFC CL is disabled. Internal Voltage Reference Parameter Symbol Limit Values min. typ. max. Unit Test Condition Trimmed reference voltage VREF 4.9 5.0 5.1 V Measured at pin PFC VC Line regulation VREF - - 40 mV VS = 3 V Version 2.0 20 28 Feb 2000 TDA 16888 External Voltage Reference Parameter Symbol Limit Values Unit Test Condition min. typ. max. VVREF VVREF VVREF IVREF 7.2 7.5 7.8 V - 3 mA IVREF 0 - - 50 mV VS = 3 V 0 40 100 mV IVREF = 2 mA - 10 -6 -4 mA VVREF = 6.5 V IVREF VVREF - -2 - mA VVREF = 0 V - 6.6 - V - VVREF Shutdown hysteresis, falling voltage threshold - 6.2 - V - td,VREF - 500 - ns VVREF = 5 V2)3) VPFC OUT = 3 V2)3) VPWM OUT = 3 V2)3) Unit Test Condition RROSC = 110 k RROSC = 51 k VS = 3 V RROSC = 51 k Buffered output voltage Line regulation Load regulation Maximum output current1) Short circuit current1) Shutdown hysteresis, rising voltage threshold Shutdown delay 1) 2) 3) See Figure 4 Design characteristics (not meant for production testing) Transient reference value Oscillator Parameter PFC/PWM frequency1) PFC/PWM frequency1) PFC/PWM frequency, line regulation Symbol fOUT50 fOUT100 fOUT Limit Values min. typ. max. 43 50 57 kHz 87 100 113 kHz - - 1 % 5.4 5.6 V - VPFC RMP 5.0 Minimum ramp voltage VPFC RMP 0.8 - SYNC, low level voltage VSYNC 1.1 1.4 V - - 0.4 V - SYNC, high level voltage VSYNC 3.5 - VVREF V - - - 20 A - - 150 A Maximum ramp voltage SYNC, input current 1) ISYNC VSYNC < 0.4 V VSYNC = 3.5 V See Figure 5 Version 2.0 21 28 Feb 2000 TDA 16888 PFC Section Parameter Symbol Limit Values min. typ. max. Unit Test Condition VPFC OUT = 2 V3) RROSC = 51 k CL = 4.7 nF 0.9 IPFC CS IPFC IAC = 100 A VPFC VC = 6 V Max duty cycle1) Don,PFC 91 94 98 % Multiplier throttling (OTA2), threshold voltage2) VPFC VS 5.2 5.5 5.8 V OTA1 disabled Overvoltage protection (C6), rising voltage threshold VPFC VS 5.8 6 6.2 V - Overvoltage protection (C6), falling voltage threshold VPFC VS 5.3 5.5 5.7 V - Overvoltage protection (C6), turn-off delay td,OV - 2 - s VPFC VS = 6.5 V3)4) VPFC OUT = 3 V3)4) Broken wire detection (C2), threshold voltage VPFC VS 0.93 1 1.07 V - Voltage sense, input current IPFC VS 0.2 0.45 0.7 A VPFC VS = 1 V Current limitation (C3), threshold voltage VPFC CL 0.93 1 1.07 V - Current limitation (C3), input current IPFC CL 1 - 10 A VPFC CL = 1 V Current limitation (C3, D4), clamping voltage VPFC CL - 0.9 - - 0.1 V IPFC CL = - 500 A Current limitation (C3), turn-off delay td,CL 30 - 150 ns VPFC CL = 0.75 V3) VPFC OUT = 3 V3) CL = 4.7 nF 1) 2) 3) 4) See Figure 6 See Figure 9 Transient reference value Design characteristics (not meant for production testing) Version 2.0 22 28 Feb 2000 TDA 16888 Multiplier Parameter Input current Input voltage Exponential function, threshold voltage Symbol IPFC IAC VPFC VC VPFC VC Limit Values Unit Test Condition min. typ. max. 0 - 1 mA - 0 - 6.7 V - - 1.1 - V 1)2) Maximum output current IPFC CS - 320 - 420 - 550 A OTA1 disabled Output current3) - IPFC IAC = 0 A VPFC VC = 2 V IPFC CS - 100 - 500 nA OTA1 disabled - - 1.2 - A IPFC IAC = 25 A VPFC VC = 2 V OTA1 disabled - - 10 - A IPFC IAC = 25 A VPFC VC = 4 V OTA1 disabled - - 40 - A IPFC IAC = 100 A VPFC VC = 4 V OTA1 disabled - - 150 - A IPFC IAC = 400 A VPFC VC = 4 V OTA1 disabled - - 170 - A IPFC IAC = 100 A VPFC VC = 6 V OTA1 disabled 1) 2) 3) Design characteristics (not meant for production testing) For input voltages below this threshold the multiplier output current remains constant. For input voltages above this threshold the output rises exponentially (see Figure 8). See Figure 7 Version 2.0 23 28 Feb 2000 TDA 16888 Operational Transconductance Amplifier (OTA1) Parameter Symbol Auxiliary power supply, threshold voltage1) VAUX VS Input current IAUX VS Output current 1) Limit Values min. typ. max. 4.8 5.0 5.2 Unit Test Condition V IPFC CS = - 1 A Multiplier disabled IPFC CS - - 15 A - 20 - - A - 0 - A - - 30 - A VAUX VS > 5.2 V VAUX VS < 4.8 V VAUX VS > 5.2 V1) VAUX VS < 4.8 V For input voltages below this threshold the output current is linearly increasing until at ca. 4.8 V the maximum output current is reached. Operational Transconductance Amplifier (OTA3) Parameter Symbol Limit Values min. typ. max. Unit Test Condition Offset compensation, threshold voltage VPFC VC 1.1 1.2 - V - Input current IPFC VC IGND S -1 - - A 1) - 0 - A - - 10 - A VPFC VC > 1.2 V VPFC VC < 1.1 V Output current 1) Design characteristics (not meant for production testing) Version 2.0 24 28 Feb 2000 TDA 16888 Voltage Amplifier (OP1) Parameter Symbol Limit Values Unit Test Condition min. typ. max. VOff IPFC FB APFC VC VPFC FB VPFC FB -4 - 4 mV 1) -1 - 1 A VPFC FB = 4 V - 85 - dB 2) 0 - 6 V - 4.9 5 5.1 V - Output, maximum voltage VPFC VC 6.3 - VVREF V IPFC VC = - 500 A Output, minimum voltage VPFC VC 0.5 - 1.1 V IPFC VC = 500 A Output, short circuit source current IPFC VC - - 10 - mA Output, short circuit sink IPFC VC current - 10 - mA VPFC VC = 0 V VPFC FB = 4.9 V VPFC VC = 6.4 V VPFC FB = 5.1 V Offset voltage Input current Open loop gain Input voltage range Voltage sense, threshold voltage 1) 2) Guaranteed by wafer test Design characteristics (not meant for production testing) Version 2.0 25 28 Feb 2000 TDA 16888 Current Amplifier (OP2) Parameter Symbol VOff IPFC CS Input current IGND S APFC CC Open loop gain Gain bandwidth product fT Offset voltage Phase margin Common mode voltage VCMVR range Limit Values Unit Test Condition min. typ. max. -5 -1 3 mV - - 500 - 500 nA - - 110 - dB - - 2.5 - MHz 1) - 60 - 1) - 0.2 - 0.5 V 1) 0.4 - 1.0 V IPFC CS = 500 A IGND S = 500 A Clamped input voltage, upper threshold (D2, D3) VPFC CS VGND S Clamped input voltage, lower threshold (D1) VPFC CS Output, maximum voltage VPFC CC 6.3 - VVREF V IPFC CC = - 500 A Output, minimum voltage VPFC CC 0.5 - 1.1 V IPFC CC = 500 A Output, short circuit source current IPFC CC - - 10 - mA Output, short circuit sink IPFC CC current - 10 - mA VPFC CC = 0 V VPFC CS = 0 V VGND S = 0.5 V VPFC CC = 6.5 V VPFC CS = 0.5 V VGND S = 0 V 1) Multiplier, OTA1 and OTA3 disabled - 0.9 - - 0.1 V IPFC CS = - 500 A Multiplier and OTA1 disabled Design characteristics (not meant for production testing) Version 2.0 26 28 Feb 2000 TDA 16888 PWM Section Parameter Symbol Undervoltage protection (C4), VPFC VS threshold voltage Limit Values Unit Test Condition min. typ. max. 3.8 4.0 4.2 V - Bias control (C5), rising voltage threshold VBC,Th - 0.45 - V - Bias control (C5), falling voltage threshold VBC,Th - 0.4 - V - Softstart (I1), charging current II1 20 30 40 A - Softstart, maximum voltage VPWM SS VPWM IN R3 AOP3 VRMP - 6.7 - V - 0.4 - 7.4 V - 75 100 150 k - - 5 - V/V - 0.36 0.4 0.5 V - VRMP VV1 ZRMP - 6.5 - V - - 1.5 - V - - 10 - k - Input voltage PWM IN - GND resistance Ramp (OP3), voltage gain Ramp (C10), pulse start threshold voltage Ramp, maximum voltage Ramp (V1), voltage offset Ramp (R1), output impedance Maximum duty cycle Don,PWM 41 - 50 % VPWM OUT = 2 V1) RROSC = 51 k CL = 4.7 nF Current sense (C9), voltage threshold VCS,Th 0.9 1.0 1.1 V - Current sense (C9), overload turn-off delay td,CS 30 - 250 ns VPWM CS = 1.25 V1) VPWM OUT = 3 V1) CL = 4.7 nF 1) Transient reference value Version 2.0 27 28 Feb 2000 TDA 16888 Gate Drive (PWM and PFC Section) Parameter Symbol Limit Values Unit Test Condition min. typ. max. VOUT - - 1.2 V VS = 5 V IOUT = 5 mA - - 1.5 V - 0.8 - V - 1.6 2.0 V - 0.2 0.2 - V 10 11 12 V 10.0 10.5 - V 8.8 - V - 150 - ns - 100 - ns - 30 - ns - 40 - ns Output current, rising edge3) IOUT -1 - - A Output current, falling edge3) IOUT - - 1.5 A VS = 5 V IOUT = 20 mA IOUT = 0 A IOUT = 50 mA IOUT = - 50 mA VS = 16 V tH = 10 s CL = 4.7 nF VS = 12 V tH = 10 s CL = 4.7 nF VS = VS,DWN + 0.2 V tH = 10 s CL = 4.7 nF VOUT = 2 V ... 8 V2) CL = 4.7 nF VOUT = 3 V ... 6 V2) CL = 4.7 nF VOUT = 9 V ... 3 V2) CL = 4.7 nF VOUT = 9 V ... 2 V2) CL = 4.7 nF CL = 4.7 nF4) CL = 4.7 nF4) Output, minimum voltage Output, maximum voltage Rise time1) Fall time 1) 2) 3) 4) VOUT tr tf - See Figure 13 Transient reference value The gate driver's output performance is characterized in Figure 14, Figure 15, Figure 16 and Figure 17. Design characteristics (not meant for production testing) Note: If not otherwise stated the figures shown in this section represent typical performance characteristics. Version 2.0 28 28 Feb 2000 TDA 16888 AED02462 VCC S S, UP V S, DWN Figure 3 V S, UP V Z3 V VCC Undervoltage Lockout Hysteresis and Zener Diode Overvoltage Protection VREF AED02463 -8 mA -7 -6 -5 -4 -3 -2 -1 0 Figure 4 Version 2.0 0 1 2 3 4 5 6 7 V V VREF 8 Foldback Characteristic of Pin 2 (VREF) 29 28 Feb 2000 TDA 16888 AED02464 400 kHz f OUT 100 10 10 100 k 500 R OSC Figure 5 PFC/PWM Frequency AED02465 100 % Don, PFC, max 95 90 85 80 0 100 200 300 k 400 R OSC Figure 6 Version 2.0 Maximum PFC Duty Cycle 30 28 Feb 2000 TDA 16888 AED02466 500 A VPFC VC = 7 V PFC CCS 400 6V 5V 4V 300 200 3V 100 2V 0 0 0.2 0.4 0.6 0.8 mA 1 PFC IAC Figure 7 Multiplier Linearity AED02356 500 A PFC CCS PFC IAC = 800 A 400 A 200 A 100 A 50 A 25 A 400 300 200 100 0 Figure 8 Version 2.0 0 1 2 3 4 5 6 V 7 VPFC VC Multiplier Dynamic 31 28 Feb 2000 TDA 16888 AED02467 500 A PFC IAC > 300 A VPFC VC = 6 V PFC CCS 250 A 400 200 A 300 150 A 200 100 A 100 50 A 0 5.0 5.25 5.5 5.75 V 6.0 VPFC VS Figure 9 Multiplier Throttling by OTA2 AED02468 100 dB A PFC VC 80 -30 60 Version 2.0 A PFC VC -60 40 -90 20 -120 0 10 -2 Figure 10 0 deg 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -150 10 6 Hz 10 7 Frequency Open Loop Gain and Phase Characteristic of Voltage Amplifier OP1 32 28 Feb 2000 TDA 16888 AED02469 120 dB A PFC CC 100 -30 A PFC CC 80 -60 60 -90 40 -120 20 -150 0 10 -2 Figure 11 0 deg 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -180 10 6 Hz 10 7 Frequency Open Loop Gain and Phase Characteristic of Current Amplifier OP2 AED02470 V1 VPWM CS V1 /2 0 4V1 VPWM RMP 3V1 VPWMCS = 0 2V1 V1 0 T/2 0 T Time Figure 12 Version 2.0 PWM Ramp Composition Scheme 33 28 Feb 2000 TDA 16888 AED02471 12 V VPFC OUT 10 8 6 4 2 0 0 0.1 0.2 s 0.4 0.3 Time Figure 13 Rising Edge of Driver Output AED02542 150 PD RL = 0 RL = 1 RL = 2 RL = 5 R L = 10 mW 100 50 f OUT = 15 kHz P D0 = 0.194 W 0 0 10 20 30 40 nF 50 CL Figure 14 Power Dissipation of Single Gate Driver at fOUT = 15 kHz Version 2.0 34 28 Feb 2000 TDA 16888 AED02543 500 PD RL = 0 RL = 1 RL = 2 RL = 5 R L = 10 mW 400 300 200 100 f OUT = 50 kHz P D0 = 0.197 W 0 0 10 20 30 40 nF 50 CL Power Dissipation of Single Gate Driver at fOUT = 50 kHz Figure 15 AED02544 1 PD RL = 0 RL = 1 RL = 2 RL = 5 R L = 10 mW 0.8 0.6 0.4 0.2 f OUT = 100 kHz P D0 = 0.201 W 0 0 10 20 30 40 nF 50 CL Figure 16 Version 2.0 Power Dissipation of Single Gate Driver at fOUT = 100 kHz 35 28 Feb 2000 TDA 16888 AED02545 1.5 PD RL = 0 RL = 1 RL = 2 RL = 5 R L = 10 mW 1.0 0.5 f OUT = 200 kHz P D0 = 0.212 W 0 0 10 20 30 40 nF 50 CL Figure 17 Version 2.0 Power Dissipation of Single Gate Driver at fOUT = 200 kHz 36 28 Feb 2000 TDA 16888 VOSC CLK OSC CLK OUT VPFC RMP VPFC CC VPFC OUT t on, max VPWM RMP VPWM IN VBC, Th VPWM OUT t on, max Time Figure 18 Version 2.0 AET02546 Timing Diagram without Synchronization 37 28 Feb 2000 TDA 16888 VOSC VSYNC CLK OSC CLK OUT VPFC RMP VPFC CC VPFC OUT t on, max VPWM RMP VPWM IN VBC, Th VPWM OUT t on, max Time Figure 19 Version 2.0 AET02547 Timing Diagram with Synchronization (fSYNC > fOSC) 38 28 Feb 2000 TDA 16888 VOSC VSYNC CLK OSC CLK OUT VPFC RMP VPFC CC VPFC OUT t on, max VPWM RMP VPWM IN VBC, Th VPWM OUT t on, max Time Figure 20 Version 2.0 AET02548 Timing Diagram with Synchronization (fSYNC < fOSC) 39 28 Feb 2000 TDA 16888 5 Package Outlines GPD05587 P-DIP-20-5 (Plastic Dual In-line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Version 2.0 40 Dimensions in mm 28 Feb 2000 TDA 16888 1.27 x 8 ma 7.6 -0.2 1) +0.09 0.35 x 45 0.23 2.65 max 2.45 -0.2 0.2 -0.1 P-DSO-20-1 (Plastic Dual Small Outline) 0.4 +0.8 0.35 +0.15 2) 0.2 24x 20 0.1 10.3 0.3 11 GPS05094 1 12.8 1) 10 -0.2 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Version 2.0 41 GPS 05094 Index Marking Dimensions in mm 28 Feb 2000 Total Quality Management Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Quality takes on an all encompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. http://www.infineon.com Published by Infineon Technologies AG Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.