LP38841MRX-ADJ - National Semiconductor

LP38841-ADJ

LP38841-ADJ 0.8A Ultra Low Dropout Adjustable Linear Regulators Stable

with Ceramic Output Capacitors

Literature Number: SNVS305B

December 2006

LP38841-ADJ

0.8A Ultra Low Dropout Adjustable Linear Regulators

Stable with Ceramic Output Capacitors

General Description

The LP38841-ADJ is a high current, fast response regulator

which can maintain output voltage regulation with minimum

input to output voltage drop. Fabricated on a CMOS process,

the device operates from two input voltages: Vbias provides

voltage to drive the gate of the N-MOS power transistor, while

Vin is the input voltage which supplies power to the load. The

use of an external bias rail allows the part to operate from ultra

low Vin voltages. Unlike bipolar regulators, the CMOS archi-

tecture consumes extremely low quiescent current at any

output load current. The use of an N-MOS power transistor

results in wide bandwidth, yet minimum external capacitance

is required to maintain loop stability.

The fast transient response of these devices makes them

suitable for use in powering DSP, Microcontroller Core volt-

ages and Switch Mode Power Supply post regulators. The

parts are available in the PSOP package.

Dropout Voltage: 75 mV (typ) @ 0.8A load current.

Quiescent Current: 30 mA (typ) at full load.

Shutdown Current: 30 nA (typ) when S/D pin is low.

Precision Reference Voltage: 1.5% room temperature ac-

curacy.

Features

■Ideal for conversion from 1.8V or 1.5V inputs

■Designed for use with low ESR ceramic capacitors

■Ultra low dropout voltage (75mV @ 0.8A typ)

■0.56V to 1.5V adjustable output range

■Load regulation of 0.1%/A (typ)

■30nA quiescent current in shutdown (typ)

■Low ground pin current at all loads

■Over temperature/over current protection

■Available in 8 lead PSOP package

■−40°C to +125°C junction temperature range

■UVLO disables output when VBIAS < 3.8V

Applications

■ASIC Power Supplies In:

- Desktops, Notebooks, and Graphics Cards, Servers

- Gaming Set Top Boxes, Printers and Copiers

■Server Core and I/O Supplies

■DSP and FPGA Power Supplies

■SMPS Post-Regulators

Typical Application Circuit

20117701

* Minimum value required if Tantalum capacitor is used (see Application Hints).

LP38841-ADJ 0.8A Ultra Low Dropout Linear Regulators

Stable with Ceramic Output Capacitors

Connection Diagram

20117735

PSOP-8, Top View

Pin Description

Number

Name

Description

1 ADJ The Adjust pin is used to set the regulated output voltage by connecting it to the external

resistors R1 and R2 (see Typical Application Circuit).

2 OUTPUT The regulated output voltage is connected to this pin.

3 BIAS The Bias pin is used to provide the low current bias voltage to the chip which operates

the internal circuitry and provides drive voltage for the N-FET.

4, 5 GND These are the power and analog grounds for the IC. Connect both pins to ground.

6 SHUTDOWN This provides a low power shutdown function which turns the regulated output OFF. Tie

to VBIAS if this function is not used.

7 INPUT

The high current input voltage which is regulated down to the nominal output voltage

must be connected to this pin. Because the bias voltage to operate the chip is provided

separately, the input voltage can be as low as a few hundred millivolts above the output

voltage.

8 N/C This pin is floating, it has no internal connection.

DAP DAP

The PSOP DAP is a thermal connection that is physically connected to the backside of

the die, and is used as a thermal connection to the PC Board copper. The DAP is not a

ground pin connection, but should be connected to ground potential.

Ordering Information

Order Number Package Type Package Drawing Supplied As

LP38841MR-ADJ PSOP-8 MRA08A 95 Units Tape and Reel

LP38841MRX-ADJ PSOP-8 MRA08A 2500 Units Tape and Reel

Block Diagram

20117724

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LP38841-ADJ

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C

Lead Temp. (Soldering, 5 seconds) 260°C

ESD Rating

Human Body Model (Note 3)

Machine Model (Note 9)

2 kV

200V

Power Dissipation (Note 2) Internally Limited

VIN Supply Voltage (Survival) −0.3V to +6V

VBIAS Supply Voltage (Survival) −0.3V to +7V

Shutdown Input Voltage (Survival) −0.3V to +7V

VADJ -0.3V to +6V

IOUT (Survival) Internally Limited

Output Voltage (Survival) −0.3V to +6V

Junction Temperature −40°C to +150°C

Operating Ratings

VIN Supply Voltage (VOUT + VDO) to 5.5V

Shutdown Input Voltage 0 to +5.5V

IOUT 0.8A

Operating Junction

Temperature Range

−40°C to +125°C

VBIAS Supply Voltage 4.5V to 5.5V

VOUT 0.56V to 1.5V

Electrical Characteristics Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over

the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA,

CIN = 10 µF CER, COUT = 22 µF CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical correlation, or design.

Symbol Parameter Conditions MIN

TYP

(Note

MAX Units

VADJ Adjust Pin Voltage 10 mA < IL < 0.8A

VO(NOM) + 1V ≤ VIN ≤ 5.5V

4.5V ≤ VBIAS ≤ 5.5V

0.552 0.56 0.568

0.543 0.577

IADJ Adjust Pin Bias Current 10 mA < IL < 0.8A

VO(NOM) + 1V ≤ VIN ≤ 5.5V

4.5V ≤ VBIAS ≤ 5.5V

1 µA

ΔVO/ΔVIN Output Voltage Line Regulation

(Note 6)

VO(NOM) + 1V ≤ VIN ≤ 5.5V 0.01 %/V

ΔVO/ΔILOutput Voltage Load Regulation

(Note 7)

10 mA < IL < 0.8A 0.1 0.4

1.3 %/A

VDO Dropout Voltage (Note 8) IL = 0.8A 75 120

205 mV

IQ(VIN) Quiescent Current Drawn from

VIN Supply

10 mA < IL < 0.8A 30 35

40 mA

V S/D ≤ 0.3V 0.06 1

30 µA

IQ(VBIAS) Quiescent Current Drawn from

VBIAS Supply

10 mA < IL < 0.8A 2 4

6mA

V S/D ≤ 0.3V 0.03 1

30 µA

UVLO VBIAS Voltage Where Regulator

Output Is Enabled

3.8 V

ISC Short-Circuit Current VOUT = 0V 2.6 A

Shutdown Input

VSDT Output Turn-off Threshold Output = ON 0.7 1.3 V

Output = OFF 0.3 0.7

Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 µs

Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15

IS/D S/D Input Current V S/D =1.3V 1 µA

V S/D ≤ 0.3V −1

θJ-A Junction to Ambient Thermal

Resistance

PSOP-8 Package (Note 10) 43 °C/W

AC Parameters

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LP38841-ADJ

Symbol Parameter Conditions MIN

TYP

(Note

MAX Units

PSRR (VIN) Ripple Rejection for VIN Input

Voltage

VIN = VOUT +1V, f = 120 Hz 80

VIN = VOUT + 1V, f = 1 kHz 65

PSRR (VBIAS) Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz 58

VBIAS = VOUT + 3V, f = 1 kHz 58

Output Noise Density f = 120 Hz 1 µV/root−Hz

enOutput Noise Voltage

VOUT = 1.5V

BW = 10 Hz − 100 kHz 150 µV (rms)

BW = 300 Hz − 300 kHz 90

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device

is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not

apply when operating the device outside of its rated operating conditions.

Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. If power

dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.

Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.

Note 4: Typical numbers represent the most likely parametric norm for 25°C operation.

Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load.

Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value.

Note 9: The machine model is a 220 pF capacitor discharged directly into each pin.

Note 10: For optimum heat dissipation, the exposed DAP on the bottom of the PSOP package must be soldered to a copper plane or connected using thermal

vias to an internal copper plane.

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LP38841-ADJ

Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, CIN = 10 µF CER, COUT =

22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT + 1V.

VBIAS Transient Response

20117736

Dropout Voltage Over Temperature

20117739

VBIAS PSRR

20117741

VBIAS PSRR

20117751

VIN PSRR

20117742

VADJ / IADJ vs Temperature

20117760

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LP38841-ADJ

Load Transient Response

20117762

Load Transient Response

20117764

Application Hints

SETTING THE OUTPUT VOLTAGE

(Refer to Typical Application Circuit)

The output voltage is set using the resistive divider R1 and

R2. The output voltage is given by the formula:

VOUT = VADJ x (1 + R1 / R2)

The value of R2 must be 10k or less for proper operation.

EXTERNAL CAPACITORS

To assure regulator stability, input and output capacitors are

required as shown in the Typical Application Circuit.

OUTPUT CAPACITOR

An output capacitor is required on the LP3884X devices for

loop stability. The minimum value of capacitance necessary

depends on type of capacitor: if a solid Tantalum capacitor is

used, the part is stable with capacitor values as low as 4.7µF.

If a ceramic capacitor is used, a minimum of 22 µF of capac-

itance must be used (capacitance may be increased without

limit). The reason a larger ceramic capacitor is required is that

the output capacitor sets a pole which limits the loop band-

width. The Tantalum capacitor has a higher ESR than the

ceramic which provides more phase margin to the loop, there-

by allowing the use of a smaller output capacitor because

adequate phase margin can be maintained out to a higher

crossover frequency. The tantalum capacitor will typically al-

so provide faster settling time on the output after a fast chang-

ing load transient occurs, but the ceramic capacitor is superior

for bypassing high frequency noise.

The output capacitor must be located less than one centime-

ter from the output pin and returned to a clean analog ground.

Care must be taken in choosing the output capacitor to ensure

that sufficient capacitance is provided over the full operating

temperature range. If ceramics are selected, only X7R or X5R

types may be used because Z5U and Y5F types suffer severe

loss of capacitance with temperature and applied voltage and

may only provide 20% of their rated capacitance in operation.

INPUT CAPACITOR

The input capacitor is also critical to loop stability because it

provides a low source impedance for the regulator. The min-

imum required input capacitance is 10 µF ceramic (Tantalum

not recommended). The value of CIN may be increased with-

out limit. As stated above, X5R or X7R must be used to ensure

sufficient capacitance is provided. The input capacitor must

be located less than one centimeter from the input pin and

returned to a clean analog ground.

FEED FORWARD CAPACITOR

(Refer to Typical Application Circuit)

A capacitor placed across R1 can provide some additional

phase margin and improve transient response. The capacitor

CFF and R1 form a zero in the loop response given by the

formula:

FZ = 1 / (2 x π x CFF x R1)

For best effect, select CFF so the zero frequency is approxi-

mately 70 kHz. The phase lead provided by CFF drops as the

output voltage gets closer to 0.56V (and R1 reduces in value).

The reason is that CFF also forms a pole whose frequency is

given by:

FP = 1 / (2 x π x CFF x R1 // R2)

As R1 reduces, the two equations come closer to being equal

and the pole and zero begin to cancel each other out which

removes the beneficial phase lead of the zero.

BIAS CAPACITOR

The 0.1µF capacitor on the bias line can be any good quality

capacitor (ceramic is recommended).

BIAS VOLTAGE

The bias voltage is an external voltage rail required to get gate

drive for the N-FET pass transistor. Bias voltage must be in

the range of 4.5 - 5.5V to assure proper operation of the part.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the

regulator output from turning on if the bias voltage is below

approximately 3.8V.

SHUTDOWN OPERATION

Pulling down the shutdown (S/D) pin will turn-off the regulator.

The S/D pin must be actively terminated through a pull-up re-

sistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is

driven from a source that actively pulls high and low (such as

a CMOS rail to rail comparator), the pull-up resistor is not re-

quired. This pin must be tied to Vin if not used.

POWER DISSIPATION/HEATSINKING

Heatsinking for the PSOP-8 package is accomplished by al-

lowing heat to flow through the exposed DAP on the bottom

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LP38841-ADJ

of the package into the copper on the PC board. The exposed

DAP must be soldered down to a copper plane to get good

heat transfer. It can also be connected through thermal vias

to internal copper planes. Since the DAP is physically con-

nected to the backside of the die, it must be held at ground

potential. Under all possible conditions, the junction temper-

ature must be within the range specified under operating

conditions.

7 www.national.com

LP38841-ADJ

Physical Dimensions inches (millimeters) unless otherwise noted

PSOP-8 8-Lead Molded PSOP-2

NS Package Number MRA08B

www.national.com 8

LP38841-ADJ

Notes

9 www.national.com

LP38841-ADJ

Notes

LP38841-ADJ 0.8A Ultra Low Dropout Linear Regulators

Stable with Ceramic Output Capacitors

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