MOSEL VITELIC
1
V53C16256SH
256K X 16 FAST PAGE MODE
CMOS DYNAMIC RAM WITH
SELF REFRESH
PRELIMINARY
V53C16256SH Rev. 0.1 December 1998
HIGH PERFORMANCE 40 50
Max. RAS Access Time, (t
RAC
) 40 ns 50 ns
Max. Column Address Access Time, (t
CAA
) 20 ns 24 ns
Min. Fast Page Mode Cycle Time, (t
PC
) 23 ns 28 ns
Min. Read/Write Cycle Time, (t
RC
) 75 ns 90 ns
Features
■
256K x 16-bit organization
■
Fast Page Mode for a sustained data rate
of 43 MHz
■
RAS access time: 40, 50 ns
■
Dual CAS Inputs
■
Low power dissipation
■
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, and Self Refresh
■
Refresh Interval: 512 cycles/8 ms
■
Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
■
Single 5.0V
±
10% Power Supply
■
TTL Interface
■
Self Refresh: 512 cycles/8ms
Description
The V53C16256SH is a 262,144 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C16256SH offers Fast Page mode
with dual CAS inputs. An address, CAS and RAS in-
put capacitances are reduced to one quarter when
the x4 DRAM is used to construct the same memory
density. The V53C16256SH has symmetric ad-
dress and accepts 512 cycle 8ms interval.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 23ns.
The V53C16256SH is best suited for graphics,
and DSP applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns) Power Temperature
Mark
K T 40 50 Std.
0
°
C to 70
°
C • • • • • Blank
2
V53C16256SH Rev. 0.1 December 1998
MOSEL VITELIC
V53C16256SH
40-Pin Plastic SOJ
PIN CONFIGURATION
Top View
40/44 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
5
6
7
8
9
10
11
12
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
16256L-02
39
40
38
37
36
35
34
33
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
5
6
7
8
9
10
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
16256L-03
43
44
42
41
40
39
38
37
36
35
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Pin Names
A
0
–A
8
Address Inputs
RAS Row Address Strobe
UCAS Column Address Strobe Upper Byte Control
LCAS Column Address Strobe Lower Byte Control
WE Write Enable
OE Output Enable
I/O
1
–I/O
16
Data Input, Output
V
CC
+3.3V Supply
V
SS
0V Supply
NC No Connect
3
MOSEL VITELIC
V53C16256SH
V53C16256SH Rev. 0.1 December 1998
Absolute Maximum Ratings*
Ambient Temperature
Under Bias................................ –10
°
C to +80
°
C
Storage Temperature (plastic)..... –55
°
C to +125
°
C
Voltage Relative to V
SS
.................–1.0 V to +7.0 V
Data Output Current .....................................50 mA
Power Dissipation..........................................1.0 W
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
°
C, V
CC
= 5.0 V
±
10%, V
SS
= 0 V
* Note:
Capacitance is sampled and not 100% tested
Symbol Parameter Typ. Max. Unit
C
IN1
Address Input 3 4 pF
C
IN2
RAS, UCAS, LCAS,
WE, OE 45pF
C
OUT
Data Input/Output 5 7 pF
Block Diagram
A0
A1
A7
A8
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
9
I/O1
ADDRESS BUFFERS
AND PREDECODERS
X0-X
ROW
DECODERS
512
MEMORY
ARRAY
COLUMN DECODERS
DATA I/O BUS
Y0-Y8
512 x 16
I/O
BUFFER
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
RAS CLOCK
GENERATOR
OE
WE
LCAS
RAS
•••
8
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
UCAS
256K x 16
16256L-04
4
V53C16256SH Rev. 0.1 December 1998
MOSEL VITELIC
V53C16256SH
DC and Operating Characteristics
(1-2)
T
A
= 0
°
C to 70
°
C, V
CC
= 5V
±
5%, V
SS
= 0 V, unless otherwise specified.
Symbol Parameter Access
Time
V53C16256SH
Unit Test Conditions NotesMin. Typ. Max.
I
LI
Input Leakage Current
(any input pin) –10 10
µ
AV
SS
≤
V
IN
≤
V
CC
I
LO
Output Leakage Current
(for High-Z State) –10 10
µ
AV
SS
≤
V
OUT
≤
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating 40 180 mA t
RC
= t
RC
(min.) 1, 2
50 160
I
CC2
V
CC
Supply Current,
TTL Standby 2 mA RAS, CAS at V
IH
other inputs
≥
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh 40 180 mA t
RC
= t
RC
(min.) 2
50 160
I
CCS
Self Refresh Current 400
µ
A RAS, LCAS, UCAS = 0.2V
A0 – A8 = V
CC
– 0.2V or 0.2V
I
CC4
V
CC
Supply Current,
Fast Page Mode Operation 40 170 mA Minimum Cycle 1, 2
50 150
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
other inputs
≥
V
SS
2 mA RAS=V
IH
, CAS=V
IL
1
I
CC6
V
CC
Supply Current,
CMOS Standby 1 mA RAS
≥
V
CC
– 0.2 V,
CAS
≥
V
CC
– 0.2 V,
All other inputs
≥
V
SS
V
CC
Supply Voltage 4.75 5.0 5.25 V
V
IL
Input Low Voltage –1 0.8 V 3
V
IH
Input High Voltage 2.0 V
CC
+1 V 3
V
OL
Output Low Voltage 0.4 V I
OL
= 2.0 mA
V
OH
Output High Voltage 2.4 V I
OH
= –2.0 mA
5
MOSEL VITELIC
V53C16256SH
V53C16256SH Rev. 0.1 December 1998
AC Characteristics
T
A
= 0
°
C to 70
°
C, V
CC
= 5V
±
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
# Symbol Parameter
40 50
Unit NotesMin. Max. Min. Max.
1t
RAS RAS Pulse Width 40 75 50 75K ns
2t
RC Read or Write Cycle Time 75 90 ns
3t
RP RAS Precharge Time 25 30 ns
4t
CSH CAS Hold Time 40 50 ns
5t
CAS CAS Pulse Width 12 14 ns
6t
RCD RAS to CAS Delay 17 28 19 36 ns
7t
RCS Read Command Setup Time 0 0 ns 4
8t
ASR Row Address Setup Time 0 0 ns
9t
RAH Row Address Hold Time 7 9 ns
10 tASC Column Address Setup Time 0 0 ns
11 tCAH Column Address Hold Time 5 7 ns
12 tRSH (R) RAS Hold Time (Read Cycle) 12 14 ns
13 tCRP CAS to RAS Precharge Time 5 5 ns
14 tRCH Read Command Hold Time Referenced to CAS 0 0 ns 5
15 tRRH Read Command Hold Time Referenced to RAS 0 0 ns 5
16 tROH RAS Hold Time Referenced to OE 810ns
17 tOAC Access Time from OE 12 14 ns
18 tCAC Access Time from CAS 12 14 ns 6, 7
19 tRAC Access Time from RAS 45 55 ns 6, 8, 9
20 tCAA Access Time from Column
Address 20 24 ns 6, 7, 10
21 tLZ OE or CAS to Low-Z Output 0 0 ns 16
22 tHZ OE or CAS to High-Z Output 0608ns16
23 tAR Column Address Hold Time from RAS 30 40 ns
24 tRAD RAS to Column Address Delay Time 12 20 14 26 ns 11
25 tRSH (W) RAS or CAS Hold Time in Write Cycle 12 14 ns
26 tCWL Write Command to CAS Lead Time 12 14 ns
27 tWCS Write Command Setup Time 0 0 ns 12, 13
28 tWCH Write Command Hold Time 5 7 ns
29 tWP Write Pulse Width 5 7 ns
30 tWCR Write Command Hold Time from RAS 30 40 ns
31 tRWL Write Command to RAS Lead Time 12 14 ns
32 tDS Data in Setup Time 0 0 ns 14
6
V53C16256SH Rev. 0.1 December 1998
MOSEL VITELIC
V53C16256SH
33 tDH Data in Hold Time 5 7 ns 14
34 tWOH Write to OE Hold Time 6 8 ns 14
35 tOED OE to Data Delay Time 6 8 ns 14
36 tRWC Read-Modify-Write Cycle Time 110 130 ns
37 tRRW Read-Modify-Write Cycle RAS Pulse
Width 75 87 ns
38 tCWD CAS to WE Delay 30 34 ns 12
39 tRWD RAS to WE Delay in Read-Modify-Write
Cycle 58 68 ns 12
40 tCRW CAS Pulse Width (RMW) 48 52 ns
41 tAWD Col. Address to WE Delay 38 42 ns 12
42 tPC Fast Page Mode Read or Write Cycle
Time 23 28 ns
43 tCP CAS Precharge Time 5 7 ns
44 tCAR Column Address to RAS Setup Time 20 24 ns
45 tCAP Access Time from Column Precharge 22 27 ns 7
46 tDHR Data in Hold Time Referenced to RAS 30 40 ns
47 tCSR CAS Setup Time CAS-before-RAS
Refresh 10 10 ns
48 tRPC RAS to CAS Precharge Time 0 0 ns
49 tCHR CAS Hold Time CAS-before-RAS
Refresh 812ns
50 tPCM Fast Page Mode Read-Modify-Write
Cycle Time 60 70 ns
51 tTTransition Time (Rise and Fall) 3 50 3 50 ns 15
52 tREF Refresh Interval (512 Cycles) 8 8 ms 17
53 tREF Self Refresh 8 8 ms
54 tRASS RAS Pulse Width During Self Refresh 100 100 µs18
55 tRPS RAS Precharge Time During Self Refresh 100 100 ns 18
56 tCHS CAS Hold Time Width During Self Refresh 100 100 ns 18
57 tCHD CAS Low Time During Self Refresh 100 100 ns 18
# Symbol Parameter
40 50
Unit NotesMin. Max. Min. Max.
AC Characteristics
(Cont’d)
7
MOSEL VITELIC
V53C16256SH
V53C16256SH Rev. 0.1 December 1998
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in Fast Page Mode.
3. Specified VIL
(min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. t
RCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD ex-
ceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
18. One CBR refresh or complete set of row refresh cycles must be completed upon existing Self Refresh Mode.
8
V53C16256SH Rev. 0.1 December 1998
MOSEL VITELIC
V53C16256SH
Truth Table
Notes:
1. Byte Write cycles LCAS or UCAS active.
2. Byte Read cycles LCAS or UCAS active.
3. Only one of the two CAS must be active (LCAS or UCAS).
Function RAS LCAS UCAS WE OE ADDRESS I/O Notes
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL Data Out
Read: Lower Byte L L H H L ROW/COL Lower Byte, Data-Out
Upper Byte, High-Z
Read: Upper Byte LHLHLROW/COL Lower Byte, High-Z
Upper Byte, Data-Out
Write: Word (Early-Write) LLLLXROW/COL Data-In
Write: Lower Byte (Early) L L H L X ROW/COL Lower Byte, Data-In
Upper Byte, High-Z
Read: Upper Byte (Early) L H L L X ROW/COL Lower Byte, High-Z
Upper Byte, Data-In
Read-Write L L L H→LL→H ROW/COL Data-Out, Data-In 1, 2
Fast Page-Mode Read L H→LH→L H L COL Data-Out 2
Fast Page-Mode Write L H→LH→L L X COL Data-In 2
Fast Page-Mode Read-Write L H→LH→LH→LL→H COL Data-Out, Data-In 1, 2
Hidden Refresh Read L→H→L L L H L ROW/COL Data-Out 2
RAS-Only Refresh L H H X X ROW High-Z
CBR Refresh H→L L L X X High-Z 3
Self Refresh H→LHHHH High-Z
9
MOSEL VITELIC
V53C16256SH
V53C16256SH Rev. 0.1 December 1998
Waveforms of Read Cycle
Waveforms of Early Write Cycle
IH
V
IL
V
RAS
IH
V
IL
V
IH
V
IL
V
tRC (2)
tRAS (1)
tAR (23)
tRP (3)
tCRP (13)
tCSH (4) tRSH (R)(12)
tCAS (5)
tRCD (6)
tCRP (13)
tCAH (11)
tASC (10)
tRAD (24)
tRAH (9)
tASR (8)
tRCS (7)
tRCH (14)
tRRH (15)
tCAR (44)
tCAA (20)
tCAC (18)
ttHZ (22)
tLZ (21)
IH
V
IL
V
WE
OH
V
OL
V
I/O
16256L-05
VALID DATA-OUT
ADDRESS
RAC (19)
COLUMN ADDRESSROW ADDRESS
tOAC (17)
tHZ (22)
IH
V
IL
V
OE
tROH (16)
UCAS, LCAS
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
tRC (2)
tRAS (1)
tAR (23)
tRP (3)
tCRP (13)
tCSH (4) tRSH (W)(25)
tCAS (5)
tRCD (6)
tCRP (13)
tCAH (11)
t
tRAD (24)
tRAH (9)
tASR (8)
t
tWCR (30) tRWL (31)
tDH (33)
tDHR (46)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V16256L-06
t
tCWL (26) WCH (28)
t
tDS (32)
COLUMN ADDRESS
VALID DATA-IN HIGH-Z
RAS
WE
OE
I/O
ADDRESS
tCAR (44)
ASC (10)
WCS (27)
WP (29)
ROW ADDRESS
UCAS, LCAS
Don’t Care Undefined
10
V53C16256SH Rev. 0.1 December 1998
MOSEL VITELIC
V53C16256SH
Waveforms of OE-Controlled Write Cycle
Waveforms of Read-Modify-Write Cycle
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
tRC (2)
tRAS (1)
tAR (23)
tRP (3)
tCRP (13)
tRCD (6)
tCRP (13)
tCAH (11)
tASC (10)
tRAH (9)
tASR (8)
ROW ADDRESS COLUMN ADDRESS
tWOH (34)
tDH (33)
tOED (35)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
16256L-07
VALID DATA-IN
tDS (32)
tRAD (24)
RAS
WE
OE
I/O
tCSH (4)
ADDRESS
tCAR (44)
t
tCAS (5)
RSH (W)(12)
tWP (29)
RWL (31)
tCWL (26)
t
UCAS, LCAS
COLUMN
ADDRESS
ROW
ADDRESS
V
V
IH
V
IL
V
IH
V
IL
V
tRP (3)
tCRP (13)
tRCD (6)
tCRP (13)
tCAH (11)
tASC (10)
tRAH (9)
tASR (8)
WP (29)
RWL (31)
tOED (35)
t
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
16256L-08
VALID
DATA-OUT
tRAC (19)
tCWL (26)
t
tRAD (24)
t
tOAC (17)
ttDH (33)
tDS (32)
HZ (22)CAC (18)
tLZ (21)
VALID
DATA-IN
IH
V
IL
V
OH
OL
RAS
WE
OE
I/O
ADDRESS
tRWC (36)
tRRW (37)
tAR (23)
tCSH (4) tRSH (W)(25)
tCRW (40)
tRWD (39) CWD (38)
tAWD (41)
t
tCAA (20)
UCAS, LCAS
Don’t Care Undefined
11
MOSEL VITELIC
V53C16256SH
V53C16256SH Rev. 0.1 December 1998
Waveforms of Fast Page Mode Read Cycle
Waveforms of Fast Page Mode Write Cycle
VALID
DATA OUT
VALID
DATA OUT
COLUMN
ADDRESS
CAC (18)
t
t
HZ (22)
HZ (22)
HZ (22)
HZ (22)
ROW
ADDRESS COLUMN
ADDRESS
IH
V
IL
V
IH
V
IL
V
RP (3)
t
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
t
RAH (9)
t
ASR (8)
t
RCS (7)
t
RCH (14)
t
CSH (4)
16256L-09
IH
V
IL
V
CP (43)
t
ASC (10)
RCD (6)
t
t
RAS (1)
t
RSH (R)(12)
t
CAS (5)
t
CAH (11)
t
HZ (22)
t
t
AR (23)
t
CAS (5)
t
CAS (5)
PC (42)
t
CRP (13)
t t
COLUMN
ADDRESS
t
t
CAR (44)
t
CAH (11)
t
RCS (7)
t
RCS (7)
t
RCH (14)
t
OAC (17)
t
tt
OAC (17)
t
CAA (20)
t
RRH (15)
t
HZ (22)
LZ (21)
t
RAC (19)
t
t
CAC (18)
VALID
DATA OUT
t
CRP (13)
tt
LZ (21)
t
RAS
CAS
WE
OE
I/O
ADDRESS
t
ASC (10)
t
LZ (21)
CAC (18)
t
CAA (20)
OAC (17)
CAP (45)
t
CAH (11)
ROW
ADD
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
t
tASR (8)
16256L-10
IH
V
IL
V
CP (43)
tASC (10)
RCD (6)
tRSH (W)(25)
COLUMN
ADDRESS
tCAH (11)
tCAS (5) tCAS (5)
tCAR (44)
tRAD (24) tCWL (26)
VALID
DATA IN
tCRP (13)
tWCS (27)
WP (29)
tCAH (11)
tASC (10) tCAH (11)
tDH (33)
tDS (32)
IH
V
IL
V
COLUMN
ADDRESS
RAH (9)
COLUMN
ADDRESS
tCRP (13)
t
tWCH (28)
tCWL (26)
tWCS (27)
WP (29)
tWCH (28)
t
tCWL (26)
tWCS (27)
WP (29)
tWCH (28)
t
VALID
DATA IN
tDH (33)
tDS (32)
VALID
DATA IN
tDH (33)
tDS (32)
tRP (3)
tAR (23)
RAS
UCAS, LCAS
WE
OE
I/O
ADDRESS
OPENOPEN
tRWL (31)
t
tCSH (4)
tRAS (1)
t
PC (42)
tt
CAS (5)
Don’t Care Undefined
12
V53C16256SH Rev. 0.1 December 1998
MOSEL VITELIC
V53C16256SH
Waveforms of Fast Page Mode Read-Write Cycle
Waveforms of RAS-Only Refresh Cycle
ROW
ADD
IH
V
IL
V
IH
V
IL
V
RP (3)
t
IH
V
IL
V
I/OH
V
I/OL
V
t
t
ASR (8)
COLUMN
ADDRESS
16256L-11
IH
V
IL
V
CP (43)
t
ASC (10)
RCD (6)
t
t
RAS (1)
t
RSH (W)(25)
COLUMN
ADDRESS
t
CAH (11)
t
CAS (5)
t
CAS (5)
t
t
t
CRP (13)
t
RCS (7)
t
CAH (11)
t
ASC (10)
t
t
CWD (38)
t
LZ (21)
IH
V
IL
V
COLUMN
ADDRESS
t
ASC (10)
RAH (9)
t
WP (29)
t
CWL (26)
t
t
CWL (26)
t
RWL (31)
t
AWD (41)
t
CAA (20)
tt
OAC (17)
t
AWD (41)
t
OAC (17)
IN
t
CAC (18)
t
OED (35)
t
DS (32)
t
DH (33)
t
LZ (21)
IN
OUT
HZ (22)
t
OED (35)
DS (32)
t
DH (33)
t
t
t
t
CAC (18)
t
CAA (20)
LZ (21)
IN
HZ (22)
t
OED (35)
DS (32)
t
DH (33)
t
t
t
CAC (18)
t
CAA (20)
t
t
WP (29)
tt
WP (29)
t
CWL (26)
t
CAR (44)
t
RAD (24)
RAS
UCAS, LCAS
WE
OE
I/O
ADDRESS
t
AWD (41)
OUT
RAC (19)
t
OAC (17)
t
RWD (39)
CAH (11)
PCM (50)
t
t
CSH (4)
t
CAS (5)
t
CWD (38)
HZ (22)
CWD (38)
OUT
CAP (45) CAP (45)
IH
V
IL
V
RAS
IH
V
IL
V
RP (3)
t
IH
V
IL
V
UCAS, LCAS
tRAS (1)
tRC (2)
tCRP (13)
tASR (8) tRAH (9)
16256L-12
WE, OE = Don’t careNOTE:
ADDRESS
ROW ADDR
Don’t Care Undefined
13
MOSEL VITELIC
V53C16256SH
V53C16256SH Rev. 0.1 December 1998
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
Waveforms of CAS-before-RAS Refresh Cycle
IH
V
IL
V
IH
V
IL
V
RP (3)
t
IH
V
IL
V
t
CSR (47)
t
RSH (W)(25)
16256L-13
t
RAS (1)
t
CHR (49)
t
RCS (7)
t
WCS (27)
t
LZ (21)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Vt
DH (33)
t
CP (43)
t
CAS (5)
t
RCH (14)
t
RRH (15)
t
ROH (16)
t
OAC (17)
t
HZ (22)
t
HZ (22)
t
RWL (31)
t
CWL (26)
t
DS (32)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
READ CYCLE
WRITE CYCLE t
WCH (28)
I/O
ADDRESS
WE
WE
I/O D
OUT
D
IN
RAS
UCAS, LCAS
OE
OE
I/O
IH
V
IL
V
RAS
OH
V
OL
V
UCAS, LCAS
IH
V
IL
V
t
RAS (1)
t
RC (2)
t
CP (43)
t
HZ (22)
t
CSR (47)
16256L-14
RP (3)
t
t
RPC (48)
t
CHR (49)
RP (3)
t
WE, OE, = Don’t care
NOTE: A –A
08
Don’t Care Undefined
14
V53C16256SH Rev. 0.1 December 1998
MOSEL VITELIC
V53C16256SH
Waveforms of Hidden Refresh Cycle (Read)
Waveforms of Hidden Refresh Cycle (Write)
IH
V
IL
V
OH
V
OL
V
RP (3)
t
IH
V
IL
V
tASR (8)
tCRP (13)
tRCD (6) tRSH (R)(12)
tRCS (7)
16256L-15
tCHR (49)
tRAD (24)
tASC (10)
t tCAH (11)
ROW
ADD COLUMN
ADDRESS
tRRH (15)
tOAC (17)
tLZ (21)
tHZ (22)
tHZ (22)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
RAS
UCAS, LCAS
WE
OE
I/O
ADDRESS
VALID DATA
RAH (9)
tCAA (20)
tCAC (18)
tRAC (19)
tRAS (1)RP (3)
t
tRAS (1)
tAR (23)
tCRP (13)
tRC (2) tRC (2)
IH
V
IL
V
IH
V
IL
V
RP (3)
t
IH
V
IL
V
t
RAS (1)
t
RC (2)
t
ASR (8)
t
CRP (13)
RP (3)
t
t
RCD (6)
t
RSH (12)
t
WCS (27)
16256L-16
t
RAS (1)
t
AR (23)
t
CHR (49)
t
CRP (13)
t
RAD (24)
t
ASC (10)
t
RAH (9)
t
CAH (11)
ROW
ADD COLUMN
ADDRESS
t
WCH (28)
t
DS (32)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
VALID DATA-IN
t
DHR (46)
t
RC (2)
RAS
UCAS, LCAS
WE
OE
I/O
ADDRESS
t
DH (33)
Don’t Care Undefined
15
MOSEL VITELIC
V53C16256SH
V53C16256SH Rev. 0.1 December 1998
Waveforms of CAS before RAS Refresh Cycle
HI-Z
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
UCAS
tRP tRASS tRPS
tRPC
tCP
tCSR tCHS tCRP
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tWRP tWRH
tCDD
tODD
tOEZ
tOFF
LCAS
MOSEL VITELIC
V53C16256SH
16
V53C16256SH Rev. 0.1 December 1998
Functional Description
The V53C16256SH is a CMOS dynamic RAM op-
timized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C16256SH reads and
writes data by multiplexing an 18-bit address into a
9-bit row and a 9-bit column address. The row ad-
dress is latched by the Row Address Strobe (RAS).
The column address “flows through” an internal ad-
dress buffer and is latched by the Column Address
Strobe (CAS). Because access time is primarily de-
pendent on a valid column address rather than the
precise time that the CAS edge occurs, the delay
time from RAS to CAS has little effect on the access
time.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be end-
ed or aborted before the minimum tRAS time has ex-
pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
mum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For exam-
ple, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
Fast Page Mode Operation
Fast Page Mode operation permits all 512 col-
umns within a selected row of the device to be ran-
domly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates the
need to reapply it for each cycle. The column ad-
dress buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating tASC
and tT from the critical timing path. CAS latches the
address into the column address buffer and acts as
an output enable. During Fast Page Mode opera-
tion, Read, Write, Read-Modify-Write or Read-
Write-Read cycles are possible at random address-
es within a row. Following the initial entry cycle into
Fast Page Mode, access is tCAA or tCAP controlled.
If the column address is valid prior to the rising edge
of CAS, the access time is referenced to the CAS
rising edge and is specified by tCAP. If the column
address is valid after the rising CAS edge, access
is timed from the occurrence of a valid address and
is specified by tCAA. In both cases, the falling edge
of CAS latches the address and enables the output.
Fast Page Mode provides a sustained data rate of
43 MHz for applications that require high data rates
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
Self Refresh
Self Refresh mode provides internal refresh con-
trol signals to the DRAM during extended periods of
inactivity. Device operation in this mode provides
additional power savings and design ease by elimi-
nation of external refresh control signals. Self Re-
fresh mode is initialed with a CAS before RAS
(CBR) Refresh cycle, holding both RAS low (tRASS)
and CAS low (tCHD) for a specified period. Both of
these parameters are specified with minimum val-
ues to guarantee entry into Self Refresh operation.
Once the device has been placed in to Self Refresh
mode the CAS clock is no longer required to main-
tain Self Refresh operation.
Data Rate 512
tRC 511 tPC
×+
----------------------------------------=
17
MOSEL VITELIC
V53C16256SH
V53C16256SH Rev. 0.1 December 1998
The Self Refresh mode is terminated by returning
the RAS clock to a high level for a specified (tRPS)
minimum time. After termination of the Self Refresh
cycle normal accesses to the device may be initiat-
ed immediately, poviding that subsequest refresh
cycles utilize the CAS before RAS (CBR) mode of
operation.
Data Output Operation
The V53C16256SH Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition en-
ables the transfer of data to and from the selected
row address in the Memory Array. A RAS high tran-
sition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level dis-
ables the I/O path and the output driver if it is en-
abled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output driv-
ers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is neces-
sary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C16256SH is dependent on the input levels
of RAS and CAS. If RAS is low during Power-On,
the device will go into an active cycle and ICC will ex-
hibit current transients. It is recommended that RAS
and CAS track with VCC or be held at a valid VIH dur-
ing Power-On to avoid current surges.
Table 1. V53C16256SH Data Output
Operation for Various Cycle Types
Cycle Type I/O State
Read Cycles Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write) High-Z
WE-Controlled Write
Cycle (Late Write) OE Controlled. High
OE = High-Z I/Os
Read-Modify-Write
Cycles Data from Addressed
Memory Cell
Fast Page Mode Read Data from Addressed
Memory Cell
Fast Page Mode Write
Cycle (Early Write) High-Z
Fast Page Mode Read-
Modify-Write Cycle Data from Addressed
Memory Cell
RAS-only Refresh High-Z
CAS-before-RAS
Refresh Cycle Data remains as in
previous cycle
CAS-only Cycles High-Z
18
V53C16256SH Rev. 0.1 December 1998
MOSEL VITELIC
V53C16256SH
Package Diagrams
40-Pin Plastic SOJ
40/44L-Pin TSOP-II
1.025 TYP. (1.035 MAX.)
[26.04 TYP. (26.29 MAX.)]
0.050 ± 0.006
[1.27 ± 0.152] 0.04 [0.1]
0.026 MIN
[0.660 MIN]
0.144 MAX
[3.66 MAX]
0.400 ±0.005
[10.16 ± 0.127]
0.440 ±0.005
[11.18 ± 0.127]
40
1
21
20
0.368 ± 0.010
[9.35 ± 0.254]
0.010
Unit in inches [mm]
0.025
0.018 +0.004
–0.002
+0.004
–0.002 0.635 +0.102
–0.051
+ 0.004
– 0.002
0.254 +0.102
–0.051
0.457 +0.102
–0.051
0.721 – 0.729
[18.31 – 18.52]
0.0315 BSC
[.8001 BSC]
40 21
120
0.039 – 0.047
[0.991 – 1.193]
0.396 – 0.404
[10.06 – 10.26]
0.462 – 0.470
[11.73 – 11.94]
0.012 – 0.016
[0.305 – 0.406] 0.002 – 0.008
[0.051 – 0.203]
0.0047 – 0.0083
[0.119 – .211]
0°–5°
0.017 – 0.023
[0.432 – 0.584]
BASE PLANE
SEATING PLANE
Unit in inches [mm]
MOSEL VITELIC
WORLDWIDE OFFICES V53C16256SH
© Copyright 1998, MOSEL VITELIC Inc. 12/98
Printed in U.S.A.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
U.S. SALES OFFICES
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
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100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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