MSP430G2x52
MSP430G2x12
www.ti.com
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
MIXED SIGNAL MICROCONTROLLER
1FEATURES
23 Low Supply Voltage Range: 1.8 V to 3.6 V Universal Serial Interface (USI) Supporting SPI
and I2C
Ultra-Low Power Consumption 10-Bit 200-ksps Analog-to-Digital (A/D)
Active Mode: 220 µA at 1 MHz, 2.2 V Converter With Internal Reference, Sample-
Standby Mode: 0.5 µA and-Hold, and Autoscan (MSP430G2x52 Only)
Off Mode (RAM Retention): 0.1 µA On-Chip Comparator for Analog
Five Power-Saving Modes Brownout Detector
Ultra-Fast Wake-Up From Standby Mode in Serial Onboard Programming,
Less Than 1 µs No External Programming Voltage Needed,
16-Bit RISC Architecture, 62.5-ns Instruction Programmable Code Protection by Security
Cycle Time Fuse
Basic Clock Module Configurations On-Chip Emulation Logic With Spy-Bi-Wire
Internal Frequencies up to 16 MHz With Interface
Four Calibrated Frequencies Family Members are Summarized in Table 1
Internal Very-Low-Power Low-Frequency Package Options
(LF) Oscillator TSSOP: 14 Pin, 20 Pin
32-kHz Crystal PDIP: 20 Pin
External Digital Clock Source QFN: 16 Pin
One 16-Bit Timer_A With Three For Complete Module Descriptions, See the
Capture/Compare Registers MSP430x2xx Family User’s Guide (SLAU144)
Up to 16 Touch-Sense Enabled I/O Pins
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2x52 and MSP430G2x12 series of microcontrollers are ultra-low-power mixed signal
microcontrollers with built-in 16-bit timers, and up to 16 I/O touch sense enabled pins and built-in communication
capability using the universal serial communication interface and have a versatile analog comparator. The
MSP430G2x52 series have a 10-bit A/D converter. For configuration details see Table 1. Typical applications
include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the
data for display or for transmission to a host system.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2MSP430 is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430G2x52
MSP430G2x12
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
www.ti.com
Table 1. Available Options(1)
Flash RAM Comp_A ADC10 Package
Device EEM Timer_A USI Clock I/O
(KB) (B) Channel Channel Type(2)
MSP430G2452IN20 16 20-PDIP
MSP430G2452IPW20 16 20-TSSOP
1 8 256 1x TA3 8 8 1 LF, DCO, VLO
MSP430G2452IRSA16 10 16-QFN
MSP430G2452IPW14 10 14-TSSOP
MSP430G2352IN20 16 20-PDIP
MSP430G2352IPW20 16 20-TSSOP
1 4 256 1x TA3 8 8 1 LF, DCO, VLO
MSP430G2352IRSA16 10 16-QFN
MSP430G2352IPW14 10 14-TSSOP
MSP430G2252IN20 16 20-PDIP
MSP430G2252IPW20 16 20-TSSOP
1 2 256 1x TA3 8 8 1 LF, DCO, VLO
MSP430G2252IRSA16 10 16-QFN
MSP430G2252IPW14 10 14-TSSOP
MSP430G2152IN20 16 20-PDIP
MSP430G2152IPW20 16 20-TSSOP
1 1 128 1x TA3 8 8 1 LF, DCO, VLO
MSP430G2152IRSA16 10 16-QFN
MSP430G2152IPW14 10 14-TSSOP
MSP430G2412IN20 16 20-PDIP
MSP430G2412IPW20 16 20-TSSOP
1 8 256 1x TA3 8 - 1 LF, DCO, VLO
MSP430G2412IRSA16 10 16-QFN
MSP430G2412IPW14 10 14-TSSOP
MSP430G2312IN20 16 20-PDIP
MSP430G2312IPW20 16 20-TSSOP
1 4 256 1x TA3 8 - 1 LF, DCO, VLO
MSP430G2312IRSA16 10 16-QFN
MSP430G2312IPW14 10 14-TSSOP
MSP430G2212IN20 16 20-PDIP
MSP430G2212IPW20 16 20-TSSOP
1 2 256 1x TA3 8 - 1 LF, DCO, VLO
MSP430G2212IRSA16 10 16-QFN
MSP430G2212IPW14 10 14-TSSOP
MSP430G2112IN20 16 20-PDIP
MSP430G2112IPW20 16 20-TSSOP
1 1 128 1x TA3 8 - 1 LF, DCO, VLO
MSP430G2112IRSA16 10 16-QFN
MSP430G2112IPW14 10 14-TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated
1
DVCC
2
3
4
5
6
78
9
10 RST/NMI/SBWTDIO
11 TEST/SBWTCK
12 XOUT/P2.7
13 XIN/P2.6/TA0.1
14 DVSS
P1.0/TA0CLK/ACLK/A0/CA0
P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA3
P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLK
P1.7 /CA7/TDO/TDI/SDI/SDA/CAOUT/A7
P1.1/TA0.0/A1/CA1
P1.2/TA0.1/A2/CA2
P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/CA4/TCK
P1.5/TA0.0/SCLK/A5/CA5/TMS
1
2
3
4
5 6 7 8
9RST/NMI/SBWTDIO
10 TEST/SBWTCK
11 XOUT/P2.7
12 XIN/P2.6/TA0.1
13
AVSS
14
DVSS
15
AVCC
16
DVCC
P1.0/TA0CLK/ACLK/A0/CA0
P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA3
P1.6/TA0.1/SDO/SCL/A6/CA6TDI/TCLK/
P1.7/ /TDO/TDISDI/SDA/CAOUT/A7/CA7
P1.1/TA0.0/A1/CA1
P1.2/TA0.1/A2/CA2
P1.4/SMCLK/A4/VREF+/VEREF+/CA4/TCK
P1.5/TA0.0/SCLK/A5/CA5/TMS
1
DVCC
2
P1.0/TA0CLK/ACLK/A0/CA0
3
4
5
P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3
6
7
8
P2.0
9
P2.1
10
P2.2 11 P2.3
12 P2.4
13 P2.5
14
15
16 RST/NMI/SBWTDIO
17 TEST/SBWTCK
18 XOUT/P2.7
19 XIN/P2.6/TA0.1
20 DVSS
P1.6/TA0.1/ TDI/TCLKSDO/SCL/A6/CA6/
P1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDI
P1.1/TA0.0/A1/CA1
P1.2/TA0.1/A2/CA2
P1.4/TA0.2/SMCLK/A4/ CA4/TCKVREF+/VEREF+/
P1.5/TA0.0 A5/CA5/TMS/SCLK/
MSP430G2x52
MSP430G2x12
www.ti.com
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
DEVICE PINOUTS
PW PACKAGE
(TOP VIEW)
NOTE: ADC10 pin functions are available only on MSP430G2x52.
NOTE: The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = 1.
RSA PACKAGE
(TOP VIEW)
NOTE: ADC10 pin functions are available only on MSP430G2x52.
NOTE: The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = 1.
N OR PW PACKAGE
(TOP VIEW)
NOTE: ADC10 pin functions are available only on MSP430G2x52.
Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A3
3 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
Port P1
8 I/O
Interrupt
capability
pullup/down
resistors
P1.x
8
Spy-Bi
Wire
XIN XOUT
RAM
256B
256B
256B
128B
Flash
8KB
4KB
2KB
1KB
Comp_A+
8 Channels
P2.x
Port P2
up to 8 I/O
Interrupt
capability
pullup/down
resistors
up to 8
USI
Universal
Serial
Interface
SPI, I2C
ADC
10-Bit
8 Ch.
Autoscan
1 ch DMA
MAB
MDB
Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A3
3 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
Port P1
8 I/O
Interrupt
capability
pullup/down
resistors
P1.x
8
Spy-Bi
Wire
XIN XOUT
RAM
256B
Flash
8KB
4KB
2KB
1KB
P2.x
Port P2
up to 8 I/O
Interrupt
capability
pullup/down
resistors
up to 8
USI
Universal
Serial
Interface
SPI, I2C
Comp_A+
8 Channels
MAB
MDB
MSP430G2x52
MSP430G2x12
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
Functional Block Diagram, MSP430G2x52
NOTE: Port P2. Two pins are available on the 14-pin and 16-pin package options. Eight pins are available on the 20-pin
package options.
Functional Block Diagram, MSP430G2x12
NOTE: Port P2. Two pins are available on the 14-pin and 16-pin package options. Eight pins are available on the 20-pin
package options.
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MSP430G2x52
MSP430G2x12
www.ti.com
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
TERMINAL FUNCTIONS
Table 2. Terminal Functions
TERMINAL
NO. I/O DESCRIPTION
NAME 14 16 20
PW RSA N, PW
P1.0/ General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
ACLK/ 2 1 2 I/O ACLK signal output
A0/ ADC10 analog input A0(1)
CA0 Comparator_A+, CA0 input
P1.1/ General-purpose digital I/O pin
TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output
3 2 3 I/O
A1/ ADC10 analog input A1(1)
CA1 Comparator_A+, CA1 input
P1.2/ General-purpose digital I/O pin
TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output
4 3 4 I/O
A2/ ADC10 analog input A2(1)
CA2 Comparator_A+, CA2 input
P1.3/ General-purpose digital I/O pin
ADC10CLK/ ADC10, conversion clock output(1)
CAOUT/ Comparator_A+, output
5 4 5 I/O
A3/ ADC10 analog input A3(1)
VREF-/VEREF/ ADC10 negative reference voltage(1)
CA3 Comparator_A+, CA3 input
P1.4/ General-purpose digital I/O pin
SMCLK/ SMCLK signal output
TA0.2/ Timer0_A, capture: CCI2A input, compare: Out2 output
A4/ 6 5 6 I/O ADC10 analog input A4(1)
VREF+/VEREF+/ ADC10 positive reference voltage(1)
CA4/ Comparator_A+, CA4 input
TCK JTAG test clock, input terminal for device programming and test
P1.5/ General-purpose digital I/O pin
TA0.0/ Timer0_A, compare: Out0 output
SCLK/ USI: clk input in I2C mode; clk in/output in SPI mode
7 6 7 I/O
A5/ ADC10 analog input A5(1)
CA5/ Comparator_A+, CA5 input
TMS JTAG test mode select, input terminal for device programming and test
P1.6/ General-purpose digital I/O pin
TA0.1/ Timer0_A, compare: Out1 output
SDO/ USI: Data output in SPI mode
SCL/ 8 7 14 I/O USI: I2C clock in I2C mode
A6/ ADC10 analog input A6(1)
CA6/ Comparator_A+, CA6 input
TDI/TCLK JTAG test data input or test clock input during programming and test
(1) Available only on MSP430G2x52 devices.
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MSP430G2x52
MSP430G2x12
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME 14 16 20
PW RSA N, PW
P1.7/ General-purpose digital I/O pin
CAOUT/ Comparator_A+, output
SDI/ USI: Data input in SPI mode
SDA/ 9 8 15 I/O USI: I2C data in I2C mode
A7/ ADC10 analog input A7(1)
CA7/ Comparator_A+, CA7 input
TDO/TDI(2) JTAG test data output terminal or test data input during programming and test
P2.0 - - 8 I/O General-purpose digital I/O pin
P2.1 - - 9 I/O General-purpose digital I/O pin
P2.2 - - 10 I/O General-purpose digital I/O pin
P2.3 - - 11 I/O General-purpose digital I/O pin
P2.4 - - 12 I/O General-purpose digital I/O pin
P2.5 - - 13 I/O General-purpose digital I/O pin
XIN/ Input terminal of crystal oscillator
P2.6/ 13 12 19 I/O General-purpose digital I/O pin
TA0.1 Timer0_A, compare: Out1 output
XOUT/ Output terminal of crystal oscillator(3)
12 11 18 I/O
P2.7 General-purpose digital I/O pin
RST/ Reset
NMI/ 10 9 16 I Nonmaskable interrupt input
SBWTDIO Spy-Bi-Wire test data input/output during programming and test
TEST/ Selects test mode for JTAG pins on port 1. The device protection fuse is
connected to TEST.
11 10 17 I
SBWTCK Spy-Bi-Wire test clock input during programming and test
DVCC 1 16 1 NA Supply voltage
AVCC - 15 - NA Supply voltage
DVSS 14 14 20 NA Ground reference
AVSS - 13 - NA Ground reference
NC - - - NA Not connected
QFN Pad - Pad - NA QFN package pad connection to VSS recommended.
(2) TDO or TDI is selected via JTAG instruction.
(3) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430G2x52
MSP430G2x12
www.ti.com
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
Table 3. Instruction Word Formats
FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 –-> R5
Single operands, destination only CALL R8 PC –>(TOS), R8–> PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0
Table 4. Address Mode Descriptions(1)
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register MOV Rs,Rd MOV R10,R11 R10 –> R11
Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) –> M(6+R6)
Symbolic (PC relative) MOV EDE,TONI M(EDE) –> M(TONI)
Absolute MOV &MEM,&TCDAT M(MEM) –> M(TCDAT)
Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) –> M(Tab+R6)
M(R10) –> R11
Indirect autoincrement MOV @Rn+,Rm MOV @R10+,R11 R10 + 2– –> R10
Immediate MOV #X,TONI MOV #45,TONI #45 –> M(TONI)
(1) S = source, D = destination
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MSP430G2x52
MSP430G2x12
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
www.ti.com
Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 1 (LPM1)
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
DCO's dc generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2)
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator remains enabled
ACLK remains active
Low-power mode 3 (LPM3)
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
Crystal oscillator is stopped
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MSP430G2x52
MSP430G2x12
www.ti.com
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
Power-Up PORIFG
External Reset RSTIFG
Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest
Flash key violation KEYV(2)
PC out-of-range(1)
NMI NMIIFG (non)-maskable
Oscillator fault OFIFG (non)-maskable 0FFFCh 30
Flash memory access violation ACCVIFG(2)(3) (non)-maskable 0FFFAh 29
0FFF8h 28
Comparator_A+ CAIFG(4) maskable 0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer0_A3 TACCR0 CCIFG(4) maskable 0FFF2h 25
Timer0_A3 TACCR2 TACCR1 CCIFG. TAIFG(2)(4) maskable 0FFF0h 24
0FFEEh 23
0FFECh 22
ADC10(5) ADC10IFG(4)(5) maskable 0FFEAh 21
USI USIIFG, USISTTIFG(2)(4) maskable 0FFE8h 20
I/O Port P2 (up to eight flags) P2IFG.0 to P2IFG.7(2)(4) maskable 0FFE6h 19
I/O Port P1 (up to eight flags) P1IFG.0 to P1IFG.7(2)(4) maskable 0FFE4h 18
0FFE2h 17
0FFE0h 16
See (6) 0FFDEh to 15 to 0, lowest
0FFC0h
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) MSP430G2x52 only
(6) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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MSP430G2x52
MSP430G2x12
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend rw: Bit can be read and written.
rw-0,1: Bit can be read and written. It is reset or set by PUC.
rw-(0,1): Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address 76543210
00h ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0
WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
OFIE Oscillator fault interrupt enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address 76543210
01h
Table 7. Interrupt Flag Register 1 and 2
Address 76543210
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault.
PORIFG Power-On Reset interrupt flag. Set on VCC power-up.
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
NMIIFG Set via RST/NMI pin
Address 76543210
03h
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MSP430G2x52
MSP430G2x12
www.ti.com
SLAS722E DECEMBER 2010REVISED DECEMBER 2011
Memory Organization
Table 8. Memory Organization
MSP430G2112 MSP430G2212 MSP430G2312 MSP430G2412
MSP430G2152 MSP430G2252 MSP430G2352 MSP430G2452
Memory Size 1kB 2kB 4kB 8kB
Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0
Main: code memory Flash 0xFFFF to 0xFC00 0xFFFF to 0xF800 0xFFFF to 0xF000 0xFFFF to 0xE000
Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte
Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h
RAM Size 128 B 256 B 256 B 256 B
0x027F to 0x0200 0x02FF to 0x0200 0x02FF to 0x0200 0x02FF to 0x0200
Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h
8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h 0FFh to 010h
8-bit SFR 0Fh to 00h 0Fh to 00h 0Fh to 00h 0Fh to 00h
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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MSP430G2x52
MSP430G2x12
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
Calibration Data Stored in Information Memory Segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.
Table 9. Tags Used by the ADC Calibration Tags
NAME ADDRESS VALUE DESCRIPTION
TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3 V and TA= 30°C at calibration
TAG_ADC10_1 0x10DA 0x10 ADC10_1 calibration tag
TAG_EMPTY - 0xFE Identifier for empty memory areas
Table 10. Labels Used by the ADC Calibration Tags
ADDRESS
LABEL CONDITION AT CALIBRATION / DESCRIPTION SIZE OFFSET
CAL_ADC_25T85 INCHx = 0x1010, REF2_5 = 1, TA= 85°C word 0x0010
CAL_ADC_25T30 INCHx = 0x1010, REF2_5 = 1, TA= 30°C word 0x000E
CAL_ADC_25VREF_FACTOR REF2_5 = 1, TA= 30°C, I(VREF+) = 1 mA word 0x000C
CAL_ADC_15T85 INCHx = 0x1010, REF2_5 = 0, TA= 85°C word 0x000A
CAL_ADC_15T30 INCHx = 0x1010, REF2_5 = 0, TA= 30°C word 0x0008
CAL_ADC_15VREF_FACTOR REF2_5 = 0, TA= 30°C, I(VREF+) = 0.5 mA word 0x0006
CAL_ADC_OFFSET External VREF = 1.5 V, f(ADC10CLK) = 5 MHz word 0x0004
CAL_ADC_GAIN_FACTOR External VREF = 1.5 V, f(ADC10CLK) = 5 MHz word 0x0002
CAL_BC1_1MHz - byte 0x0009
CAL_DCO_1MHz - byte 0x00008
CAL_BC1_8MHz - byte 0x0007
CAL_DCO_8MHz - byte 0x0006
CAL_BC1_12MHz - byte 0x0005
CAL_DCO_12MHz - byte 0x0004
CAL_BC1_16MHz - byte 0x0003
CAL_DCO_16MHz - byte 0x0002
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DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
average DCO(RSEL,DCO) DCO(RSEL,DCO+1)
32 × f × f
f = MOD × f + (32 MOD) × f
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Main DCO Characteristics
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ..., RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are two 8-bit I/O ports implemented:
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition(port P1 and port P2 only) is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and port P2, if available.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
Each I/O has an individually programmable pin-oscillator enable bit to enable low-cost touch sensing.
WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
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Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 11. Timer0_A3 Signal Connections(1)
INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT
BLOCK
N20, PW20 PW14 RSA16 N20, PW20 PW14 RSA16
SIGNAL NAME SIGNAL
P1.0-2 P1.0-2 P1.0-1 TACLK TACLK
ACLK ACLK Timer NA
SMCLK SMCLK
PinOsc PinOsc PinOsc INCLK
P1.1-3 P1.1-3 P1.1-2 TA0.0 CCI0A P1.1-3 P1.1-3 P1.1-2
ACLK CCI0B P1.5-7 P1.5-7 P1.5-6
CCR0 TA0
VSS GND
VCC VCC
P1.2-4 P1.2-4 P1.2-3 TA0.1 CCI1A P1.2-4 P1.2-4 P1.2-3
CAOUT CCI1B P1.6-14 P1.6-8 P1.6-7
CCR1 TA1
VSS GND P2.6-19 P2.6-12 P2.6-12
VCC VCC
P1.4-6 P1.4-6 P1.4-5 TA0.2 CCI2A P1.4-6 P1.4-6 P1.4-5
PinOsc PinOsc PinOsc TA0.2 CCI2B CCR2 TA2
VSS GND
VCC VCC
(1) Only one pin-oscillator must be enabled at a time.
USI
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
Comparator_A+
The primary function of the Comparator_A+module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC10 (MSP430G2x52 only)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
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Peripheral File Map
Table 12. Peripherals With Word Access
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
ADC10 (MSP430G2x52 devices only) ADC data transfer start address ADC10SA 01BCh
ADC memory ADC10MEM 01B4h
ADC control register 1 ADC10CTL1 01B2h
ADC control register 0 ADC10CTL0 01B0h
Timer0_A3 Capture/compare register TACCR2 0176h
Capture/compare register TACCR1 0174h
Capture/compare register TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control TACCTL2 0166h
Capture/compare control TACCTL1 0164h
Capture/compare control TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Memory Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog Timer+ Watchdog/timer control WDTCTL 0120h
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Table 13. Peripherals With Byte Access
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
ADC10 (MSP430G2x52 devices only) Analog enable 1 ADC10AE1 04Bh
Analog enable 0 ADC10AE0 04Ah
ADC data transfer control register 1 ADC10DTC1 049h
ADC data transfer control register 0 ADC10DTC0 048h
USI USI control 0 USICTL0 078h
USI control 1 USICTL1 079h
USI clock control USICKCTL 07Ah
USI bit counter USICNT 07Bh
USI shift register USISR 07Ch
Comparator_A+ Comparator_A+ port disable CAPD 05Bh
Comparator_A+ control 2 CACTL2 05Ah
Comparator_A+ control 1 CACTL1 059h
Basic Clock System+ Basic clock system control 3 BCSCTL3 053h
Basic clock system control 2 BCSCTL2 058h
Basic clock system control 1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
Port P2 Port P2 selection 2 P2SEL2 042h
Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection 2 P1SEL2 041h
Port P1 resistor enable P1REN 027h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Function SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h
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Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
16 MHz
System Frequency - MHz
12 MHz
6 MHz
1.8 V
Supply Voltage - V
3.3 V
2.7 V
2.2 V 3.6 V
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Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS –0.3 V to 4.1 V
Voltage applied to any pin(2) –0.3 V to VCC + 0.3 V
Diode current at any device pin ±2 mA
Unprogrammed device –55°C to 150°C
Storage temperature range, Tstg (3) Programmed device –55°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions MIN NOM MAX UNIT
During program execution 1.8 3.6
VCC Supply voltage V
During flash programming/erase 2.2 3.6
VSS Supply voltage 0 V
TAOperating free-air temperature -40 85 °C
VCC = 1.8 V, dc 6
Duty cycle = 50% ± 10%
Processor frequency (maximum MCLK frequency VCC = 2.7 V,
fSYSTEM dc 12 MHz
using the USART module)(1)(2) Duty cycle = 50% ± 10%
VCC = 3.3 V, dc 16
Duty cycle = 50% ± 10%
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
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0.0
1.0
2.0
3.0
4.0
5.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC Supply Voltage V
Active Mode Current mA
fDCO = 1 MHz
fDCO = 8 MHz
fDCO = 12 MHz
fDCO = 16 MHz
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz, 2.2 V 220
fACLK = 32768 Hz,
Program executes in flash,
Active mode (AM)
IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA
current (1 MHz) 3 V 320 400
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics Active Mode Supply Current (Into VCC)
Figure 2. Active Mode Current vs VCC, TA= 25°C Figure 3. Active Mode Current vs DCO Frequency
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0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
TA Temperature C
V = 3.6 V
CC
TA Temperature C
I Low−power mode current µA
LPM4
V = 1.8 V
CC
V = 3 V
CC
V = 2.2 V
CC
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
I Low−power mode current µA
LPM3
V = 3.6 V
CC
TA Temperature °C
V = 1.8 V
CC
V = 3 V
CC
V = 2.2 V
CC
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 0
ILPM0,1MHz BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 55 µA
(LPM0) current(3) DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 2
ILPM2 BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 22 µA
(LPM2) current(4) DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,
Low-power mode 3 fACLK = 32768 Hz,
ILPM3,LFXT1 25°C 2.2 V 0.7 1.0 µA
(LPM3) current(4) CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,
Low-power mode 3 fACLK from internal LF oscillator (VLO),
ILPM3,VLO 25°C 2.2 V 0.5 0.7 µA
current, (LPM3)(4) CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz, 25°C 0.1 0.5
Low-power mode 4 fACLK = 0 Hz,
ILPM4 2.2 V µA
(LPM4) current(5) CPUOFF = 1, SCG0 = 1, SCG1 = 1, 85°C 0.8 1.5
OSCOFF = 1
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 4. LPM3 (VLO) Current vs Temperature Figure 5. LPM4 Current vs Temperature
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Schmitt-Trigger Inputs Ports Px(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
0.45 VCC 0.75 VCC
VIT+ Positive-going input threshold voltage V
3 V 1.35 2.25
0.25 VCC 0.55 VCC
VIT– Negative-going input threshold voltage V
3 V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ VIT–) 3 V 0.3 1 V
For pullup: VIN = VSS
RPull Pullup/pulldown resistor 3 V 20 35 50 k
For pulldown: VIN = VCC
CIInput capacitance VIN = VSS or VCC 5 pF
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int).
Leakage Current Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.x) High-impedance leakage current (1) (2) 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input, and the pullup/pulldown resistor is
disabled.
Outputs Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH High-level output voltage I(OHmax) = –6 mA(1) 3 V VCC 0.3 V
VOL Low-level output voltage I(OLmax) = 6 mA(1) 3 V VSS + 0.3 V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fPx.y Port output frequency (with load) Px.y, CL= 20 pF, RL= 1 kΩ(1) (2) 3 V 12 MHz
fPort_CLK Clock output frequency Px.y, CL= 20 pF(2) 3 V 16 MHz
(1) A resistive divider with two 0.5-kΩresistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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