MM74HC595MX - FAIRCHILD SEMICONDUCTOR

June 2009

MM74HC595 • Rev. 1.0.2

MM74HC595 — 8-Bit Shift Register with Output Latches

MM74HC595

8-Bit Shift Register with Output Latches

Features

 Low Quiescent current: 80µA Maximum

(74HC Series)

 Low Input Current: 1µA Maximum

 8-Bit Serial-In, Parallel-Out Shift Register with

Storage

 Wide Operating Voltage Range: 2V–6V

 Cascadable

 Shift Register has Direct Clear

 Guaranteed Shift Frequency: DC to 30MHz

Description

The MM74HC595 high-speed shift register utilizes

advanced silicon-gate CMOS technology. This device

possesses the high noise immunity and low power

consumption of standard CMOS integrated circuits, as

well as the ability to drive 15 LS-TTL loads.

This device contains an eight-bit serial-in, parallel-out,

shift register that feeds an eight-bit D-type storage

register. The storage register has eight 3-state outputs.

Separate clocks are provided for both the shift register

and the storage register. The shift register has a direct-

overriding clear, serial input, and serial output

(standard) pins for cascading. Both the shift register

and storage register use positive-edge triggered clocks.

If both clocks are connected together, the shift register

state is one clock pulse ahead of the storage register.

The 74HC logic family is speed, function, and pin-out

compatible with the standard 74LS logic family. All

inputs are protected from damage due to static

discharge by internal diode clamps to VCC and ground.

Ordering Information

Part Number Operating

Temperature

Range

Eco

Status Package Packing

Method

MM74HC595M -40 to +85°C RoHS Tubes

MM74HC595MX -40 to +85°C RoHS

16-Lead, Small Outline Integrated Circuit (SOIC),

JEDEC MS-012, 0.150 Inch Narrow Tape and Reel

MM74HC595SJ -40 to +85°C RoHS Tubes

MM74HC595SJX -40 to +85°C RoHS

16-Lead, Small Outline Package (SOP), EIAJ

TYPE II, 5.3mm Wide Tape and Reel

MM74HC595MTC -40 to +85°C RoHS Tubes

MM74HC595MTCX -40 to +85°C RoHS

16-Lead, Thin Shrink Small Outline Package

(TSSOP), JEDEC MO-153, 4.4mm Wide Tape and Reel

MM74HC595N -40 to +85°C RoHS 16-Lead, Plastic Dual In-Line Package (PDIP),

JEDEC MS-001, 0.300 Inch Wide Tubes

For Fairchild’s defini t i on of Eco St atus, pleas e visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

MM74HC595 • Rev. 1.0.2 2

MM74HC595 — 8-Bit Shift Register with Output Latches

Block Diagram

Figure 1. Logic Diagram (Positive Logic)

MM74HC595 • Rev. 1.0.2 3

MM74HC595 — 8-Bit Shift Register with Output Latches

Pin Configuration

Figure 2. Pin Configuration

Pin Definitions

Pin # Name Description

1 QB Output Bit B

2 QC Output Bit C

3 QD Output Bit D

4 QE Output Bit E

5 QF Output Bit F

6 QG Output Bit G

7 QH Output Bit H

8 GND Ground

9 Q’H Serial Data Output

10 SCLR Shift Register Clear

11 SCK Shift Register Clock Input

12 RCK Storage Register Clock Input

13 G Output Enable

14 SER Serial Data Input

15 QA Output Bit A

16 VCC Supply Voltage

Truth Table

RCK SCK SCLR G Function

X X X H QA through QH = 3-state

X X L L Shift register clocked; Q’H = 0

X ↑ H L Shift register clocked; QN = Qn-1, Q0 = SER

↑ X H L Contents of shift; register transferred to output latches

L = Logic Level LOW

H = Logic Level HIGH

X = Don’t Care

↑ = Transition from LOW to HIGH level

MM74HC595 • Rev. 1.0.2 4

MM74HC595 — 8-Bit Shift Register with Output Latches

Absolute Maximum Ratings(1)

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage -0.5 7.0 V

VIN DC Input Voltage -1.5 to VCC+ 1.5 V

VOUT DC Output Voltage -0.5 to VCC+ 0.5 V

IIK, IOK Clamp Diode Current ±20 mA

IOUT DC Output Current, per Pin ±35 mA

ICC DC VCC or GND Current, per Pin ±70 mA

TSTG Storage Temperature Range -65 +150 °C

PDIP(2) 600

PD Power Dissipation SOIC Package Only 500 mW

TL Lead Temperature +260 °C

ESD Electrostatic Discharge Capability Human Body Model,

JESD22-A114 4000 V

Notes:

1. Unless otherwise specified all voltages are referenced to ground.

2. Power dissipation temperature derating, plastic package (PDIP);12mW/°C from -65 to +85°C.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2 6 V

VIN, VOUT DC Input or Output Voltage 0 VCC V

TA Operating Temperature Range -40 +85 °C

VCC=2.0V 1000

VCC=4.5V 500

tR,tF Input Rise and Fall Times

VCC=6.0V 400

ns

MM74HC595 • Rev. 1.0.2 5

MM74HC595 — 8-Bit Shift Register with Output Latches

Electrical Characteristics(3)

TA=25°C TA=-40 to

85°C TA=-55

to 125°C

Symbol Parameter Conditions VCC Typ. Guaranteed Limits

Units

2.0V 1.50 1.50 1.50

4.5V 3.15 3.15 3.15

VIH

Minimum HIGH

Level Input

Voltage

6.0V 4.20 4.20 4.20

V

2.0V 0.50 0.50 0.50

4.5V 1.35 1.35 1.35

VIL

Minimum LOW

Level Input

Voltage

6.0V 1.80 1.80 1.80

V

2.0V 2.00 1.90 1.90 1.90

4.5V 4.50 4.40 4.40 4.40

Minimum HIGH

Level Output

Voltage

VIN=VIH or VIL ⏐IOUT⏐≤20µA

6.0V 6.00 5.90 5.90 5.90

V

⏐IOUT⏐≤4.0mA 4.5V 4.20 3.98 3.84 3.70

Q’H VIN=VIH or VIL ⏐IOUT⏐≤5.2mA 6.0V 5.20 5.48 5.34 5.20 V

⏐IOUT⏐≤6.0mA 4.5V 4.20 3.98 3.84 3.70

VOH

QA through QH VIN=VIH or VIL ⏐IOUT⏐≤7.8mA 6.0V 5.70 5.48 5.34 5.20 V

2.0V 0 0.10 0.10 0.10

4.5V 0 0.10 0.10 0.10

Minimum LOW

Level Output

Voltage

VIN=VIH or VIL ⏐IOUT⏐≤20µA

6.0V 0 0.10 0.10 0.10

V

⏐IOUT⏐≤4.0mA 4.5V 0.20 0.26 0.33 0.40

Q’H V

IN=VIH or VIL ⏐IOUT⏐≤5.2mA 6.0V 0.20 0.26 0.33 0.40 V

⏐IOUT⏐≤6.0mA 4.5V 0.20 0.26 0.33 0.40

VOL

QA through QH VIN=VIH or VIL ⏐IOUT⏐≤7.8mA 6.0V 0.20 0.26 0.33 0.40 V

IIN

Maximum Input

Output

Leakage

VIN=VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA

IOZ

Maximum 3-

State Output

Leakage

VOUT =VCC

or GND G=VIH 6.0V ±0.5 ±5.0 ±10 µA

ICC

Maximum

Quiescent

Supply Current

VIN =VCC

or GND IOUT=µA 6.0V 8.0 80 160 µA

Note:

3. For a power supply of 5V ±10%, the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. The 4.5V

values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V,

respectively; VIH value at 5.5V is 3.85V. The worst-case leakage current (IIN, ICC, and IOZ) occurs for CMOS at

the higher voltage; so the 6.0V values should be used.

MM74HC595 • Rev. 1.0.2 6

MM74HC595 — 8-Bit Shift Register with Output Latches

AC Electrical Characteristics

VCC = 5V, TA = 25°C, tr = tf = 6ns.

Symbol Parameter Conditions Typ. Guaranteed Limit Units

fMAX Maximum Operating Frequency of SCK 50 30 MHz

Maximum Propagation Delay, SCK to Q’H12 20

tPHL,tPLH Maximum Propagation Delay, RCK to QA

thru Q’H

CL=45pF 18 30 ns

tPZH,tPZL Maximum Output Enable Time from G to

QA thru Q’H RL=1kΩ, CL=45pF 17 28 ns

tPHZ,tPLZ Maximum Output Disable Time from G to

QA thru Q’H RL=1kΩ, CL=45pF 15 25 ns

Minimum Setup Time from SER to SCK 20 ns

Minimum Setup Time from SCLR to SCK 20 ns

tS

Minimum Setup Time from SER to

RCK(4) 40 ns

tH Minimum Hold Time from SER to SCK 0 ns

tW Minimum Pulse Width of SCK or RCK 16 ns

Note:

4. This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be

connected together in which case the storage register state will be one clock pulse behind the shift register.

MM74HC595 • Rev. 1.0.2 7

MM74HC595 — 8-Bit Shift Register with Output Latches

Electrical Characteristics

VCC = 2.0−6.0V, CL = 50pF, tr = tf =6ns unless otherwise specified.

TA=25°C TA=-40 to

85°C TA=-55

to 125°C

Symbol Parameter Conditions VCC Typ. Guaranteed Limits Units

2.0V 10.0 6.0 4.8 4.0

4.5V 45.0 30.0 24.0 20.0

fMAX Maximum Operating

Frequency CL=50pF

6.0V 50.0 35.0 28.0 24.0

ns

CL=50pF 2.0V 58.0 210.0 235.0 315.0

CL=150pF 2.0V 83.0 294.0 367.0 441.0

CL=50pF 4.5V 14.0 42.0 53.0 63.0

CL=150pF 4.5V 17.0 58.0 74.0 88.0

CL=50pF 6.0V 10.0 36.0 45.0 54.0

Maximum Propagation

Delay, SCK to Q’H

CL=150pF 6.0V 14.0 50.0 63.0 76.0

ns

CL=50pF 2.0V 70.0 175.0 220.0 265.0

CL=150pF 2.0V 105.0 245.0 306.0 368.0

CL=50pF 4.5V 21.0 35.0 44.0 53.0

CL=150pF 4.5V 28.0 49.0 61.0 74.0

CL=50pF 6.0V 18.0 30.0 37.0 45.0

Maximum Propagation

Delay, RCK to QA thru Q’H

CL=150pF 6.0V 26.0 42.0 53.0 63.0

ns

2.0V 175.0 221.0 261.0

4.5V 35.0 44.0 52.0

tPHL,tPLH

Maximum Propagation

Delay, SCLR to Q’H

6.0V 30.0 37.0 44.0

ns

CL=50pF 2.0V 75.0 175.0 220.0 265.0

RL=1kΩCL=150pF 2.0V 100.0 245.0 306.0 368.0

CL=50pF 4.5V 15.0 35.0 44.0 53.0

CL=150pF 4.5V 20.0 49.0 61.0 74.0

CL=50pF 6.0V 13.0 30.0 37.0 45.0

tPZH,tPZL

Maximum Output Enable

Time from G to QA thru Q’H

CL=150pF 6.0V 17.0 42.0 53.0 63.0

ns

2.0V 75.0 175.0 220.0 265.0

4.5V 15.0 35.0 44.0 53.0

tPHZ,tPLZ

Maximum Output Disable

Time from G to QA thru Q’H RL=1kΩ, CL=50pF

6.0V 13.0 30.0 37.0 45.0

ns

Continued on the following page…

MM74HC595 • Rev. 1.0.2 8

MM74HC595 — 8-Bit Shift Register with Output Latches

Electrical Characteristics

VCC = 2.0−6.0V, CL = 50pF, tr = tf =6ns unless otherwise specified.

TA=25°C TA=-40 to

85°C TA=-55

to 125°C

Symbol Parameter Conditions VCC Typ. Guaranteed Limits Units

2.0V 100 125 150

4.5V 20 25 30

tS Minimum Setup Time from

SER to SCK RL=1kΩ, CL=50pF

6.0V 17 21 25

ns

2.0V 50 63 75

4.5V 10 13 15

tR

Minimum Removal Time

from SCLR to SCK

6.0V 9 11 13

ns

2.0V 100 125 150

4.5V 20 25 30

tS Minimum Setup Time from

SCK to RCK

6.0V 17 21 26

ns

2.0V 5 5 5

4.5V 5 5 5

tH Minimum Hold Time from

SER to SCK

6.0V 5 5 5

ns

2.0V 30 80 100 120

4.5V 9 16 20 24

tW

Minimum Pulse Width of

SCK or SCLR

6.0V 8 14 18 22

ns

2.0V 1000 1000 1000

4.5V 500 500 500

tR,tF Maximum Input Rise and

Fall Time, Clock

6.0V 400 400 400

ns

2.0V 25 60 75 90

4.5V 7 12 15 18

Maximum Output Rise and

Fall Time QA-QH

6.0V 6 10 13 15

ns

2.0V 75 95 110

4.5V 15 19 22

tTHL,tTLH

Maximum Output Rise and

Fall Time Q’H

6.0V

13 16 19

ns

G=VCC

90

CPD

Power Dissipation

Capacitance, Outputs

Enabled(5) G=GND 150 pF

CIN Maximum Input Capacitance 5 10 10 10 pF

COUT Maximum Output

Capacitance 15 20 20 20 pF

Note:

5. CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic

current consumption, IS = CPD VCCf + ICC.

MM74HC595 • Rev. 1.0.2 9

MM74HC595 — 8-Bit Shift Register with Output Latches

Timing Diagram

Figure 3. Timing Diagram

Note:

6. Implies that the output is in 3-state mode.

XXX

MM74HC595 • Rev. 1.0.2 10

MM74HC595 — 8-Bit Shift Register with Output Latches

Physical Dimensions

X 45°

DETAIL A

SCALE: 2:1

8°

0°

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AC, ISSUE C.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD

FLASH AND TIE BAR PROTRUSIONS

D) CONFORMS TO ASME Y14.5M-1994

E) LANDPATTERN STANDARD: SOIC127P600X175-16AM

F) DRAWING FILE NAME: M16AREV12.

SEATING PLANE

GAGE PLANE

C

C0.10

SEE DETAIL A

LAND PATTERN RECOMMENDATION

PIN ONE

INDICATOR

1

16

8

M

0.25

9

CBA

B

A

5.6

1.27 0.65

1.75

10.00

9.80

8.89

6.00

1.27

(0.30)

0.51

0.35

1.75 MAX

1.50

1.25

0.25

0.10

0.25

0.19

(1.04)

0.90

0.50

0.36

(R0.10)

0.50

0.25

4.00

3.80

Figure 4. 16-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Inch Narrow

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

MM74HC595 • Rev. 1.0.2 11

MM74HC595 — 8-Bit Shift Register with Output Latches

Physical Dimensions

Figure 5. 16-Lead, Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Pack age drawings are provi ded as a servic e to customers considering Fairchild components. Drawings may change in any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emic onductor representative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

MM74HC595 • Rev. 1.0.2 12

MM74HC595 — 8-Bit Shift Register with Output Latches

Physical Dimensions

0.65

4.4±0.1

MTC16rev4

0.11

4.55

5.00

5.00±0.10

12°

7.354.45

1.45

5.90

Figure 6. 16-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pack age drawings are provi ded as a servic e to customers considering Fairc h i l d components. Drawi ngs may change in any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emic onductor representative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

MM74HC595 • Rev. 1.0.2 13

MM74HC595 — 8-Bit Shift Register with Output Latches

Physical Dimensions

16 9

81

NOTES: UNLESS OTHERWISE SPECIFIED

A THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BB

B) ALL DIMENSIONS ARE IN MILLIMETERS.

D) CONFORMS TO ASME Y14.5M-1994

E) DRAWING FILE NAME: N16EREV1

19.68

18.66

6.60

6.09

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR PROTRUSIONS

3.42

3.17

3.81

2.92

(0.40)

2.54

17.78

0.58

0.35

1.78

1.14

5.33 MAX

0.38 MIN 8.13

7.62

0.35

0.20

15

0

8.69

A

TOP VIEW

SIDE VIEW

Figure 7. 16-Lead, Plastic Dual In-Line Package (PDIP), JEDEC MS-001, 0.300 Inch Wide

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

MM74HC595 • Rev. 1.0.2 14

MM74HC595 — 8-Bit Shift Register with Output Latches