HT82700 - Holtek Semiconductor

HT827XX

8-bit Microcontroller with Voice ROM

Selection T a ble

Item Program R OM Data RAM Voice ROM

HT82700 4K × 15 112 × 8 128K × 8

HT82720 4K × 15 1 12 × 896K × 8

HT82740 4K × 15 1 12 × 864K × 8

HT82770 2K × 14 80 × 864K × 8

HT82780 2K × 14 80 × 832K × 8

Features

8-bit mi cr ocontroller

•Operating voltage: 2.4V~5.2V

•2K × 14 or 4K × 15 program ROM

•80 × 8 or 112 × 8 data RAM

•24 bidirectional I/O lines

•An interrupt input

•An 8-bit programmable timer/event counter

with overflow interrupts

•A watch dog time r

•On-chip crystal and RC types of oscillator

•Halt functio n to reduce p ower cons umptio n

and a wake-up feature

•63 powerful instructions

•Up to a 1µs instruction cycle with a 4MHz

system clock at VDD=5V

•All instructions in 1 or 2 machi ne cycles

•14 bit table read instruction

•Four level subroutine nesting

•Bit manipulation instruction

General Description

The HT827XX series are an 8 bit high perform-

ance microcontroller with a voice synthesizer

and tone generator . They are designed for appli-

cations on multiple I/Os with sound effects. The

LSIs provide 26 kinds of voice sampling rates, 4

octaves of tone level as well as a high quality of

current type D/A output. With such a flexible

structure, the HT827XX series are excellent for

applications on versatile vo ice and so und effect

products. They also include a halt function to

reduce power consumption.

Voice and melody synthesi zer

•32K × 8~128K × 8 voice ROM

•3/4 bit ADPCM coding algorithm

•26 kinds of voice sampling rates

•A tone level of 4 octaves

•14 kind s of melody beats

•Current type of D/A switch output

•A tone generator counter

•Controllable volume

Applications

•Intelligent educational toys

•High end toy controllers

•Talking alarm clocks

•Alert & warning system

•Public address systems

•Sound effect generators

1 4th Jan ’97

Pin Assignment

Block Diagram

HT827XX

2 4th Jan ’97

Pa d Assignment (HT82700)

Chip size: 3760 × 5680 (µm)2

* The IC substrate should be connected to VSS in the PCB layout artwork.

* The TMR pad must be bo un d to VDD or VSS if it is not us ed.

HT827XX

3 4th Jan ’97

Pad Coordinates (HT82700) Unit: µm

Pad No. X Y Pad No. X Y

1 –1597.90 2589.80 18 1703.20 –2057.70

2 –1624.50 –1101.80 19 1708.20 –1761.80

3 –1624.90 –1536.00 20 1744.20 –1521.20

4 –1618.80 –1869.00 21 1698.80 –930.60

5 –1618.80 –2276.80 22 1652.90 2589.80

6 –1605.70 –2582.30 23 1389.20 2589.80

7 –1318.60 –2622.80 24 1122.10 2589.80

8 –1035.80 –2622.80 25 858.40 2589.80

9 –762.50 –2622.80 26 544.80 2589.90

10 –483.80 –2622.80 27 285.10 2589.90

11 –210.50 –2622.80 28 27.80 2589.70

12 68.20 –2622.80 29 –229.50 2589.90

13 341.50 –2622.80 30 –489.20 2589.90

14 620.20 –2622.80 31 –802.80 2589.80

15 889.35 –2622.80 32 –1066.50 2589.80

16 1158.10 –2622.80 33 –1334.20 2589.80

17 1706.20 –2371.60

Pa d Assignment (HT82720)

Chip size: 3750 × 4970 ( µm)2

HT827XX

4 4th Jan ’97

* The IC substrate should be connected to VSS in the PCB layout artwork.

* The TMR pad must be bo un d to VDD or VSS if it is not us ed.

Pad Coordinates (HT82720) Unit: µm

Pad No. X Y Pad No. X Y

1 –1624.40 –746.80 18 1701.10 –1596.30

2 –1624.80 –1181.00 19 1689.40 –1329.10

3 –1618.70 –1514.00 20 1698.90 –592.70

4 –1618.70 –1921.80 21 1653.00 2234.80

5 –1605.60 –2227.30 22 1389.30 2234.80

6 –1318.50 –2267.80 23 1122.20 2234.80

7 –1035.70 –2267.80 24 858.50 2234.80

8 –762.40 –2267.80 25 544.90 2234.90

9 –483.70 –2267.80 26 285.20 2234.90

10 –210.40 –2267.80 27 27.90 2234.70

11 68.30 –2267.80 28 –229.40 2234.90

12 341.60 –2267.80 29 –489.10 2234.90

13 620.30 –2267.80 30 –802.70 2234.80

14 889.50 –2267.80 31 –1066.40 2234.80

15 1158.20 –2267.80 32 –1334.10 2234.80

16 1718.00 –2167.10 33 –1597.80 2234.80

17 1703.30 –1853.10

Pa d Assignment (HT82740)

Chip size: 3750 × 4260 (µm)2

HT827XX

5 4th Jan ’97

* The IC substrate should be connected to VSS in the PCB layout artwork.

* The TMR pad must be bo un d to VDD or VSS if it is not us ed.

Pad Coordinates (HT82740) Unit: µm

Pad No. X Y Pad No. X Y

1 –1624.40 –391.60 18 1701.10 –1241.10

2 –1624.80 –825.80 19 1689.40 –973.90

3 –1618.70 –1158.80 20 1698.90 –237.50

4 –1618.70 –1566.60 21 1653.00 1879.60

5 –1605.60 –1872.10 22 1389.30 1879.60

6 –1318.50 –1912.60 23 1122.20 1879.60

7 –1035.70 –1912.60 24 858.50 1879.60

8 –762.40 –1912.60 25 544.90 1879.70

9 –483.70 –1912.60 26 285.20 1879.70

10 –210.40 –1912.60 27 27.90 1879.50

11 68.30 –1912.60 28 –229.40 1879.70

12 341.60 –1912.60 29 –489.10 1879.70

13 620.30 –1912.60 30 –802.70 1879.60

14 889.50 –1912.60 31 –1066.40 1879.60

15 1158.20 –1912.60 32 –1334.10 1879.60

16 1718.00 –1811.90 33 –1597.80 1879.60

17 1703.30 –1497.90

Pa d Assignment (HT82770)

Chip size: 3700 × 3940 (µm)2

HT827XX

6 4th Jan ’97

* The IC substrate should be connected to VSS in the PCB layout artwork.

* The TMR pad must be bo un d to VDD or VSS if it is not us ed.

Pad Coordinates (HT82770) Unit: µm

Pad No. X Y Pad No. X Y

1 –1624.40 1757.90 18 1676.50 –1343.85

2 –1651.60 –277.10 19 1681.50 –1097.55

3 –1651.60 –631.10 20 1717.50 –916.65

4 –1631.50 –1179.30 21 1672.10 –326.05

5 –1631.50 –1530.80 22 1626.40 1757.90

6 –1592.50 –1750.10 23 1362.70 1757.90

7 –1358.70 –1746.70 24 1095.60 1757.90

8 –1075.90 –1746.70 25 831.90 1757.90

9 –802.60 –1746.70 26 518.30 1758.00

10 –523.90 –1746.70 27 258.60 1758.00

11 –250.60 –1746.70 28 1.30 1757.80

12 28.10 –1746.70 29 –256.00 1758.00

13 301.40 –1746.70 30 –515.00 1758.00

14 580.10 –1746.70 31 –829.30 1757.90

15 849.25 –1746.70 32 –1093.00 1857.90

16 1118.00 –1746.70 33 –1360.70 1857.90

17 1679.50 –1636.65

Pa d Assignment (HT82780)

Chip size: 3700 × 3230 (µm)2

* The IC substrate should be connected to VSS in the PCB layout artwork.

* The TMR pad must be bo un d to VDD or VSS if it is not us ed.

HT827XX

7 4th Jan ’97

Pad Coordinates (HT82780) Unit: µm

Pad No. X Y Pad No. X Y

1 –1651.60 75.05 18 1681.50 –936.55

2 –1651.60 –278.95 19 1662.60 –674.95

3 –1631.50 –827.15 20 1672.10 39.15

4 –1631.50 –1178.65 21 1626.40 1405.75

5 –1592.50 –1397.95 22 1362.70 1405.75

6 –1358.70 –1394.55 23 1095.60 1405.75

7 –1075.90 –1394.55 24 831.90 1405.75

8 –817.60 –1394.55 25 518.30 1405.85

9 –568.90 –1394.55 26 258.60 1405.85

10 –325.60 –1394.55 27 1.30 1405.65

11 –76.90 –1394.55 28 –256.00 1405.85

12 166.40 –1394.55 29 –515.70 1405.85

13 415.10 –1394.55 30 –829.30 1405.75

14 673.40 –1394.55 31 –1093.00 1405.75

15 952.10 –1394.55 32 –1360.70 1405.75

16 1679.50 –1420.85 33 –1624.40 1405.75

17 1676.50 –1147.05

Pad Description

Pad No. Pad Name I/O Mask Option Function

31~33

22~25 PA0~PA7 I/O Wake-up

Pull-High

or none

Bidirectional 8 bit input/output ports

Each b it can be co nfigured as a wake-up input by

mask op tion. Software i nstructions d etermine the

CMOS output or schmitt trigger input with or

without a pull high resistor (mask option).

2~5

26,27

29,30 PB0~PB7 I/O Pull-High

or none

Bidirectional 8 bit input/output ports

Software instructions determine the CMOS output

or schmitt trigger input with or without a pull high

resistor (mask option).

6,28 VSS — — Negative power supply (GND)

7INT I —

External interrupt schmitt trigger input with a

pull-high resistor

Edge triggered is activated on a high to low

transition.

8 TMR I — Schmitt trigger input for a timer/event counter

9~16 PC0~PC7 I/O Pull-High

or none

Bidirectional 8 bit input/output ports

Software instructions determine the CMOS output

or schmitt trigger input with or without a pull-high

resistor (mask option).

HT827XX

8 4th Jan ’97

Pad No. Pad Name I/O Mask Option Function

17 AUD O — Audio output for driving an external transistor

PMOS open drain ou tput

18 RES I — Schmitt trigger reset input, active low

19 VDD — — Positive power supply

21 OSC1

OSC2 I

OCrystal or RC

OSC1 and OSC2 connect to an RC network or

crystal (determined by mask option) for an

internal system clock. In the case of RC operation,

an oscillation resistor connects to OSC1. OSC2 is

the outp ut terminal of a 1/4 system cl ock.

Abso lu te M ax imum R a tin g s

Supply Voltage ................ .... .... .... ..–0.3V to 5.5V Storage Temperature............. ....–50°C to 125°C

Input Voltage................. VSS–0.3V to VDD+0.3V Operating Temperature...............–25°C to 70°C

D.C. Characteristics (Ta=25°C)

Symbol Parameter Test Condition Min. Typ. Max. Unit

VDD Condition

VDD Operating Voltage — — 2.4 — 5.2 V

IDD1 Operating Curre nt (Crystal OSC) 3V No load,

fSYS=4MHz — 0.7 1.5 mA

5V — 2 3 mA

IDD2 Operating Current (RC OSC ) 3V No load,

fSYS=4MHz — 1.5 3 mA

5V — 2.5 5 mA

ISTB1 Stand-by Current (WDT Enabled) 3V No load,

system HALT ——10

µA

5V — — 20 µA

ISTB2 Stand-by Current (WDT Disabled) 3V No load,

system HALT ——3µA

5V — — 5 µA

VIL Input Low Voltage for I/O Ports 3V — 0 — 0.6 V

5V — 0 — 1.0 V

VIH Input High Voltage for I/O Ports 3V — 2.4 — 3 V

5V — 4.0 — 5 V

VIL1 Input Low Volt age

(RES,TMR, INT) 3V — 0 — 0.6 V

5V — 0 — 1.0 V

HT827XX

9 4th Jan ’97

Symbol Parameter Test Condition Min. Typ. Max. Unit

VDD Condition

VIH1 Input High Voltage

(RES,TMR, INT) 3V — 2.4 — 3 V

5V — 4.0 — 5 V

IOL1 I/O Port Sink Current

(PortA, PortC)

3V VDD=3V,

VOL=0.3V 24—mA

5V VDD=5V,

VOL=0.5V 610—mA

OH1 I/O Port Source Current

(PortA, PortC)

3V VDD=3V,

VOH=2.7V –1 –1.5 — mA

5V VDD=5V,

VOH=4.5V –2 –4 — mA

IOL2 PortB Sink Current 3V VDD=3V,

VOL=0.3V 610—mA

5V VDD=5V,

VOL=0.5V 20 25 — mA

IOH2 PortB Source Current 3V VDD=3V,

VOH=2.7V –1 –1.5 — mA

5V VDD=5V,

VOH=4.5V –2 –4 — mA

RPH Pull-High Resistance of

I/O Ports & INT 3V — 25 50 100 KΩ

5V — 10 30 60 KΩ

IOMax. AUD Output Current 3V VOH=0.6V –1.5 –2 — mA

A.C. Characteristics (Ta=25°C)

Symbol Parameter Test Conditio n Min. Typ. Max. Unit

VDD Condition

fSYS1 System Clock (Crystal OSC) 3V — 400 — 4000 KHz

5V — 400 — 4000 KHz

fSYS2 System Clock (RC OSC) 3V — 400 — 4000 KHz

5V — 400 — 4000 KHz

fTIMER Timer I/P Frequency (TMR) 3V — 0 — 4000 KHz

5V — 0 — 4000 KHz

tWDTOSC Watch Dog Oscillator 5V — 31 78 140 µs

HT827XX

10 4th Jan ’97

Symbol Parameter Test Conditio n Min. Typ. Max. Unit

VDD Condition

tWDT1 Watch Dog Timeout Period (RC) 5V Without WDT

prescaler 82036ms

WDT2 Watch Dog Timeout Period

(System Clock) 5V Without WDT

prescaler — 1024 — tSYS

tRES External Reset Low Pulse Width 5V — 1 — — µs

tINT Interrupt P ulse Width 5V — 1 — — µs

Note: tSYS=1/(fSYS)

Application Circuits

RC os cillator for multiple I/O applications Cry stal osci l lator fo r multiple I /O appli cations

HT827XX

11 4th Jan ’97

System Ar ch itecture

Exec utiv e flow

The HT827XX series provide a system clock

which is derived from a crystal or an RC type of

oscillator. The clock is internally divided into

four non-o verlappi ng clocks den oted b y P1, P2,

P3 and P4. An instruction cycle consists of

T1~T4.

Instruction fetching and execution are pipe-

lined in such a way that a fetch takes an in-

struction cycle while decoding and execution

take the next instruction cycle. The pipelining

scheme causes each instruction to execute effec-

tively in a cycle. If an instruction changes the

program counter, two cycles are required to

complete that instruction.

Progra m co un ter - PC

The program counter (PC) controls the se-

quence in which the instructions stored in the

program ROM are executed.

The con tents of the p rogram cou nter are incre-

mented by one after a program memory word is

accessed to fetch an instruction code. The pro-

gram counter then points to a memory word

containing the next instruction code.

The PC manipulates a program transfer by

loading the address corresponding to each in-

struction when executing a jump instruction,

conditional skip execution, loading PCL regis-

ter, subroutine call, initial reset, internal inter-

rupt, external interrupt or return from

subroutine.

The conditional skip is activated by instructions.

Once the condition is sat isf ied, t he next instr uc-

tion, fetc hed during the current instruc tion exe-

cution, is discarded and a dummy cycle r eplaces

it to get a proper instruction. Otherwise, the

system will proceed with the next instr uct ions.

The lower byte of the program counter (PCL) is

a readable and writable register (06H). Moving

data into PC L perform s a short ju mp. The des-

tination is within 256 locations.

Once a control trans fer takes pl ace, the e xecu-

tion suffers from an additional dummy cycle.

Execution Flow

HT827XX

12 4th Jan ’97

Program memory - ROM

The program memory stores the to-be-executed

program instru ctions. I t also in cludes data, ta -

ble and interrupt entries, addressed by the pro-

gram counter along with the table pointer.

The program memory size for HT82 7XX series

are shown as following.

HT82700, HT82720,

HT82740 4K × 15

HT8 27 70, H T82 78 0 2K × 14

Certain locations in the program memory are

rese rved for speci al usages :

•Location 000H

This area is reserved for program initializa-

tion. The program always begins execution at

location 000H each time the system is reset.

•Location 004H

This area is reserved for an external interrupt

service program. The program begins execu-

tion at location 004H if the INT input pin is

activated, the interrupt is enabled and the

stack is not full.

•Location 008H

This area is reserved for a voice sampling rate

counter interrupt service program. The pro-

gram begins execution at location 008H if a

timer interrupt results from a sampling rate

counter overflow, the interrupt is enabled and

the stack is not full.

•Location 00CH

This area is reserved for a timer/event counter

interrupt service program. The program be-

gins execution at location 00CH if an inter-

rupt results from a timer/event counter

overflow, the interrupt is enabled and the

stack is not full.

Program Memory

Mode Program Counter

*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Initial reset 000000000000

External interrupt 0 0 0 000000100

Sampling rate counter overflow 0 0 0 000001000

Timer/event Counter overflow 0 0 0 000001100

Skip PC+2

Loading PCL *11*10*9 *8@7@6@5@4@3@2@1@0

Jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Notes: *11(*10)~*0: Bits of program counter S11(*S10)~S0: Bits of stack register

#11(#10)~#0: Bits of instruction code @7~@0: Bits of PCL

The bit 11 of PC counter is omitted for HT82770 and HT82780

HT827XX

13 4th Jan ’97

•Tabl e location

Any location in the program ROM can be used

as a look-up table. The instructions “T ABRDC

[m]” (the current page, 1 page=256 words) and

“TABRDL [m]” (the last page) transfer the

contents of the lowe r-orde r byte to the s peci-

fied data memory, and the higher-order byte

to TBLH (08H). Only the destination of the

lower-order byte in the table is well-defined.

The other bits of the table word are trans-

ferred to the lower portion of TBLH. The

higher-order byte register (TBLH) of the table

is read only. The table pointer (TBLP), on the

other hand, is a re ad/write registe r (07H) in-

dicating the table location. This location must

be pla ced in TBLP before accessing the tab le.

All the table related instructions require 2

cycles to complete an operation. These areas

may function as a normal program memory

depending upon the user’s requirements.

Stack re g ist er - Sta c k

The stack register is a special part of the mem-

ory used to save the contents of the program

counter (PC). This stack is organized into 4

levels. It is neither part of the data nor program

space , and i s nei the r rea d able no r writa ble. Its

activated level is indexed by a stack pointer

(SP) and is neith er readable nor writa ble. At a

subroutine call or interrupt acknowledgment,

the contents of the program counter are pushed

onto the stack. The program counter is restored

to its previous value from th e stack at the end

of a subroutine or interrupt routine, which is

signaled by a return instruction (RET or RETI).

After a chip reset, SP will point to the top of the

stack.

The interrup t re ques t fla g will be record ed but

the acknowledgment be inhibited when the

stack is ful l and a non-ma sked inte rrupt takes

place. After the stack pointer is decremented

(by RET or RETI), the interrupt will be serv-

iced. This feature prevents stack overflow and

allows p rogramme rs to use the stru cture more

easily. In a sim ilar case, if th e stack is ful l and

a “CALL” is subsequently executed, stack over-

flow occu rs and the first en try is lost (only the

most recent two return addresses are stored).

Data memory - RAM

The data memory is further divided into two

functional group s, namely special function reg-

isters and general purpose data memories. Al-

though most of them are readable/writable,

some are read only.

The data mem ory si ze for HT827XX series are

shown as following.

Item RAM

Size Special

RAM General

RAM Address

HT82700

HT82720

HT82740 137 × 8 00H~2FH 30H~9FH

HT82770

HT82780 105 × 8 00H~2FH 30H~7FH

The special function registers include an indi-

rect addressing register (00H), timer/event

counter (TMR; 10H), timer/event counter con-

trol register (TMRC; 11H), program counter

lower-order byte register (PCL; 06H), memory

Instruction(s) Table Location

*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

Notes: *11(*10)~*0: Bits of table location P1 1( P 10 ) ~P 8 : B it s of c ur r en t p r og r am co u nt e r

@7~@0: Bits of table pointer

The bit 11 is omitted for HT82770 and HT82780

HT827XX

14 4th Jan ’97

pointer regi ste r (MP; 01 H), accu mula tor (A CC;

05H), table pointer (TBLP; 07H), table higher-

order byte register (TBLH; 08H), status regis-

ter (STATUS; 0AH), interrupt control register

(INTC; 0BH), watch dog timer option setting

PB; 14H, PC; 16H) and I/O control registers

(PAC; 13H, PBC; 15H, PCC; 17H). The 20H to

2FH are used for sound and tone (melody) syn-

thesis. The function registers include a lower-

order byte register (DAL; 20H) of D/A data,

higher-order byte register (DAH;21H) of D/A

data , volume control register (VCR; 22H), sam-

pling rate control register (SRC; 23H), beat con-

trol register (BEAT; 28H), tempo control

(TONE; 2AH) and voice ROM control register

(ROMC; 2CH). The remaining space before 30H

is reserved for future expansion. Reading these

remaining locations will get “00H”. The general

purpose data memory, addressed from 30H to

9FH (7FH), is used for data and control infor-

mation under instruction commands.

All of the areas of data memory can handle

arithmetic, logic, increment, decrement and ro-

tate operatio ns directly. Except some dedicated

bits, each bit in the data memory can be set and

reset by “SET [m].i” and “CLR [m].i”, and can

also be indirectly accessed through a memory

pointer register (MP; 01H).

Indirect addressing register

Location 00H is an indirect addressing register

that is not physically implemented. Any

read/write operation of [00H] accesses the data

memory pointed to by MP ( 01H ). Indirec tly r ead-

ing location 00H will return the result 00H

whereas indirectly writing it will lead to no opera-

tions. The memory poin ter register MP (01H) is a

7 bit register . Bit 7 of MP is undefined and reading

it will return the result “1”. Any writing operation

to MP will transfer only the lower 7 bit data to MP.

Arithme tic and logic unit - ALU

This circuit performs 8 b it arithm etic and logic

operations. ALU provides the following func-

tions:

RAM Mapping

HT827XX

15 4th Jan ’97

•Arithmetic operations (ADD, ADC, SUB,

SBC, DAA)

•Logic operations (AND, OR, XOR, CPL)

•Rotation (RL, RR, RLC, RRC)

•Increment & decrement (INC, DEC)

•Branch decision (SZ, SNZ, SIZ, SDZ ....)

ALU not only saves the results of a data operation

but also change the stat us register.

Status register - STATUS

This 8 bit registe r (0AH) consists o f a zero flag

(Z), carry flag (C), auxiliary carry flag (AC),

overflow flag (OV), power down flag (PD) and

watch dog time-out flag (TO). It also records the

status information and controls the operation

sequence.

Except th e TO and P D flags, bits in th e status

to other registers. Any data written into the

status register will not change the TO or PD

flag. Operations related to the status register

may yield different results from those intended.

The TO and PD flags can be altered only by a

watch dog timer overflow, chip power-up, clear-

ing the watch dog time or executing the “HAL T”

instruction.

The Z, OV, AC and C flags generally reflect the

statuses of the latest operations.

The statu s re gister wi ll no t be pus hed onto the

stack automatically on entering the interrupt

sequence or executing the subroutine call. If the

status co ntents are imp ortant and the sub rou-

tine may corrupt the status register, the pro-

grammer must take precautions and save it

properly.

Interrupt

The HT827XX series provide an external inter-

rupt in addition to two internal timer/event

counter interrupts. The interrupt control regis-

ter (INTC; 0BH) includes interrupt control bits

to set the enable/disable and the interrupt re-

quest flags.

Once an interrupt subroutine is serviced, all

the other interrupts will be blocked (by clear-

ing the EMI bit). This scheme may prevent any

further interrupt nesting. Other interrupt re-

quests may happen during this interval but

only the interrupt request flag is recorded. If a

Labels Bits Function

C is set if an operation results in a carry during an addition operation or if a

borrow does not take place during a subtraction operation; otherwise C is

cleared. It is also affected by a rotate through carry instruction.

AC 1 AC is set if the op e ration resu lts in a carry ou t of the low nibbles in additio n or

if no borrow from the high nibble into the low nibble in subtraction takes place;

otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is

cleared.

OV 3 OV is s et if an ope ration re sults in a carry into th e highest-order b it but not a

carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD 4 PD is cleared by a system power-up or executing the “CLR WDT” instruction. PD

is set by executing the “HALT” instruction.

TO 5 TO is cleared by a system power-up or executing the “CLR WDT” or “HALT”

instructions. TO is set by a WDT time-out.

— 6 Undefined, read as “0”.

— 7 Undefined, read as “0”.

STAT US Register

HT827XX

16 4th Jan ’97

interrupt needs servicing within the service

routine, the programmer may set the EMI bit

and the corresponding bit of INTC, allowing

interrupt nesting. If the stack is full, the inter-

rupt request will not be acknowledged till the

SP is decremented, whether or not the related

interrupt is enabled. If immediate service is

desired, the stack has to be prevented from

being full.

All these interrupts have a wakeup capability.

As an interrupt is serviced, a control transfer

occurs by pushing the program counter onto the

stack and then branching to subroutines at the

specified location(s) in the program memory.

Only the program counter is pushed onto the

stack. The programmer must save the contents

of the register or status register (STATUS) in

advance if they are altered by an interrupt serv-

ice program which corru pts the de sired co ntrol

sequence.

External interrupts are triggered by a high to

low transition of INT. The related interrupt

request flag (EIF; bit 4 of INTC) are also set.

Whe n an interrup t is ena bled, the stack is not

full and the extern al interru pt is acti ve, a sub-

routine call to location 04H will occur. The in-

terrupt reque st flag (EI F) and EMI bits will be

clea red to disable other interrupts.

The sam pling rate counter interrupt is initial-

ized by setting a sampling rate counter inter-

rupt request flag (SRF; bit 5 of INTC), which is

caus ed b y a ti mer over flow. When an interrup t

is enabled, the stack is not full and the SRF bit

is set, a subroutine call to location 08H will

occur. The related i nterrup t requ est flag (SRF )

will be reset and the EMI bit be cleared to

disa ble further interrupts .

The internal timer/event counter interrupt is

initiali zed by setting a timer/event counter in-

terrup t reque st flag (TF; bi t 6 of IN TC), whi ch

is caused by a timer overflow. When an inter-

rupt is enabled, the stack is not full and the TF

bit is set, a subroutine call to location 0CH will

occur. The related interrupt request flag (TF)

will be reset and the EMI bit be cleared to

disa ble further interrupts .

During the execution of an interrupt subrou-

tine, other interrupt acknowledgments are all

held until the “RETI” instruction is executed or

the EMI bit and the related interrupt control bit

are set to 1 (if the stack is not full). To return

from an interrupt subroutine, “RET” or “RET I”

INTC

(0BH)

0EMI

Controls a master (global) interrupt

(1=enabled; 0=disabled)

1 EEI Controls an external interrupt

(1=enabled; 0=disabled)

2ESI

Controls a sampling rate counter interrupt

(1=enabled; 0=disabled)

3ETI

Controls a timer/event counter interrupt

(1=enabled; 0=disabled)

4EIF

External interrupt request flag

(1=active; 0=inactive)

5SRF

Sampl ing rate counte r request flag

(1=active; 0=inactive)

6TF

Internal timer/eve nt counter request flag

(1=active; 0=inactive)

7−Unused bit, read as “0”.

INTC Register

HT827XX

17 4th Jan ’97

may be invoked. RETI will set the EMI bit to

enable an interrupt service, but RET will not.

Interrupts occurring in an interval between the

rising edges of two consecutive T2 pulses will be

serviced at the latter of the two T2 pulses if the

corresponding interrupts are enabled. In the

case of simultaneous requests, they can be

masked by resetting the EMI bit. The following

table illustrates the priority of applying the

simu ltaneous requests:

No. Interrupt

Source Priority Vector

aExternal

Interrupt 104H

Sampling Rate

Counter Overflow 208H

Timer/Event

Counter Overflow 30CH

The timer/event counter interrupt request flag

(TF), external interrupt request flag (EIF), sam-

pling rate counter interrupt request flag (SRF),

enable timer/event counter bit (ETI), enable ex-

ternal interrupt bit (EEI), enable sampling rate

counter bit (ESI) and enable master interrupt bit

(EMI) make up of an interrupt control register

(INTC) which is located at 0BH in the data mem-

ory. EMI, EEI, ESI and ETI are used to control the

enable/disable status of interrupts. These bits

prevent the requested interrupt from being serv-

iced. Once the interrupt request flags (TF, SRF,

EIF) are all set, they will remain in the INTC

by a software instru ction.

The “CALL s ubroutine” had better not to be used

within the in terrupt subro utine. Th is is becau se

interrupts often occur in an unpredictable man-

ner or required to be serviced immediately in

certain applications. If only one stack is left and

enabling the interrupt is not well controlled, op -

eration of the “call” in the interrupt subroutine

will damage the original control sequence.

Oscillator configuration

The HT827XX series provide two kinds of oscilla-

tor circuits, namely RC and crystal oscillators, for

system clocks. Selection of the osci llator circuit

is determ ined b y ma sk o ptio n. No m atte r what

kind of oscillator type is chosen, the system

clock is provided by the signal. The HAL T mode

stops the system oscillator and resists in an

external signal for conserving power.

If an RC type of oscillator is used, an external

resistor between OSC1 and GND is required

and the range of the resistance h as to be from

51KΩ to 1MΩ. The system, divided by 4, is

available on OSC2, which synchronizes exter-

nal logic. The RC type of oscillator provides the

most cost-effective solution. Nonetheless, the

frequency of the oscillation may vary with VDD,

temperature and the chip itself due to process

variatio ns. It is, therefore , not suitab le for tim-

ing sensitive operati ons where an accurate os-

cillator frequency is demanded.

On the other hand, if a crystal type of oscillator

is used instead, a crystal across OSC1 and OSC2

is required, providing feedback and phase shift

for the oscillator. No other external components

are needed. The resonator can replace the crys-

tal and connects between OSC1 and OSC2 so

that a frequency reference can be derived. But

two external capacitors in OSC1 and OSC2 are

required.

The WDT oscillator is a free running on chip RC

oscillator, requiring no external components. The

WDT oscillator still works a period of approxi-

mately 78 µs even when the system enters the

power down mode and the system clock is termi-

nated. It nonetheless can be disabled by mask

option for conserv ing power.

Watch dog timer - WDT

The clock source of WDT is implemented by a

dedicated RC oscillator (WDT oscillator) or in-

struction clock (system clock di vided by 4), de-

System Oscillator

HT827XX

18 4th Jan ’97

cided by mask option. The watch dog timer is

designed to prevent a software malfunction or

sequence jumping to an unknown location with

unpredictable results. It can be disabled by

mask option. After it is disabled, all executions

related to WDT resul t in no operations.

WDT is first divided by 256 (8 stages) to get a

nominal time-out period of approximately 20 ms

once an internal WDT oscillator (RC type of oscil-

lat or no rmally with a pe riod of 78µs) is selected.

This time-out period may vary with temperature,

VDD and process variations. By invoking the

WDT prescaler, a longer time-out period can be

realized. W riting data to WS2, WS1 and WS0 (bits

2, 1 and 0 of WDTS) can derive different time-out

periods. If WS2, WS1 and WS0 all equal t o 1, t he

division ratio is up to 1:128, and the maximum

time-out per iod is 2. 6 sec onds.

WS2 WS1 WS0 Division Ratio

000 1:1

001 1:2

010 1:4

011 1:8

1 0 0 1:16

1 0 1 1:32

1 1 0 1:64

1 1 1 1:128

WDTS Register

If the WDT oscillator is disabled, the WDT clock

may still come from an instruction clock. It oper-

ates in the same manner except that WDT may

stops counting and loses its protecting purpose

in the HALT state. In this situation the logic

can only be re-initialized by external logic. The

high nibble and bit 3 of WDTS are reserved for

user’s defined flags. The programmer may use

these flags to indicate some specified statuses.

The on-chip RC oscillator (WDT OSC) is

strongly recommended if the device operates in

a noisy environment, since the HALT function

will stop the system clock.

Overf low of the WDT un der a no rma l oper ati on

initia lizes a “ch ip re se t” an d se ts th e s tatus b it

“TO”. It will initialize a “warm reset”, and only

PC and SP are reset to zero in the HALT mode.

To clear the contents of WDT (including the

WDT prescaler), three methods are adopted,

namely external reset (a low level to RES), soft-

ware instruction(s), and “HALT” instruction.

The software instruction(s) include “CLR WDT”

and the other sets - “CLR WDT1” and “CLR

WDT2”. Of these two types of instructions, only

one can be active at a time by mask option -

“CLR WDT times selection option”. If “CLR

WDT” is chosen (i.e., CLRWDT times equal

one), an y exe cution of the “CLR WDT” in struc-

tion will clear WDT. In the case that “CLR

WDT1” and “CLR WDT2” are selected (i.e.,

CLRWDT times equal two), these two instruc-

tions must be executed to clear WDT ; otherwise

WDT may reset the chip as a result of time-out.

Power down operati on - HALT

The HALT mode is initialized by the “HALT”

instruction and results in the following...

•The system oscillator is turned off but the

WDT oscillator still keeps running (if the

Watch Dog Timer

HT827XX

19 4th Jan ’97

WDT oscillator is selected).

•The contents of the on-chip RAM and regis-

ters remain unchanged.

•The WDT and WDT prescaler are cleared and

re-counted (if the clock of WDT is from the

WDT oscillator).

•All the I/O ports m ai nta in thei r ori gin al stat-

uses.

•The PD flag is set and the TO flag cleared.

The system can quit the HALT mode by an exter-

nal reset, interrupt, external falling edge signal

on port A or WDT overflow . An external reset leads

to device initialization and a WD T overflow per-

forms a “warm reset”. The reason for chip reset

can then be determined after examining the TO

and PD flags. The PD flag is cleared when the

system powers up or executes the “CLR WDT”

instruction and set when the “HALT” instruction

is executed. The TO flag is set if the WDT time-out

occurs, and causes a wake-up that resets only PC

and SP. The others maintain their original stat-

uses.

The port A wake-up and interrupt methods can be

considered as a continuation of normal execution.

Each bit in port A can be independently selected

to wake up the device by mask option. Awakening

from an I/O port stimulus, the program resumes

execution of the next instruction. However, if it is

awakening from an interrupt, two sequences may

happen. The program will resume execution at

the next instruction if the related interrupt(s) is

disabled or the interrupt(s) is enabled but the

stack is full. Nonetheless, if the interrupt is en-

abled and the stack is not full, a regular interrupt

response takes place.

Once the wake- up event(s) occurs, and t he system

clock comes fr om crystal, it t akes 1024 tSYS (sys-

tem clock period) to resume a normal operation.

That is to say, the HT827XX series will insert a

dummy period after the wake-up. If the system

clock, on the other h and, is from an RC type of

oscillator, it will continue operation. The actual

interrup t subrouti ne execution will be delayed

by one or more cycles if the wake-up results

from an interrupt acknowledge. It, on the other

hand, will be executed immediately after the

dummy period is finished if the wake-up results

in the next instruction execution.

To minimize power consumption, all the I/O

pins should be carefully man aged before enter-

ing the HALT mode.

Reset

There are three ways in which a reset can occur:

•RES reset during normal operation

•RES reset duri ng HALT

•WDT time-out reset during a normal operation

The WDT time-out during HALT is different

from other chip reset conditions, since it can

perform a “warm reset” that resets only PC and

SP, leaving the other circuits remain in their

origina l states. Som e registers will remain un -

changed during reset conditions. Most registers

are reset to the “initial condition” once the reset

conditions are met. The program can distin-

guish be tween differen t “chip res ets” by e xam-

ining the PD flag and TO flag.

TO P D RESET Conditions

00RES reset duri ng power -up

RES reset duri ng normal

operation

RES wake-up HALT

WDT time-out during normal

operation

1 1 WDT wake-up HALT

Note: “u” means “unchanged”.

To guarantee that the crystal oscillator is

started and stabilized, XST (Crystal Start-up

Timer) provides an extra-delay by an OSC mask

option. The extra-delay delays 1024 system

clock pulses when th e system awakes from the

HALT state or from system power-up and the

RES transforms low to high. XST is automat-

ically selected if the crystal oscillator is in-

voked. It, on the other hand, is disabled when

the RC oscillator is chosen. The XST delay is

added after XST is chosen and awakening from

the HALT state or the system powers up.

The reset duration comes only from RES if an

RC oscillator is selected. An extra delay, on the

other hand, is added during the power-up pe-

riod and any wakeup from HALT only if a crys-

tal oscillator is chosen instead.

HT827XX

20 4th Jan ’97

The HT827XX series provide another useful fea-

ture for purposes of testing and synchronization.

Releasing RES high will star t execution if RES

keeps low long enough.

PC 000H

Interrupt Disabled

Prescaler Cleared

WDT Cleared. After a

master reset, WDT

begins counting.

Timer/Event Counter Off

Input/Output Ports Input mode

SP Point to the top of

the stack.

Reset Circuit

The states of the registers are summarized in the following table:

(Power On)

WDT T ime-o ut

(Normal

Operation)

RES Reset

(Normal

Operation)

RES Reset

(HALT) WDT Time-out

(HALT)

TMR xxxx xxxx uuuu uuuu uu uu uuuu uuuu uuuu uuuu uuuu

TMRC 00-0 1—- 00-0 1—- 00-0 1—- 00-0 1—- uu-u u—-

PC 000H 000H 000H 000H 000H∗

MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu

ACC xxxx xxxx u uuu uuuu uu uu uuuu uuuu uuuu uuuu uuuu

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLH —xx xxxx —uu uuuu —uu uuuu —uu uuuu —uu uuuu

STATUS —00 xxxx —1u uuuu —uu uuuu —01 uuuu —11 uuuu

INTC —00 -000 —00 -000 —00 -000 —00 -000 —uu -uuu

WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 111 1 1111 1111 1 111 1111 1111 uuuu uuu u

PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 111 1 1111 1111 1 111 1111 1111 uuuu uuu u

PC —11 1111 —11 1111 —11 1111 —11 1111 —uu uuuu

PCC —11 1111 —11 1111 —11 1111 —11 1111 —uu uuuu

Notes: “*” mean s “warm reset”.

“u” means “un c ha ng e d”.

“x” me ans “unkno wn”.

HT827XX

21 4th Jan ’97

Sampling rate counter

The HT827XX series offer a sampling rate

counter. This counter contains a 5 bit program-

mable count-up counter. The clock may come

from 128KHz or 2KHz by code option.

When the 128KHz clock is selected, 26 kinds of

sampling rate are provided for a voice synthe-

sizer. Following is a table of the 26 kinds of

sampling rates:

Code Freq. Code Freq.

xx00 0000 3.50KHz xx00 1101 5.89KHz

xx00 0001 3.61KHz xx00 1110 6.21KHz

xx00 0010 3.72KHz xx00 1111 6.58KHz

xx00 0011 3.86KHz xx01 0000 6.99KHz

xx00 0100 3.99KHz xx01 0001 7.46KHz

xx00 0101 4.14KHz xx01 0010 7.99KHz

xx00 0110 4.30KHz xx01 0011 8.61KHz

xx00 0111 4.48KHz xx01 0100 9.32KHz

xx00 1000 4.66KHz xx01 0101 10.17KHz

xx00 1001 4.86KHz xx01 0110 11.19KHz

xx00 1010 5.08KHz xx01 0111 12.43KHz

xx00 1011 5.33KHz xx01 1000 13.98KHz

xx00 1100 5.59KHz xx01 1001 15.98KHz

Sampling Rate Ta ble

Note: “XX” means don’t care.

On the other hand, when the 2KHz clock is

chosen, 32 kinds of time periods of the envelope

decay is offered. Following is a table of the

envelope decay:

Code Freq. Code Freq.

xx10 0000 54.6Hz xx11 0000 109.3Hz

xx10 0001 56.4Hz xx11 0001 116.5Hz

xx10 0010 58.3Hz xx11 0010 124.9Hz

xx10 0011 60.3Hz xx11 0011 134.5Hz

xx10 0100 62.4Hz xx11 0100 145.7Hz

xx10 0101 64.7Hz xx11 0101 158.9Hz

Code Freq. Code Freq.

xx10 0110 67.2Hz xx11 0110 174.8Hz

xx10 0111 69.9Hz xx11 0111 194.2Hz

xx10 1000 72.8Hz xx11 1000 218.5Hz

xx10 1001 76.0Hz xx11 1001 249.7Hz

xx10 1010 79.5Hz xx11 1010 291.3Hz

xx10 1011 83.2Hz xx11 1011 349.6Hz

xx10 1100 87.4Hz xx11 1100 437.0Hz

xx10 1101 92.0Hz xx11 1101 582.7Hz

xx10 1110 97.1Hz xx11 1110 874.0Hz

xx10 1111 102.8Hz xx11 1111 1.75KHz

Envelope Decay Table

Note: “xx” means don’ t care.

One o f the rel ative cou nter values is preloa ded

to the sampling rate counter after a code is

written to the counter (SRC;23H). Once the

sampling rate counter starts counting, it will

count from its current contents to 1FH. The

counter is reloaded from the sampling rate

counter preload register, and generates an in-

terrupt request flag (SRF; bit 5 of INTC) if

overflow of the divide-by-1 counter occurs.

To enable a counting operation, the ON bit

(SRON; bit 7 of TEMP O) of the counte r shou ld

be set to 1. Overflow of the sampling rate

counter is o ne of the wake-up sources. Writing

a “0” to ESI will disable the interrupt service.

Writing data to the sampling rate preload reg-

ister will also reload the data to the sampling

rate counter in the case of 1F condition of the

sampling rate counter . Data written to the sam-

pling rate counter will, on the other hand, be

kept only in the co unter preload register if the

counter is turned on. The sampling rate counter

still goes on working till an overflow of the

divide-by-1 counter occurs.

The clock is blocked to avoid errors once the sam-

pling rate counter is read. The programmer

should take the counting error into account since

blocking of the clock may result in a counting

error.

HT827XX

22 4th Jan ’97

Labels Bits Function

SR0~SR4 0~4 To define an voice sampling

rate or envelope decaying

time

2K/128K 5 To define an input clock

source (0=128K; 1=2K)

— 6~7 Unused bits, read as “0”.

SRC Register

Ti mer/ Ev en t co un t e r

The HT827XX series provide a timer/event

counter. This counter contains an 8 bit prog ram-

mable count-up counter. The clock may come

from an external source or the system clock

divided by 4. Only one reference time-base is

available when an internal instruction clock is

selected. The external clock input allows the

user to count external events, measure time in-

tervals or pulse widths, or g enerat e an accurat e

time base.

There are two regist ers related to the timer/ event

counter, namely TMR ([10H]) and TMRC ([11H]).

Two physical registers are mapped to the TMR

location. Writing TMR makes the starting value

put in the timer/event counter preload register

and reading it gets the contents of the timer/event

counter. TMRC is a timer/event counter control

The TM0 and TM1 bits define the operation

mode. The event counting mode counts external

events, indicating that the source of the clock is

from an external (TMR) pin. The timer mode

functions as a normal timer with the clock

source coming from an instruction clock. The

pulse width measurement mode can be used to

count a high to low level duration of an external

signal (TMR). This counting is based on the

instruction clock.

In the event counting or timer mode, after the

timer/event counter starts counting, it will count

from its current contents to FFH. Once an over-

flow occurs, the counter is reloaded from the

timer/event counter preload register and gener-

ates an interrupt request flag ( TF; bit 6 of INTC).

In the pulse width measurement mode with the

TON and TE bits equal to one, after TMR re-

ceives a transient from low to high (or high to

low when the TE bit is “0”), it will start counting

till it returns to the original level and resets the

TON. T he meas ure d resu lt sti ll re mains in th e

timer/event counter even when the activated

transient re-occurs. In other words, only one

cycle can be measured till TON is set. The cycle

measu rement will go on functio ning as lon g as

further transient pulses are received. In this

opera tion mod e, the ti mer/event counter sta rts

countin g not accordin g to the logic level b ut to

the transient edges. In the case of a counter

overflow, the counter is reloaded from the

timer/event counter preload register and issues

an interrupt request, like the other two modes.

The timer ON bit (TON ; b it 4 of TMRC ) should

be set to 1 to enable a counting operation. In the

pulse width measurement mode, TON will be

cleared automatically after the measurement

cycle is completed. In the other two modes, it

TON can be reset only by instructions. The

overflow of the timer/event counter is one of the

wake-up s ources. Writin g a “0” to E TI will dis-

able the interrup t se rvice no matter what kind

of operation mode is chosen.

In the case of the timer/event counter OFF con-

dition, wri ting data to the timer/event counter

preload register will also reload it to the

timer/event counter. Data written to the

timer/event counter will however be kept in the

timer/event counter preload register if the

timer/event counter is turned on. The timer/

event counter will be still operating till an over-

flow occurs.

The clock will be blocked to avoid errors after

the timer/event coun ter (reading TMR) is read.

The programmer should take the counting error

into accoun t si nce clock b locking may result in

a counting error.

Sampling Rate Counter

HT827XX

23 4th Jan ’97

Labels (TMRC) Bits Function

— 0-2 Unused bits, read as “0”.

TE 3 To define the TMR active edge of a timer/event counter

(0=active on low to high; 1=active on high to low)

TON 4 To enable/disable timer counting (0=disabled; 1=enabled)

— 5 Unused bits, read as “0”.

TM0

TM1 6

To define the operation mode

01=Event count mo de (External clock)

10=Timer mode (Internal clock)

11=Pulse width measurement mode

00=Unused

TMRC Register

Timer/Event Counter

Tone and mel ody generator

The HT827XX series provide a tone frequency

(BEAT; 28H) as well as tempo frequency register

(TEMPO; 29H) for generating melody and sound

effects.

The LSI can generate four octaves, labeled from

C2# to C6. Desired frequencies can be obta ined

by first writing the related data into a tone

frequency register (TONE; 2A H) and then ena-

bling the tone counter. A Tone frequence is gen-

erated and remained if the tone counter

overflows.

Labels Bits Function

TN0~

TN3 0~3 To define the tone frequency

(refer to the tone frequency

table)

OCT0

OCT1 4

To define the 4 octave tone

frequencies (refer to the tone

frequency table)

— 6 Unused bit, read as “0”.

TEN 7 To enable/disable the tone

counter (0=disabled;

1=enabled)

HT827XX

24 4th Jan ’97

The BEAT register counts melody beats. Bit 7

(BTO) of the BEA T register is set when the beat

counter ove rflows. No interrupt is gen erated if

the beat counter overflows. So bit 7 (BTO) of the

BEAT register must be polled to generate cor-

rect beat frequencies. After reading the BTO

status, the bit 7 should be cleared by the pro-

grammer to avoid the malfunction of the next

polling.

Labels Bits Function

B0~B6 0~6 To de fine the beat frequency

(refer to the beat frequency

table)

BTO 7 B TO is set when the beat

counter is time-out.

BEAT Register

Code Beat

1xxx xxxx Beat time-out

000 0 00 00 1/24 BEAT

0000 00 10 1/8 BEAT

0000 00 11 1/6 BEAT

0000 01 01 1/4 BEAT

0000 01 11 1/3 BEAT

0000 10 11 1/2 BEAT

0000 11 11 2/3 BEAT

0001 00 01 3/4 BEAT

0001 01 11 1 BEAT

0010 00 11 3/2 BEAT

0010 1111 2 BEATS

0100 0100 3 BEATS

0101 1111 4 BEATS

0111 0111 5 BEATS

Other codes —

Note: “—” means unknown beats.

BEAT Frequency Table

TONE Counter

BEAT Counter

HT827XX

25 4th Jan ’97

Code Frequency Tone Code Frequency Tone

1x00 0000 — — 1x10 0000 — —

1x00 0001 138.5Hz C2#1x10 0001 553.8Hz C4#

1x00 0010 146.4Hz D2 1x10 0010 585.7Hz D4

1x00 0011 155.4Hz D2#1x1 0 0011 621.5Hz D4#

1x00 0100 164.5Hz E 2 1x10 0100 658.1Hz E4

1x00 0101 174.8Hz F2 1x1 0 0101 699.2Hz F4

1x00 0110 185.2Hz F2#1x10 0110 74 0.9Hz F4#

1x00 0111 195.6Hz G2 1x10 0111 782.3Hz G4

1x00 1000 207.2Hz G2#1x1 0 1000 828.7Hz G4#

1x00 1001 220.2Hz A 2 1x10 1001 880.9Hz A4

1x00 1010 233.1Hz A2#1x10 1010 932.3Hz A4#

1x00 1011 247.5Hz B 2 1x10 1011 990.0Hz B4

1x00 1100 261.4Hz C3 1x10 11 00 1045.6Hz C5

1x00 1101 — — 1x10 1101 — —

1x00 1110 — — 1x10 1110 — —

1x00 1111 — — 1x10 1111 — —

1x01 0000 — — 1x11 0000 — —

1x01 0001 279.6Hz C3#1x11 0001 1107.7Hz C5#

1x01 0010 292.9Hz D3 1x11 0010 1171.5Hz D 5

1x01 0011 310.8Hz D3#1x11 0011 1243.1Hz D5#

1x01 0100 329.0Hz E3 1x11 01 00 1316.2Hz E5

1x01 0101 349.6Hz F3 1x11 01 01 1398.4Hz F5

1x01 0110 370.4Hz F3#1x11 0110 1481.8Hz F5#

1x01 0111 391.2Hz G3 1x11 0111 1564.7Hz G 5

1x01 1000 414.4Hz G3#1x11 1000 1657.4Hz G5#

1x01 1001 440.5Hz A3 1x11 10 01 1761.8Hz A5

1x01 1010 466.1Hz A3#1x11 1010 1864.6Hz A5#

1x01 1011 495.0Hz B3 1x11 10 11 1980.1Hz B5

1x01 1100 522.8Hz C4 1x11 11 00 2091.1Hz C6

1x01 1101 — — 1x11 1101 — —

1x01 1110 — — 1x11 1110 — —

1x01 1111 — — 1x11 1111 — —

TONE Frequency Table

Note: “x” means don’t care. “—” means invalid.

HT827XX

26 4th Jan ’97

The TEMPO register counts melodies. A tempo

frequency is generated after tempo data are

loaded and the TEMPO counter is enabled also.

The tempo decides the beat time p eriod.

Labels Bits Function

TN0~

TN3 0~3 To define the tempo frequency

(refer to the tempo

fr eq uency tab le)

— 4,5 Unused bits, read as “0”.

TMPEN 6 To enab le/d isabl e the temp o

counter (0=disabled;

1=enabled)

SRON 7

To enable/disable the D/A

output, sampling rate

counter and counter ROM

(0=disable d; 1=enabled)

Voice ROM

The HT827XX series include a ROM for storing

sound and tone (melody) data. Coded data can

be saved in an internal mask ROM by changing

one l aye r o f the m ask a fter the so un d an d ton e

(melody) sources are coded by Holtek’s tools.

The voice ROM size for HT827XX series are

shown as following.

Item Voice ROM Size

HT82700 128K × 8

HT82720 96K × 8

Item Voice ROM Size

HT82740 64K × 8

HT82770 64K × 8

HT82780 32K × 8

The handshaking between the microcontroller

and voice ROM is through a ROM control register

(ROMC; 2CH). To enable the voice ROM, the bit 7

of the TEMPO register should be set as “1”. The

related ROM address has to be saved in the ROM

control register first if the microcontroller at-

tempts to read the sound or tone (melody) d ata in

the mask ROM. The ROM is comprised by a set of

address counters internally. After the microcon-

troller finishes reading a byte of data, its internal

address counter will automatically be increased

by one. In this case, r eading continuous data only

requires loading the start ing address to the ROM

control regi ster.

Code TEMPO CLK TEMPO BPM

0000 30.5Hz 68.3

0001 32.55Hz 72.8

0010 34.88Hz 78.0

0011 37.56Hz 84.0

0100 40.69Hz 91.0

0101 44.39Hz 99.3

0110 48.83Hz 109.3

AD0~AD3

D4~D7

D0~D3

Data Register

(high nibbl e)

Voice

ROM

Data Register

(low nibble)

A1X~A12

Address

Counter

Address

Counter

Address

Counter

Address

Counter

A11~A8

A7~A4

A3~A0

ROMC

TEMPO.7

X=4, 5 or 6

Voice ROM

HT827XX

27 4th Jan ’97

Code TEMPO CLK TEMPO BPM

0111 54.25Hz 121.4

1000 61Hz 136.6

1001 65.1Hz 145.7

1010 69.8Hz 156.1

1011 75.12Hz 168.1

1100 81.38Hz 182.1

1101 88.78Hz 198.6

1110 97.66Hz 218.5

1111 108.5Hz 242.8

TEMPO Freq ue ncy Tabl e

The lower-order nibble is valid whereas the

higher-ord er nibble inva lid of the RO M contro l

dress has to be divided into four nibbles, and

written into the ROM control register four

times with respect to the divided four nibbles.

The lower-order nibble and higher-order nibble

data can th en be rea d back by two time ’s read-

ing after sound or tone (melody) starting ad-

dress is written. For example, if the starting

address of the sound data to be read is 0CF0H,

the program of reading one byte of sound or tone

(melody) data is as follows:

Read-New-Data:

SET TEMPO.7

MOV A, 00H

MOV [ROMC],A; Write the first nibble

address

MOV A,0FH

MOV[ROMC],A; Write the second

nibble address

MOV A,0CH

MOV [ROMC],A; Write the th ird

nibble address

MOV A,00H

MOV [ROMC],A; Write the fou rth

nibble address

MOV A,[ROMC]; Read the lower-

or der ni bble data

MO V [DATA ],A ;

MOV A,[ROMC]; Read the high-order

nibble data

SWAPA [ACC];

ORM A,[DATA]; Combine the lower-

order data and

higher-order data

In p ut/Output po r ts

The HT827XX series include 24 bidirectional

input/output lines, labeled from PA to PC,

which are mapped to the data memories of

Input/Output Ports

HT827XX

28 4th Jan ’97

[12H], [14H] and [16H], respectively. All of

these I/O ports can be used as input and output

operations. For input operation, these ports are

non-latched, i.e., the inputs must be ready at

the T2 rising edge of the instruction “MOV

A,[m]” (m=12, 14 or 16H). For output operation,

all the data are latched and remain unchanged

till the output latch is re-written.

Each I/O line has its own control register (PAC,

PBC an d P CC ) to co ntro l th e inp ut /outp ut con -

figuration. W ith a control register , a CMOS out-

put or schmitt trigger input can be

re-configured dynamically (i.e., on-the-fly)with

or without pull-high resistor structures under a

software control. To function as an input, the

corresponding latch of a control register must

write “1”. The pull-high resistance will be auto-

matically exhibited if the pull-high option is

chosen. The input source(s) also depends on the

control register. If the bit of the control register

bit “1”, the input will read the pad state. If it is

“0”, the contents of the latches will move to the

internal bus. The latter is possible only in the

“read-modify-write” instruction. For the output

function, CMOS is the only configuration.

Thes e control registers are all mappe d to loca -

tions 13H, 15H and 17H.

Thes e input/ou tp ut li ne s stay a t a high level or

floating (decided by mask option) after a chip

reset. Each bit of the input/output latches can

be set or cleared by the “SET[m].i” and

“CLR[m].i” (m=12H, 14H or 16H) instructions.

Some instructions will first input data and then

follow the output operations. For instance,

“SET[m].i”, “CLR[m].i”, “CPL[m], and “CPLA[m]”

read the entire port state into the CPU, execute

the defined operations (bit-operation), and then

write the results back to the latches or accumu-

lator.

Each line of port A is cap able of waking up the

device. The highest two bits of port C are not

physically implemented. A “0” will return on

reading the highest two b its, but writing them

will result in no operations.

Mas k option

The follo wing ta ble il lustrates 5 ki nds o f mask

option in the HT827XX series. All of them have

to be defined to ensure a proper system func-

tion.

No. Mask Opti on

OSC type selection

This option decides the selection of a

system clock to be an RC or crystal type

of oscillator.

WDT source selection

Three selections a re provide d, namely

on-chip RC oscillator, instruction clock

and WDT disable.

CLRWDT times selection

This option defines the way of clearing

WDT by instructions. “Once” means

“CLR WDT” can clear WDT. “Twice”

means WDT can be cleared only if both

“CLR WDT1” and “CLR WDT2” are

executed.

Wake-up selection

This option defines the activity of the

wake-up function. All of the external

I/O pins (PA only) are capable of

waking up the chip from a HALT mode.

Pull-high selection

This option decides whether or not the

pull-high resistance exists in the input

mode of the I/O ports. Each bit of the

I/O port can be independently selected.

HT827XX

29 4th Jan ’97

Instruction Set

Instruction set sum mary

Mnemonic Description Flag Affected

Arithmetic

ADD A,[m]

ADDM A,[m]

ADD A,x

ADC A,[m]

ADCM A,[m]

SUB A,x

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

Add data memory to ACC

Add ACC to data memory

Add immediate data to ACC

Add data memory to ACC with carry

Add ACC to register with carry

Subtract immediate data from ACC

Subtract data memory from ACC

Subtract data memory from ACC with result in data memory

Subtract data memory from ACC with carry

Subtract data memory from ACC with carry leaving result in

data memory

Decimal adjust ACC for addition with result in data memory

Z,C,AC,OV

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

OR A,x

XOR A,x

CPL [m]

CPLA [m]

AND data memo ry to ACC

OR data memory to ACC

Exclusive-OR data memory to ACC

AND ACC to data memory

OR ACC to data memory

Exclusive-OR ACC to data memory

AND imm ediate data to A CC

OR immed iate data to AC C

Exclusive-OR immediate data to ACC

Complement data memory

Complement data memory with result in ACC

Increment &

Decrement

INCA [m]

INC [m ]

DECA [m]

DEC [m]

Increment data memory with result in ACC

Increment data memory

Decrement data memory with result in ACC

Decrement data memory

HT827XX

30 4th Jan ’97

Mnemonic Description Flag Affected

Rotate

RRA [m]

RR [m]

RRCA [m]

RRC [m]

RLA [m]

RL [m]

RLCA [m]

RLC [m]

Rotate data memory right with result in ACC

Rotate data memory right

Rotate data memory right through carry with result in ACC

Rotate data memory right through carry

Rotate data memory left with result in ACC

Rotate data memory left

Rotate data memory left through carry with result in ACC

Rotate data memory left through carry

None

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move data memory to ACC

Move ACC to data memory

Move immediate data to AC C

None**

None

Bit Operation

CLR [m].i

SET [m].i Clear bit of data memory

Set bit of data memory None

None

Branch

JMP addr

SZ [m]

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

RET A,x

RETI

Jump unconditionally

Skip if data memory is zero

Skip if data memory is zero with data movement to ACC

Skip if bit i of data memo ry is zero

Skip if bit i of data memory is not zero

Skip if increment data memory is zero

Skip if decrement data memory is zero

Skip if increment data memory is zero with result in ACC

Skip if decrement data memory is zero with result in ACC

Subroutine call

Return from subroutine

Return from subroutine and load immediate data to ACC

Return from interrupt

None

Table Read

TABRDC [m]

TABRDL [m] Read ROM code (current page) to data memory and TBLH

Read ROM code (last page) to data memory and TBLH None

None

HT827XX

31 4th Jan ’97

Mnemonic Description Flag Affected

Miscellaneous

NOP

CLR [m]

SET [m]

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

No operation

Clear data memory

Set data memory

Clear Watchdog timer

Pre-clear Watchdog timer

Swap nibbles of data memory

Swap nibbles of data memory with result in ACC

Enter power down mode

None

TO,PD

TO*,PD*

None

TO,PD

Notes:

x = 8 bit immediate data

m = 7 bit data memory address

A = accumulator

i = 0...7 number of bits

addr = 1 1 bit program memory address

√ = Flag(s) is affected

– = Flag(s) is unaffected

* = Flag (s) may be affected by the execution status.

** = For the old version of the E.V. chip, the zero flag (Z) can be affected by executing the

MOV A,[M] instruction.

For the new version of the E.V. chip, the zero flag will not be altered after executing the

MOV A,[M] instruction.

HT827XX

32 4th Jan ’97

Instruction Definition

ADC A,[m] Add data memory and carry to accumulator

Description The contents of the specified data memory accumulator and carry flag are

added simultaneously, leaving the result in the accumulator.

Operation ACC ← ACC+[m]+C

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

ADCM A,[m] Add accumulator and carry to data memory

Description The contents of the specified data memory accumulator and carry flag are

added simultaneously, leaving the result in the specified data memory.

Operation [m] ← ACC+[m]+C

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

ADD A,[m] Add data memory to accumulator

Description The contents of the specified data memory and accumulator are added.

The result is stored in the accumulator.

Operation ACC ← ACC+[m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

ADD A,x Add immediate data to accumulator

Description The contents of the accumulator and specified data are added, leaving the

result in the accumulator.

Operation ACC ← ACC+x

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

HT827XX

33 4th Jan ’97

ADDM A,[m] Add accumulator to data memory

Description The contents of the specified data memory and accumulator are added.

The result is stored in the data memory.

Operation [m] ← ACC+[m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

AND A,[m] Logical AND accumulator with data memory

Description Data in the accumulator and specified data memory perform a bitwise logi-

cal_AND operation. The result is stored in the accumulator.

Operation ACC ← ACC “AND” [m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

AND A,x Logical AND immediate data to accumulator

Description Da ta in the accumulator an d specified data perform a bitwise logical_AN D

operation. The result is stored in the accumulator.

Operation ACC ← ACC “AND” x

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

ANDM A,[m] Logical AND data memory with accumulator

Description Data in the specified data memory and accumulator perform a bitwise logi-

cal_AND operation. The result is stored in the data memory.

Operation [m] ← ACC “ AND” [ m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

HT827XX

34 4th Jan ’97

CALL addr Subroutine call

Description The instruction unconditionally calls a subroutine which is located at the

indicated address. The program counter increments once to obtain the ad-

dress of the next instruction, and pushes this onto the stack. The indicated

address is then loaded. Program execution continues with the instruction

at this address.

Operation Stack ← PC+1

PC ← addr

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

CLR [m] Clear data memory

Description The contents of the specified data memory are cleared to zero.

Operation [m] ← 00H

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

CLR [m]. i Clear bit of data memory

Description Bit i of the specified data memory is cleared to zero.

Operation [m].i ← 0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

CLR WDT Clear watch dog timer

Description The WDT and WDT Prescaler are cleared (re-count from zero). The power

down bit (PD) and time-out bit (TO) are both cleared.

Operation WDT & WDT Prescaler ← 00H

PD & TO ← 0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––00––––

HT827XX

35 4th Jan ’97

CLR WDT1 Preclear watch dog timer

Description The PD, TO flags, WDT and the WDT Prescaler are all cleared (re-count

from zero) if the other preclear WDT instruction has been executed. Execu-

tion only of this instruction without the other preclear instruction sets the

indicated flag, which implies that this instruction is executed and the PD

and TO flags remain unchanged.

Operation WDT & WDT Prescaler ← 00H*

PD & TO ← 0*

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––0*0*––––

CLR WDT2 Preclear watch dog timer

Description The PD, TO flags, WDT and the WDT Prescaler are all cleared (re-count

from zero) if the other preclear WDT instruction has been executed. Execu-

tion only of this instruction without the other preclear instruction sets the

indicated flag, which implies that this instruction is executed and the PD

and TO flags remain unchanged.

Operation WDT & WDT Prescaler ← 00H*

PD & TO ← 0*

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––0*0*––––

CPL [m] Complement data memory

Description Each bit of the specified data memory is logically complemented (1’s com-

plement). Bits which previously contained a one are changed to zero and

vice-versa.

Operation [m] ← [m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

HT827XX

36 4th Jan ’97

CPLA [m] Complement data memory-place result in accumulator

Description Each bit of the specified data memory is logically complemented (1’s com-

plement). Bits which previously contained a one are changed to zero and

vice-versa. The complemented result is stored in the accumulator and the

contents of the data memo ry remain unchanged.

Operation ACC ← [m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

DAA [m] Decimal-Adju st accumulator for addition

Description The value of the accumulator is adjusted to a BCD (Binary Code Decimal)

code. If bits 0~3 of the accumulator are greater than 9 or AC is one, six is

added to the low-order nibble of the accumulator, deriving a BCD digit in

the low-order nibb le. Similarly, if bits 4~7 of the accumulator are greater

than 9 or C is one, six is added to the high-order nibble of the accumulator,

generating a BCD digit in the high-order nibble. The result is stored in the

data memory.

Operation If ACC.3~ACC.0 >9 or AC=1

then ([m].3~[m].0) ← (ACC.3~ACC.0)+6

else ([m].3~[m].0) ← (ACC.3~ACC.0)

and

If ACC.7~ ACC. 4 >9 or C= 1

then ([m].7~[m].4) ← (ACC.7~ACC.4)+6,C=1

else ([m].7~[m].4) ← (ACC.7~ACC.4),C=C

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––––√

DEC [m] Decrement data memory

Description Data in the specified data memory are decremented by one.

Operation [m] ← [m]–1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

HT827XX

37 4th Jan ’97

DECA [m] Decrement data memory-place result in accumulator

Description Data in the specified data memory are decremented by one, leaving the re-

sult in the accumulator. The contents of the data memory remain un-

changed.

Operation ACC ← [m]–1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

HALT Enter power down mod e

Description This instruction stops program execution and turns off the system clock.

The contents of the RAM and registers are retained. The WDT and pres-

caler are cleared. The power down bit (PD) is set and the WDT time-out bit

(TO) is cleared.

Operation PC ← PC+1

PD ← 1

TO ← 0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––01––––

INC [m] Increment data memory

Description Da ta in the specified data memory are incremented by one.

Operation [m] ← [m]+1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

INCA [m] Increment data memory-place result in accumulator

Description Da ta in the specified data memory are incremented by one, leaving the re-

sult in the accumulator. The contents of the data memory remain un-

changed.

Operation ACC ← [m]+1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

HT827XX

38 4th Jan ’97

JMP addr Direct Jump

Description Bits 0~10 of the program counter are rep laced with the directly–specified

addresses unconditionally, and the control is passed to this destination.

Operation PC ← addr

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

MOV A,[m] Move data memory to accumulator

Description The contents of the specified data memor y are copied to the accumulator.

Operation ACC ← [m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––**––

MOV A,x Move immediate data to accumulator

Description The 8 bit data specified by the code is loaded into the accumulator.

Operation ACC ← x

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

MOV [m],A Move accumulator to data memory

Description The contents of the accumulator are copied to the specified data memory

(one of the data memory).

Operation [m] ← ACC

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

HT827XX

39 4th Jan ’97

NOP No operation

Description No operation is performed. Execution continues with the next instruction.

Operation PC ← PC+1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

OR A,[m] Logical OR accumulator with data memory

Description Data in the accumulator and specified data memory (one of the data mem-

ory) perform a bitwise logical_OR operation. The result is stored in the ac-

cumulator.

Operation ACC ← ACC “OR” [m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

OR A,x Logical OR immediate data to accumulator

Description Da ta in the accumulator an d specified data perform a bitwise logical_OR

operation. The result is stored in the accumulator.

Operation ACC ← ACC “OR” x

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

ORM A,[m] Logical OR data memory with accumulator

Description Data in the data memory (one of the data memory) and accumulator per-

form a bitwise logical_OR operation. The result is stored in the data mem-

ory.

Operation [m] ← ACC “O R” [m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

HT827XX

40 4th Jan ’97

RET Return from subroutine

Description The program counter is restored from the stack. This is a two cycle instruc-

tion.

Operation PC ← Stack

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

RET A,x Return and place immediate data in accumulator

Description The program counter is restored from the stack and the accumulator

loaded with the specified 8-bit immediate data.

Operation PC ← Stack

ACC ← x

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

RETI Return from interrupt

Description The program counter is restored from the stack, and interrupts enabled by

setting the EMI bit. EMI is an enable master(global) interrupt bit (bit 0;

Operation PC ← Stack

EMI ← 1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

RL [m] Rotate data memory left

Description The contents of the specified data memory are rotated one bit left with bit

7 rotated into bit 0.

Operation [m].(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)

[m].0 ← [m].7

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

HT827XX

41 4th Jan ’97

RLA [m] Rotate data memory left-place result in accumulator

Description Data in the specified data memory are rotated one bit left with bit 7 ro-

tated into bit 0, leaving the rotation result in the accumulator. The con-

tents of the data memory remain unchanged.

Operati on ACC. (i+1) ← [m]. i; [m].i:bit i of the data memory (i=0-6)

ACC.0 ← [m].7

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

RLC [m] Rotate data memory left through carry

Descrip tion The contents of the specifie d data memory and carry flag are rotated one

bit left. Bit 7 replaces the carry bit; the original carry flag is rotated to the

bit 0 position.

Operation [m].(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)

[m].0 ← C

C ← [m].7

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––––√

RLCA [m] R otate left through carry-place result in accumulator

Description Data in the specified data memory and carry flag are rotated one bit left.

Bit 7 replaces the carry bit and the original carry flag is rotated to the bit 0

position. The rotation result is stored in the accumulator but the contents

of the data memory remain unchan ged.

Operati on ACC. (i+1) ← [m]. i; [m].i:bit i of the data memory (i=0-6)

ACC.0 ← C

C ← [m].7

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––––√

HT827XX

42 4th Jan ’97

RR [m] Rotate data memory right

Description The contents of the specified data memory are rotated one bit right with

bit 0 rotated to bit 7.

Operation [m].i ← [m].(i+1); [m].i:bit i of the data m emory (i=0-6)

[m].7 ← [m].0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

RRA [m] Rotate right-place result in accumulator

Description Data in the specified data memory are rotated one bit right with bit 0 ro-

tated to bit 7, leaving the rotation result in the accumulator. The contents

of the data memory remain unchan ged.

Operation ACC.(i) ← [m].(i+1); [m ].i:bit i of the da ta me mo ry (i=0-6)

ACC.7 ← [m]. 0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

RRC [m] Rotate da ta memory right through carry

Descrip tion The contents of the specifie d data memory and carry flag are rotated one

bit right. Bit 0 replaces the carry bit; the original carry flag is rotated to

the bit 7 position.

Operation [m].i ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)

[m].7 ← C

C ← [m].0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––––√

HT827XX

43 4th Jan ’97

RRCA [m] Rotate right through carry-place result in accumulator

Description Data of the specified data memory and carry flag are rotated one bit right.

Bit 0 replaces the carry bit and the original carry flag is rotated to the bit 7

position. The rotation result is stored in the accumulator. The contents of

the data memory remain unchanged.

Operation ACC.i ← [m ].(i+1); [m].i:bit i of the data memory (i=0-6)

ACC.7 ← C

C ← [m].0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––––√

SBC A,[m] Subtract data memory and carry from accumulator

Description The contents of the specified data memory and the complement of the

carry flag are subtracted from the accumulator, leaving the result in the ac-

cumulator.

Operation ACC ← ACC+[m]+C

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

SBCM A,[m] Subtract data memory and carry from accumulator

Description The contents of the specified data memory and the complement of the

carry flag are subtracted from the accumulator, leaving the result in the

data memory.

Operation [m] ←ACC+[m]+C

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

HT827XX

44 4th Jan ’97

SDZ [m] Skip if decrement data memory is zero

Description The contents of the specified data memory are decremented by one. If the

result is zero, the next instruction is skipped. If the result is zero, the fol-

lowing instruction, fetched during the current instruction execution, is dis-

carded and a dummy cycle is rep laced to get a proper instruction. This

makes a 2 cycle instruction. Otherwise proceed with the next instruction.

Operation Ski p if ([m]–1)=0, [m] ← ([m]–1)

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

SDZA [m] Decrement data memory-place result i n ACC, sk i p if zero

Description The contents of the specified data memory are decremented by one. If the

result is zero, the next instruction is skipped. The result is stored in the ac-

cumulator but the data memory remains unchanged. If the result is zero,

the following instruction, fetched during the current instruction execution,

is discarded and a dummy cycle is replaced to get a proper instruction,

making a 2 cycle instruction. Otherwise proceed with the next instruction.

Operation Skip if ( [m]–1) =0, ACC ← ([m]–1)

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

SET [m] Set data memory

Description Each bit of the specified data memory is set to one.

Operation [m] ← FFH

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

SET [m]. i Set bit of data memory

Description Bit “i” of the specified data memory is set to one.

Operation [m].i ← 1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

HT827XX

45 4th Jan ’97

SIZ [m ] Skip if increment data memory is zero

Description The contents of the specified data memor y are incremented by one. If the

result is zero, the following instruction, fetched during the current instruc-

tion execution, is discarded and a dummy cycle is replaced to get the

proper instruction. This is a 2 cycle instruction. Otherwise proceed with

the next instruction.

Operation Skip if ([m]+1)=0, [m] ← ([m]+1)

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

SIZA [m ] Increment data memory-place result in ACC, skip if zero

Description The contents of the specified data memor y are incremented by one. If the

result is zero, the next instruction is skipped and the result stored in the

accumulator. The data memory remains unchanged. If the result is zero,

the following instruction, fetched during the current instruction execution,

is discarded and a dummy cycle is replaced to get a proper instruction.

This is a 2 cycle instruction. Otherwise proceed with th e next instruction.

Operation Skip if ([m]+1)=0, ACC ← ([m]+1)

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

SNZ [m]. i Skip if bit “i” of the data memory is not zero

Description If bit “i” of the specified data memory is not zero, the following instruction,

fetched during the current instruction execution, is discarded and a

dumm y cycle is repla ced to get a proper instruction. This is a 2 cycle in-

struction. Otherwise proceed with th e next instruction.

Operation Skip if [m].i≠0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

HT827XX

46 4th Jan ’97

SUB A,[m] Subtract data memory from accumulator

Description The specified data memory is subtracted from the contents of the accumu-

lator, leaving the result in the accumulator.

Operation ACC ← ACC+[m]+1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

SUBM A,[m] Subtract data memory from accumulator

Description The specified data memory is subtracted from the contents of the accumu-

lator, leaving the result in the data memory.

Operation [m] ← ACC+[m]+1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

SUB A,x Subtract immediate data from accumulator

Description The immediate data specified by the code is subtracted from the contents

of the accumulator, leaving the result in the accumulator.

Operation ACC ← ACC+x+1

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–– – – √√√√

SWAP [m] Swap nibbles within the data memory

Description The low-order and high-order nibble s of the specified data memory (one of

the data memory) are interchanged.

Operation [m].3~[m].0 ↔ [m].7~[m].4

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

HT827XX

47 4th Jan ’97

SWAPA [m] Swap data memory-place result in accumulator

description The low-order and high-order nibbles of the specified data memory are in-

terchanged, writing the result to the accum ulator. The contents of the data

memory remain unchanged.

Operation ACC.3~ACC.0 ← [m].7~[m].4

ACC.7~A CC.4 ← [m].3~[m].0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

SZ [m] Skip if data memory is zero

Description If the contents of the specified data memory are zero, the following instruc-

tion, fetched during the current instruction execution, is discarded and a

dumm y cycle is repla ced to get a proper instruction. This is a 2 cycle in-

struction. Otherwise proceed with th e next instruction.

Operation Skip if [m]=0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

SZA [m] Move data memory to ACC, skip if zero

Description The contents of the specified data memor y are copied to the accumulator. If

the contents are zero, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get a

proper instruction. This is a 2 cycle instruction. Otherwise proceed with

the next instruction.

Operation Skip if [m]=0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

HT827XX

48 4th Jan ’97

SZ [m]. i Skip if bit “i” of the data memory is zero

Description If bit “i” of the specified data memory is zero, the following instruction,

fetched during the current instruction execution, is discarded and a

dumm y cycle is repla ced to get a proper instruction. This is a 2 cycle in-

struction. Otherwise proceed with th e next instruction.

Operation Skip if [m].i=0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

TABRDC [m] Move ROM code (current page) to TBLH & data memory

Description The low byte of the ROM code (current page) addressed by the table

pointer (TBLP) is moved to the specified data memory and the high byte is

transferred to TBL H directly.

Operation [m] ← ROM code (low byte)

TBLH ← ROM code (high byte)

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

TABRDL [m ] Move ROM code (last page) to TBLH & data memory

Description The low byte of the ROM code (last page) addressed by the table pointer

(TBLP) is moved to the data memory and the high byte is transferred to

TBLH directly.

Operati on [m] ← ROM code (low byte)

TBLH ← ROM code (high byte)

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

––––––––

XOR A,[m] Logical XOR accumulator with data memory

Description Data in the accumulator and indicated data memory perform a bitwise logi-

cal Exclusive_OR operation and the result is stored in the accumulator.

Operation ACC ← ACC “XOR” [ m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

HT827XX

49 4th Jan ’97

XORM A,[m] Logical XOR data memory with accumulator

Description Data in the indicated data memory and accumulator perform a bitwise logi-

cal Exclusive_OR operation. The result is stored in the data memory. The

zero flag is affected.

Operation [m] ← ACC “XOR” [m]

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

XOR A,x Logical XOR immediate data to accumulator

Description Data in the the accumulator and specified data perform a bitwise logical

Exclusive_OR operation. The result is stored in the accumulator. The zero

flag is affected.

Operation ACC ← ACC “XOR” x

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

–––––√––

HT827XX

50 4th Jan ’97