NXP Semiconductors Data Sheet: Technical Data K02P64M100SFA Rev. 4, 08/2016 Kinetis K02 64 KB/128 KB Flash 100 MHz ARM(R) Cortex(R)-M4 Based Microcontroller with FPU Ideal for low-power applications that require processing efficiency and high peripheral integration. These devices share the comprehensive enablement and scalability of the Kinetis family. This product offers: * Run power consumption down to 117.5 A/MHz and static power consumption down to 2.8 A with full state retention and 5.7 s wakeup. Lowest static mode down to 70 nA. * Excellent processing efficiency, 100 MHz ARM(R) Cortex(R)M4-based device with floating-point unit in a tiny form factor MK02FN128VLH10 MK02FN128VLF10 MK02FN128VFM10 MK02FN64VLH10 MK02FN64VLF10 MK02FN64VFM10 64 LQFP (LH) 10 x 10 x 1.4 Pitch 0.5 mm 48 LQFP (LF) 7 x 7 x 1.4 Pitch 0.5 mm 32 QFN (FM) 5 x 5 x 1 Pitch 0.5 mm Performance * 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz Memories and memory interfaces * Up to 128 KB of embedded flash and 16 KB of RAM * Preprogrammed Kinetis flashloader for one-time, insystem factory programming Analog modules * One 16-bit SAR ADC (1.2 MS/s in 12bit mode) * One 12-bit DAC * Two analog comparators (CMP) with 6- bit DAC * Accurate internal voltage reference (not available in 32-pin QFN package) Communication interfaces * One SPI module * Two UART modules * One I2C: Support for up to 1 Mbps operation System peripherals * Flexible low-power modes, multiple wake up sources * 4-channel DMA controller * Independent External and Software Watchdog monitor Timers * One 6-channel general-purpose/PWM timer Clocks * Two 2-channel general-purpose timers with * Crystal oscillator: 32-40 kHz or 3-32 MHz quadrature decoder functionality (FTM2 does not * Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz have external pins on the 32-pin QFN or the 48-pin * Multi-purpose clock generator with FLL LQFP package) * Periodic interrupt timers Security and integrity modules * 16-bit low-power timer * Hardware CRC module * Programmable delay block * 128-bit unique identification (ID) number per chip * Flash access control to protect proprietary software Operating Characteristics * Voltage range (including flash writes): 1.71 to 3.6 V Human-machine interface * Temperature range (ambient): -40 to 105C * Up to 46 general-purpose I/O (GPIO) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Ordering Information Part Number Memory Number of GPIOs Flash (KB) SRAM (KB) MK02FN128VLH10 128 16 46 MK02FN128VLF10 128 16 35 MK02FN128VFM10 128 16 26 MK02FN64VLH10 64 16 46 MK02FN64VLF10 64 16 35 MK02FN64VFM10 64 16 26 Device Revision Number Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN] 0N36M 0000 0000 Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. KINETISKMCUSELGD Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K02P64M100SFARM Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document. Chip Errata The chip mask set Errata provides additional or corrective information for Kinetis_K_0N36M a particular device mask set. Package drawing Package dimensions are provided by the part number: * MK02FN64VFM10 * MK02FN128VFM10 * MK02FN64VLF10 * MK02FN128VLF10 * MK02FN64VLH10 * MK02FN128VLH10 * * * * * * 98ARE10566D 98ARE10566D 98ASH00962A 98ASH00962A 98ASS23234W 98ASS23234W Figure 1 shows the functional modules in the chip. 2 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 ARM (R) CortexTM-M4 Core Debug interfaces Interrupt controller System DMA (4 ch) DSP FPU Program flash (Up to 128 KB) RAM (16 KB) Clocks Frequencylocked loop Low-leakage wakeup Low/high frequency oscillators Internal and external watchdogs Internal reference clocks Security Analog Timers CRC 16-bit SAR ADC x1 Timers x1 (6ch) x2 (2ch) Flash access control Comparator with 6-bit DAC x2 Programmable 12-bit DAC x1 Periodic interrupt timers High performance voltage ref 16-bit low-power timer and Integrity Memories and Memory Interfaces delay block Communication Interfaces 2 I C x1 UART x2 Human-Machine Interface (HMI) Up to 46 GPIOs SPI x1 Figure 1. Functional block diagram Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 3 NXP Semiconductors Table of Contents 1 Ratings.................................................................................... 5 1.1 Thermal handling ratings................................................. 5 1.2 Moisture handling ratings................................................ 5 1.3 ESD handling ratings....................................................... 5 1.4 Voltage and current operating ratings............................. 5 2 General................................................................................... 6 2.1 AC electrical characteristics.............................................6 2.2 Nonswitching electrical specifications..............................6 2.2.1 Voltage and current operating requirements....... 6 2.2.2 LVD and POR operating requirements................7 2.2.3 Voltage and current operating behaviors.............8 2.2.4 Power mode transition operating behaviors........ 9 2.2.5 Power consumption operating behaviors............ 10 2.2.6 EMC radiated emissions operating behaviors..... 16 2.2.7 Designing with radiated emissions in mind..........17 2.2.8 Capacitance attributes.........................................17 2.3 Switching specifications...................................................17 2.3.1 Device clock specifications..................................17 2.3.2 General switching specifications......................... 18 2.4 Thermal specifications..................................................... 18 2.4.1 Thermal operating requirements......................... 18 2.4.2 Thermal attributes................................................19 3 Peripheral operating requirements and behaviors.................. 20 3.1 Core modules.................................................................. 20 3.1.1 SWD electricals .................................................. 20 3.1.2 JTAG electricals.................................................. 21 3.2 System modules.............................................................. 24 3.3 Clock modules................................................................. 24 3.3.1 MCG specifications..............................................24 3.3.2 IRC48M specifications.........................................26 3.3.3 Oscillator electrical specifications........................26 3.4 Memories and memory interfaces................................... 29 3.4.1 Flash electrical specifications.............................. 29 3.5 Security and integrity modules........................................ 30 3.6 Analog............................................................................. 30 4 NXP Semiconductors 4 5 6 7 3.6.1 ADC electrical specifications............................... 30 3.6.2 CMP and 6-bit DAC electrical specifications....... 34 3.6.3 12-bit DAC electrical characteristics....................37 3.6.4 Voltage reference electrical specifications.......... 40 3.7 Timers..............................................................................41 3.8 Communication interfaces............................................... 41 3.8.1 DSPI switching specifications (limited voltage range).................................................................. 42 3.8.2 DSPI switching specifications (full voltage range).................................................................. 43 3.8.3 Inter-Integrated Circuit Interface (I2C) timing...... 45 3.8.4 UART switching specifications............................ 47 Dimensions............................................................................. 47 4.1 Obtaining package dimensions....................................... 47 Pinout...................................................................................... 47 5.1 K02F Signal Multiplexing and Pin Assignments.............. 47 5.2 Recommended connection for unused analog and digital pins........................................................................50 5.3 K02F Pinouts................................................................... 51 Part identification.....................................................................54 6.1 Description.......................................................................54 6.2 Format............................................................................. 54 6.3 Fields............................................................................... 55 6.4 Example...........................................................................55 6.5 48-pin LQFP part marking............................................... 56 6.6 32-pin QFN part marking................................................. 56 Terminology and guidelines.................................................... 56 7.1 Definitions........................................................................ 56 7.2 Examples......................................................................... 57 7.3 Typical-value conditions.................................................. 57 7.4 Relationship between ratings and operating requirements....................................................................58 7.5 Guidelines for ratings and operating requirements..........58 8 Revision History...................................................................... 58 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Ratings 1 Ratings 1.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 1.4 Voltage and current operating ratings Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 5 NXP Semiconductors General Symbol Description Min. Max. Unit VDD Digital supply voltage -0.3 3.8 V IDD Digital supply current -- 145 mA VDIO Digital input voltage -0.3 VDD + 0.3 V VAIO Analog1 -0.3 VDD + 0.3 V -25 25 mA VDD - 0.3 VDD + 0.3 V ID VDDA Maximum current single pin limit (applies to all digital pins) Analog supply voltage 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference 2.2 Nonswitching electrical specifications 2.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V Notes Table continues on the next page... 6 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 General Table 1. Voltage and current operating requirements (continued) Symbol Description Min. Max. Unit Analog supply voltage 1.71 3.6 V VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V 0.7 x VDD -- V 0.75 x VDD -- V -- 0.35 x VDD V -- 0.3 x VDD V 0.06 x VDD -- V VDDA VIH Input high voltage * 2.7 V VDD 3.6 V Notes * 1.7 V VDD 2.7 V VIL Input low voltage * 2.7 V VDD 3.6 V * 1.7 V VDD 2.7 V VHYS Input hysteresis IICIO Analog and I/O pin DC injection current -- single pin * VIN < VSS-0.3V (Negative current injection) IICcont Contiguous pin DC injection current --regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins * Negative current injection 1 -3 -- mA -25 -- mA VODPU Open drain pullup voltage level VDD VDD V VRAM VDD voltage required to retain RAM 1.2 -- V 2 1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold -- high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds -- high range Notes 1 VLVW1H * Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H * Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H * Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H * Level 4 falling (LVWV=11) 2.92 3.00 3.08 V Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 7 NXP Semiconductors General Table 2. VDD supply LVD and POR operating requirements (continued) Symbol Description VHYSH Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) Min. Typ. Max. Unit -- 80 -- mV 1.54 1.60 1.66 V Low-voltage warning thresholds -- low range 1 VLVW1L * Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L * Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L * Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L * Level 4 falling (LVWV=11) 2.04 2.10 2.16 V -- 60 -- mV VHYSL Low-voltage inhibit reset/recover hysteresis -- low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period -- factory trimmed 900 1000 1100 s 1. Rising threshold is the sum of falling threshold and hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 3. Voltage and current operating behaviors Symbol Min. Typ. Max. Unit Notes 2.7 V VDD 3.6 V, IOH = -5 mA VDD - 0.5 -- -- V 1 1.71 V VDD 2.7 V, IOH = -2.5 mA VDD - 0.5 -- -- V 2.7 V VDD 3.6 V, IOH = -20 mA VDD - 0.5 -- -- V 1.71 V VDD 2.7 V, IOH = -10 mA VDD - 0.5 -- -- V IOHT Output high current total for all ports -- -- 100 mA VOL Output low voltage -- Normal drive pad except RESET_B 2.7 V VDD 3.6 V, IOL = 5 mA -- -- 0.5 V 1.71 V VDD 2.7 V, IOL = 2.5 mA -- -- 0.5 V 2.7 V VDD 3.6 V, IOL = 20 mA -- -- 0.5 V 1.71 V VDD 2.7 V, IOL = 10 mA -- -- 0.5 V VOH VOH VOL VOL Description Output high voltage -- Normal drive pad except RESET_B Output high voltage -- High drive pad except RESET_B 1 1 Output low voltage -- High drive pad except RESET_B 1 Output low voltage -- RESET_B Table continues on the next page... 8 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 General Table 3. Voltage and current operating behaviors (continued) Symbol Min. Typ. Max. Unit 2.7 V VDD 3.6 V, IOL = 3 mA -- -- 0.5 V 1.71 V VDD 2.7 V, IOL = 1.5 mA -- -- 0.5 V Output low current total for all ports -- -- 100 mA All pins other than high drive port pins -- 0.002 0.5 A High drive port pins -- 0.004 0.5 A Input leakage current (total all pins) for full temperature range -- -- 1.0 A 2 RPU Internal pullup resistors 20 -- 50 k 3 RPD Internal pulldown resistors 20 -- 50 k 4 IOLT IIN IIN Description Notes Input leakage current (per pin) for full temperature range 1, 2 1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD=3.6V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS 4. Measured at VDD supply voltage = VDD min and Vinput = VDD 2.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSxRUN recovery times in the following table assume this clock configuration: * * * * CPU and system clocks = 72 MHz Bus clock = 36 MHz Flash clock = 24 MHz MCG mode: FEI Table 4. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit Notes -- -- 300 s 1 -- -- 135 s -- -- 135 s -- -- 75 s * VLLS0 RUN * VLLS1 RUN * VLLS2 RUN Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 9 NXP Semiconductors General Table 4. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- -- 75 s -- -- 5.7 s -- -- 5.7 s Notes * VLLS3 RUN * VLPS RUN * STOP RUN 1. Normal boot (FTFA_OPT[LPBOOT]=1) 2.2.5 Power consumption operating behaviors The current parameters in the table below are derived from code executing a while(1) loop from flash, unless otherwise noted. The IDD typical values represent the statistical mean at 25C, and the IDD maximum values for RUN, WAIT, VLPR, and VLPW represent data collected at 125C junction temperature unless otherwise noted. The maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 5. Power consumption operating behaviors Symbol IDDA Description Min. Typ. Max. Unit Notes -- -- See note mA 1 @ 1.8V -- 18.70 19.37 mA 2, 3, 4 @ 3.0V -- 18.71 19.38 mA @ 1.8V -- 18.13 18.80 mA @ 3.0V -- 18.19 18.86 mA @ 1.8V -- 22.2 22.87 mA @ 3.0V -- 22.4 23.07 mA @ 1.8V -- 12.74 13.41 mA @ 3.0V -- 12.82 13.49 mA Analog supply current IDD_HSRUN High Speed Run mode current - all peripheral clocks disabled, CoreMark benchmark code executing from flash IDD_HSRUN High Speed Run mode current - all peripheral clocks disabled, code executing from flash 4 IDD_HSRUN High Speed Run mode current -- all peripheral clocks enabled, code executing from flash IDD_RUN 5 Run mode current in Compute operation -- CoreMark benchmark code executing from flash 2, 3, 6 Table continues on the next page... 10 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 General Table 5. Power consumption operating behaviors (continued) Symbol Description IDD_RUN Run mode current in Compute operation -- code executing from flash IDD_RUN IDD_RUN Min. Typ. Max. Unit Notes @ 1.8V -- 12.10 13.10 mA 6 @ 3.0V -- 12.20 13.37 mA @ 1.8V -- 12.8 13.47 mA @ 3.0V -- 12.9 13.57 mA -- 14.8 15.47 mA * @ 25C -- 14.9 15.57 mA * @ 70C -- 14.9 15.57 mA * @ 85C -- 14.9 15.57 mA * @ 105C -- 15.5 16.20 mA -- 12.1 12.77 mA * @ 25C -- 12.2 12.87 mA * @ 70C -- 12.2 12.87 mA * @ 85C -- 12.2 12.87 mA * @ 105C -- 12.7 13.37 mA Run mode current -- all peripheral clocks disabled, code executing from flash 7 Run mode current -- all peripheral clocks enabled, code executing from flash @ 1.8V 8 @ 3.0V IDD_RUN Run mode current -- Compute operation, code executing from flash @ 1.8V 9 @ 3.0V IDD_WAIT Wait mode high frequency current at 3.0 V -- all peripheral clocks disabled -- 5.5 6.17 mA 7 IDD_WAIT Wait mode reduced frequency current at 3.0 V -- all peripheral clocks disabled -- 3.5 4.17 mA 10 IDD_VLPR Very-low-power run mode current in Compute operation -- CoreMark benchmark code executing from flash @ 1.8V -- 0.58 0.86 mA 2, 11, 3 @ 3.0V -- 0.59 0.87 mA @ 1.8V -- 0.47 0.75 mA @ 3.0V -- 0.47 0.75 mA Very-low-power run mode current at 3.0 V -- all peripheral clocks disabled -- 0.62 0.90 mA IDD_VLPR IDD_VLPR Very-low-power run mode current in Compute operation, code executing from flash 11 12 Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 11 NXP Semiconductors General Table 5. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks enabled -- 0.76 1.04 mA 13 IDD_VLPW Very-low-power wait mode current at 3.0 V -- all peripheral clocks disabled -- 0.28 0.56 mA 14 IDD_STOP Stop mode current at 3.0 V @ -40C to 25C -- 0.26 0.33 mA @ 70C -- 0.30 0.47 mA @ 85C -- 0.35 0.52 mA @ 105C -- 0.43 0.60 mA IDD_VLPS Very-low-power stop mode current at 3.0 V @ -40C to 25C -- 2.80 8.30 A @ 70C -- 13.30 29.90 A @ 85C -- 26.90 46.45 A @ 105C -- 56.80 67.05 A @ -40C to 25C -- 1.3 1.71 A @ 70C -- 3.8 5.35 A @ 85C -- 7.6 8.50 A @ 105C -- 15.1 19.05 A @ -40C to 25C -- 1.3 1.55 A @ 70C -- 3.1 4.05 A @ 85C -- 7.2 8.60 A @ 105C -- 12.0 14.10 A @ -40C to 25C -- 0.63 0.87 A @ 70C -- 1.70 2.35 A @ 85C -- 2.8 3.40 A @ 105C -- 7.6 8.80 A @ -40C to 25C -- 0.35 0.46 A @ 70C -- 1.38 1.94 A @ 85C -- 2.4 2.95 A @ 105C -- 7.3 8.45 A @ -40C to 25C -- 0.07 0.16 A @ 70C -- 1.05 1.78 A @ 85C -- 2.1 2.80 A IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled Table continues on the next page... 12 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 General Table 5. Power consumption operating behaviors (continued) Symbol Description @ 105C Min. Typ. Max. Unit -- 6.9 8.25 A Notes 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. Cache on and prefetch on, low compiler optimization 3. CoreMark benchmark compiled using IAR 7.2 with optimization level low 4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All peripheral clocks disabled. 5. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 6. 72 MHz core and system clock, 36 MHz bus clock and 24 MHz flash clock. MCG configured for FEE mode. All peripheral clocks disabled. Compute operation. 7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEI mode. All peripheral clocks disabled. 8. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute operation. 10. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. 11. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. Compute operation. Code executing from flash. 12. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 13. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled, but peripherals are not in active operation. Code executing from flash. 14. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Table 6. Low power mode peripheral adders--typical value Symbol Description Temperature (C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 A IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 A IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 uA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. VLLS1 440 490 540 560 570 580 nA VLLS3 440 490 540 560 570 580 LLS 490 490 540 560 570 680 Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 13 NXP Semiconductors General Table 6. Low power mode peripheral adders--typical value (continued) Symbol Description Temperature (C) Unit -40 25 50 70 85 105 VLPS 510 560 560 560 610 680 STOP 510 560 560 560 610 680 48 Mhz internal reference clock 350 350 350 350 350 350 A ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 A IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. 66 66 66 66 66 66 A 214 237 246 254 260 268 I48MIRC MCGIRCLK (4 MHz internal reference clock) >OSCERCLK (4 MHz external crystal) IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 45 45 45 45 45 45 A IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 42 42 42 42 42 42 A 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: * MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at frequencies between 50 MHz and 100MHz. * No GPIOs toggled * Code execution from flash with cache enabled * For the ALLOFF curve, all peripheral clocks are disabled except FTFA 14 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 General Figure 3. Run mode supply current vs. core frequency Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 15 NXP Semiconductors General Figure 4. VLPR mode supply current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 64 LQFP package Parame Conditions ter VEME Clocks Frequency range Level (Typ.) Unit Notes Device configuration, test FSYS = 100 MHz 150 kHz-50 MHz conditions and EM 50 MHz-150 MHz FBUS = 50 MHz testing per standard IEC External crystal = 10 MHz 150 MHz-500 MHz 61967-2. 500 MHz-1000 MHz Supply voltage: VDD = 11 dBuV 1, 2, 3 3.3 V N IEC level 12 11 8 4 Temp = 25C 1. Measurements were made per IEC 61967-2 while the device was running typical application code. 2. Measurements were performed on a similar 64LQFP device. 3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 16 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 General 4. IEC Level Maximums: N 12dBmV, M 18dBmV, L 24dBmV, K 30dBmV, I 36dBmV . 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: * Go to nxp.com * Perform a keyword search for "EMC design." 2.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins -- 7 pF CIN_D Input capacitance: digital pins -- 7 pF 2.3 Switching specifications 2.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit Notes High Speed run mode fSYS System and core clock -- 100 MHz fBUS Bus clock -- 50 MHz Normal run mode (and High Speed run mode unless otherwise specified above) fSYS System and core clock -- 72 MHz fBUS Bus clock -- 50 MHz fFLASH Flash clock -- 25 MHz fLPTMR LPTMR clock -- 25 MHz VLPR mode1 fSYS System and core clock -- 4 MHz fBUS Bus clock -- 4 MHz fFLASH Flash clock -- 1 MHz fERCLK External reference clock -- 16 MHz LPTMR clock -- 25 MHz fLPTMR_pin Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 17 NXP Semiconductors General Table 9. Device clock specifications (continued) Symbol Description fLPTMR_ERCLK LPTMR external reference clock Min. Max. Unit -- 16 MHz Notes 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, and timers. Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1, 2 External RESET and NMI pin interrupt pulse width -- Asynchronous path 100 -- ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, passive filter disabled) -- Asynchronous path 50 -- ns 4 Port rise and fall time * Slew disabled * 1.71 VDD 2.7V 5 -- -- * 2.7 VDD 3.6V * Slew enabled * 1.71 VDD 2.7V * 2.7 VDD 3.6V 10 ns 5 ns 30 ns 16 ns -- -- 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater of synchronous and asynchronous timing must be met. 3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be recognized. 4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized. 5. 25 pF load 2.4 Thermal specifications 18 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 General 2.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 C TA Ambient temperature -40 105 C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + RJA x chip power dissipation. 2.4.2 Thermal attributes Board type Symbol Descriptio n 64 LQFP 48 LQFP 32 QFN Unit Notes Single-layer (1s) RJA Thermal resistance, junction to ambient (natural convection) 66 79 97 C/W 1 Four-layer (2s2p) RJA Thermal resistance, junction to ambient (natural convection) 48 55 33 C/W 1 Single-layer (1s) RJMA Thermal 54 resistance, junction to ambient (200 ft./min. air speed) 67 81 C/W 1 Four-layer (2s2p) RJMA Thermal 41 resistance, junction to ambient (200 ft./min. air speed) 49 28 C/W 1 -- RJB Thermal resistance, junction to board 30 33 13 C/W 2 -- RJC Thermal resistance, junction to case 17 23 2.0 C/W 3 -- JT Thermal 3 characterizati 5 6 C/W 4 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 19 NXP Semiconductors Peripheral operating requirements and behaviors Board type Symbol Descriptio n 64 LQFP 48 LQFP 32 QFN Unit Notes on parameter, junction to package top outside center (natural convection) 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 SWD electricals Table 12. SWD full voltage range electricals Symbol S1 Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 33 MHz 1/S1 -- ns 15 -- ns SWD_CLK frequency of operation * Serial wire debug S2 SWD_CLK cycle period S3 SWD_CLK clock pulse width * Serial wire debug S4 SWD_CLK rise and fall times -- 3 ns S9 SWD_DIO input data setup time to SWD_CLK rise 8 -- ns S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 -- ns S11 SWD_CLK high to SWD_DIO data valid -- 25 ns S12 SWD_CLK high to SWD_DIO high-Z 5 -- ns 20 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors S2 S3 S3 SWD_CLK (input) S4 S4 Figure 5. Serial wire clock input timing SWD_CLK S9 SWD_DIO S10 Input data valid S11 SWD_DIO Output data valid S12 SWD_DIO S11 SWD_DIO Output data valid Figure 6. Serial wire data timing 3.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz * Boundary Scan 0 10 * JTAG and CJTAG 0 20 1/J1 -- ns 50 -- ns J2 TCLK cycle period J3 TCLK clock pulse width Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 21 NXP Semiconductors Peripheral operating requirements and behaviors Table 13. JTAG limited voltage range electricals (continued) Symbol Description * Boundary Scan Min. Max. Unit 25 -- ns * JTAG and CJTAG J4 TCLK rise and fall times -- 3 ns J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 1 -- ns J7 TCLK low to boundary scan output data valid -- 25 ns J8 TCLK low to boundary scan output high-Z -- 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1 -- ns J11 TCLK low to TDO data valid -- 19 ns J12 TCLK low to TDO high-Z -- 19 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns Table 14. JTAG full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V TCLK frequency of operation MHz * Boundary Scan 0 10 * JTAG and CJTAG 0 15 1/J1 -- ns * Boundary Scan 50 -- ns * JTAG and CJTAG 33 -- ns J4 TCLK rise and fall times -- 3 ns J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 1.4 -- ns J7 TCLK low to boundary scan output data valid -- 27 ns J8 TCLK low to boundary scan output high-Z -- 27 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1.4 -- ns J11 TCLK low to TDO data valid -- 26.2 ns J12 TCLK low to TDO high-Z -- 26.2 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns J2 TCLK cycle period J3 TCLK clock pulse width 22 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors J2 J3 J3 TCLK (input) J4 J4 Figure 7. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 8. Boundary scan (JTAG) timing Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 23 NXP Semiconductors Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 9. Test Access Port timing TCLK J14 J13 TRST Figure 10. TRST timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 24 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors 3.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 C -- 32.768 -- kHz fints_t Total deviation of internal reference frequency (slow clock) over voltage and temperature -- +0.5/-0.7 2 % 31.25 -- 39.0625 kHz -- 0.3 0.6 %fdco 1 fints_t Internal reference frequency (slow clock) -- user trimmed fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature -- +0.5/-0.7 2 %fdco 1, 2 fdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70C -- 0.3 1.5 %fdco 1 Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25C -- 4 -- MHz Frequency deviation of internal reference clock (fast clock) over temperature and voltage -- factory trimmed at nominal VDD and 25 C -- +1/-2 5 %fintf_ft Internal reference frequency (fast clock) -- user trimmed at nominal VDD and 25 C 3 -- 5 MHz fintf_ft fintf_ft fintf_t floc_low Loss of external clock minimum frequency -- RANGE = 00 (3/5) x fints_t -- -- kHz floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 (16/5) x fints_t -- -- kHz 31.25 -- 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz -- 23.99 -- MHz -- 47.97 -- MHz -- 71.99 -- MHz FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 3, 4 640 x ffll_ref Mid range (DRS=01) 1280 x ffll_ref Mid-high range (DRS=10) 1920 x ffll_ref High range (DRS=11) 2560 x ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 5, 6 732 x ffll_ref Mid range (DRS=01) 1464 x ffll_ref Mid-high range (DRS=10) Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 25 NXP Semiconductors Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit -- 95.98 -- MHz Notes 2197 x ffll_ref High range (DRS=11) 2929 x ffll_ref Jcyc_fll FLL period jitter * fVCO = 48 MHz * fVCO = 98 MHz tfll_acquire -- -- 180 -- ps -- -- 150 FLL target frequency acquisition time -- -- 1 ms 7 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. 2.0 V <= VDD <= 3.6 V. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 IRC48M specifications Table 16. IRC48M specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDD48M Supply current -- 400 500 A firc48m Internal reference frequency -- 48 -- MHz firc48m_hv Total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over full temperature -- 0.5 1.5 %firc48m firc48m_hv Total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over -40C to 85C -- 0.5 1.0 %firc48m firc48m_lv Total deviation of IRC48M frequency at low voltage (VDD=1.71V-1.89V) over full temperature -- 0.5 2.0 %firc48m Jcyc_irc48m Period Jitter (RMS) -- 35 150 ps Startup time -- 2 3 s tirc48mst Notes 1 1. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings: * MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or * SIM_SOPT2[PLLFLLSEL]=11 26 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors 3.3.3 Oscillator electrical specifications 3.3.3.1 Oscillator DC electrical specifications Table 17. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC IDDOSC Supply current -- low-power mode (HGO=0) Notes 1 * 32 kHz -- 500 -- nA * 4 MHz -- 200 -- A * 8 MHz (RANGE=01) -- 300 -- A * 16 MHz -- 950 -- A * 24 MHz -- 1.2 -- mA * 32 MHz -- 1.5 -- mA Supply current -- high-gain mode (HGO=1) 1 * 32 kHz -- 25 -- A * 4 MHz -- 400 -- A * 8 MHz (RANGE=01) -- 500 -- A * 16 MHz -- 2.5 -- mA * 24 MHz -- 3 -- mA * 32 MHz -- 4 -- mA Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Feedback resistor -- high-frequency, lowpower mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain mode (HGO=1) -- 1 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power mode (HGO=0) -- -- -- k -- 0 -- k RS 2, 4 Series resistor -- high-frequency, high-gain mode (HGO=1) Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 27 NXP Semiconductors Peripheral operating requirements and behaviors Table 17. Oscillator DC electrical specifications (continued) Symbol 5 Vpp 1. 2. 3. 4. 5. Description Min. Typ. Max. Unit Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) -- VDD -- V Notes VDD=3.3 V, Temperature =25 C See crystal or resonator manufacturer's recommendation Cx and Cy can be provided by using either integrated capacitors or external components. When low-power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other device. 3.3.3.2 Symbol Oscillator frequency specifications Table 18. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency -- lowfrequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency -- highfrequency mode (low range) (MCG_C2[RANGE]=01) 3 -- 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 -- 32 MHz fec_extal Input clock frequency (external clock mode) -- -- 50 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- 750 -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- 250 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) -- 0.6 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) -- 1 -- ms tcst Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL 28 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 3.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 19. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes thvpgm4 Longword Program high-voltage time -- 7.5 18 s -- thversscr Sector Erase high-voltage time -- 13 113 ms 1 thversall Erase All high-voltage time -- 104 904 ms 1 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications -- commands Table 20. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec2k tpgmchk Read 1s Section execution time (flash sector) -- -- 60 s 1 Program Check execution time -- -- 45 s 1 trdrsrc Read Resource execution time -- -- 30 s 1 tpgm4 Program Longword execution time -- 65 145 s -- tersscr Erase Flash Sector execution time -- 14 114 ms 2 trd1all Read 1s All Blocks execution time -- -- 0.9 ms 1 trdonce Read Once execution time -- -- 30 s 1 Program Once execution time -- 100 -- s -- tersall Erase All Blocks execution time -- 140 1150 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 tpgmonce 1. Assumes 25 MHz flash clock frequency. Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 29 NXP Semiconductors Peripheral operating requirements and behaviors 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 21. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 3.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation -- 2.5 6.0 mA Average current adder during high voltage flash erase operation -- 1.5 4.0 mA Reliability specifications Table 22. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 -- years -- tnvmretp1k Data retention after up to 1 K cycles 20 100 -- years -- nnvmcycp Cycling endurance 10 K 50 K -- cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 C Tj 125 C. 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins ADCx_DPx, ADCx_DMx. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 30 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors 3.6.1.1 16-bit ADC operating conditions Table 23. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 -- 3.6 V VDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2 VSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage * 16-bit differential mode VREFL -- 31/32 * VREFH V * All other modes VREFL -- * 16-bit mode -- 8 10 * 8-bit / 10-bit / 12-bit modes -- 4 5 -- 2 5 CADIN RADIN RAS Input capacitance Input series resistance Analog source resistance (external) Notes VREFH pF k 13-bit / 12-bit modes 3 fADCK < 4 MHz -- -- 5 k fADCK ADC conversion 13-bit mode clock frequency 1.0 -- 24.0 MHz 4 fADCK ADC conversion 16-bit mode clock frequency 2.0 -- 12.0 MHz 4 Crate ADC conversion 13-bit modes rate No ADC hardware averaging 5 20 -- 1200 Ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion 16-bit mode rate No ADC hardware averaging 5 37 -- 461 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 31 NXP Semiconductors Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 11. ADC input impedance equivalency diagram 3.6.1.2 16-bit ADC electrical characteristics Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes 0.215 -- 1.7 mA 3 * ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz * ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK * ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz * ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 IDDA_ADC Supply current ADC asynchronous clock source fADACK Sample Time TUE DNL INL See Reference Manual chapter for sample times Total unadjusted error * 12-bit modes -- 4 6.8 * <12-bit modes -- 1.4 2.1 Differential nonlinearity * 12-bit modes -- 0.7 -1.1 to +1.9 * <12-bit modes -- 0.2 * 12-bit modes -- 1.0 Integral non-linearity -0.3 to 0.5 -2.7 to +1.9 Table continues on the next page... 32 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1 Min. Typ.2 Max. -- 0.5 -0.7 to +0.5 * 12-bit modes -- -4 -5.4 * <12-bit modes -- -1.4 -1.8 * 16-bit modes -- -1 to 0 -- * 13-bit modes -- -- 0.5 * <12-bit modes EFS EQ ENOB Full-scale error Quantization error Effective number of bits Unit Notes LSB4 VADIN = VDDA5 LSB4 16-bit differential mode 6 * Avg = 32 12.8 14.5 * Avg = 4 11.9 13.8 -- -- bits bits 16-bit single-ended mode * Avg = 32 * Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode * Avg = 32 12.2 13.9 11.4 13.1 -- -- 6.02 x ENOB + 1.76 bits bits dB dB -- -94 7 -- dB 16-bit single-ended mode * Avg = 32 SFDR Spurious free dynamic range -- -85 82 95 16-bit differential mode * Avg = 32 16-bit single-ended mode 78 -- -- dB -- dB 7 90 * Avg = 32 EIL Input leakage error IIn x RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device VTEMP25 Temp sensor voltage 25 C 1.55 1.62 1.69 mV/C 8 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 33 NXP Semiconductors Peripheral operating requirements and behaviors 4. 5. 6. 7. 8. 1 LSB = (VREFH - VREFL)/2N ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 ENOB 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.30 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 12. Typical ENOB vs. ADC_CLK for 16-bit differential mode Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.00 13.75 13.50 13.25 13.00 ENOB 12.75 12.50 12.25 12.00 11.75 11.50 11.25 11.00 Averaging of 4 samples Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 13. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 34 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors 3.6.2 CMP and 6-bit DAC electrical specifications Table 25. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 200 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- -- 20 A VAIN Analog input voltage VSS - 0.3 -- VDD V VAIO Analog input offset voltage -- -- 20 mV * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VH Analog comparator hysteresis1 VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns -- -- 40 s -- 7 -- A Analog comparator initialization IDAC6b delay2 6-bit DAC current adder (enabled) INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 35 NXP Semiconductors Peripheral operating requirements and behaviors 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 36 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.6.3 12-bit DAC electrical characteristics 3.6.3.1 Symbol 12-bit DAC operating requirements Table 26. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.6 V VDACR Reference voltage 1.13 3.6 V 1 2 CL Output load capacitance -- 100 pF IL Output load current -- 1 mA Notes 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 37 NXP Semiconductors Peripheral operating requirements and behaviors 3.6.3.2 Symbol 12-bit DAC operating behaviors Table 27. 12-bit DAC operating behaviors Description IDDA_DACL Supply current -- low-power mode Min. Typ. Max. Unit -- -- 330 A -- -- 1200 A Notes P IDDA_DACH Supply current -- high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) -- low-power mode -- 100 200 s 1 tDACHP Full-scale settling time (0x080 to 0xF7F) -- high-power mode -- 15 30 s 1 tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and high-speed mode -- 0.7 1 s 1 Vdacoutl DAC output voltage range low -- highspeed mode, no load, DAC set to 0x000 -- -- 100 mV Vdacouth DAC output voltage range high -- highspeed mode, no load, DAC set to 0xFFF VDACR -100 -- VDACR mV INL Integral non-linearity error -- high speed mode -- -- 8 LSB 2 DNL Differential non-linearity error -- VDACR > 2 V -- -- 1 LSB 3 DNL Differential non-linearity error -- VDACR = VREF_OUT -- -- 1 LSB 4 -- 0.4 0.8 %FSR 5 Gain error -- 0.1 0.6 %FSR 5 Power supply rejection ratio, VDDA 2.4 V 60 -- 90 dB TCO Temperature coefficient offset voltage -- 3.7 -- V/C TGE Temperature coefficient gain error -- 0.000421 -- %FSR/C Rop Output resistance (load = 3 k) -- -- 250 SR Slew rate -80h F7Fh 80h VOFFSET Offset error EG PSRR BW 6 V/s * High power (SPHP) 1.2 1.7 -- * Low power (SPLP) 0.05 0.12 -- 3dB bandwidth kHz * High power (SPHP) 550 -- -- * Low power (SPLP) 40 -- -- 1. 2. 3. 4. 5. 6. Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR - 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device 38 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 NXP Semiconductors Peripheral operating requirements and behaviors 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 16. Typical INL error vs. digital code Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 39 NXP Semiconductors Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 25 -40 55 85 105 125 Temperature C Figure 17. Offset at half scale vs. temperature 3.6.4 Voltage reference electrical specifications Table 28. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. 40 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors Table 29. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1920 1.1950 1.1980 V 1 Vout Voltage reference output with user trim at nominal VDDA and temperature=25C 1.1945 1.1950 1.1955 V 1 Vstep Voltage reference trim step -- 0.5 -- mV 1 Vtdrift Temperature drift (Vmax -Vmin across the full temperature range) -- -- 15 mV 1 Ibg Bandgap only current -- -- 80 A Ilp Low-power buffer current -- -- 360 uA 1 Ihp High-power buffer current -- -- 1 mA 1 V 1, 2 VLOAD Load regulation * current = 1.0 mA Tstup Buffer startup time Tchop_osc_st Internal bandgap start-up delay with chop oscillator enabled up Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) -- 200 -- -- -- 100 s -- -- 35 ms -- 2 -- mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 30. VREF limited-range operating requirements Symbol Description Min. Max. Unit TA Temperature 0 70 C Notes Table 31. VREF limited-range operating behaviors Symbol Vtdrift Description Temperature drift (Vmax -Vmin across the limited temperature range) Min. Max. Unit -- 10 mV Notes 3.7 Timers See General switching specifications. 3.8 Communication interfaces Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 41 NXP Semiconductors Peripheral operating requirements and behaviors 3.8.1 DSPI switching specifications (limited voltage range) The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 32. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- 25 MHz 2 x tBUS -- ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 2 -- ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 2 -- ns 2 DS5 DSPI_SCK to DSPI_SOUT valid -- 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid -2 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 16.2 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK (CPOL=0) DSPI_SIN DSPI_SOUT DS7 DS1 DS2 DS4 DS8 First data First data Data Last data DS5 DS6 Data Last data Figure 18. DSPI classic SPI timing -- master mode 42 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors Table 33. Slave mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- 12.5 MHz 4 x tBUS -- ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 21.4 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 2.6 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 17 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 17 ns (tSCK/2) - 2 (tSCK/2) + 2 Notes 1 ns 1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus clock is 60 MHz, the SPI clock must not be greater than 10 MHz. DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DSPI_SOUT First data DS13 DSPI_SIN DS12 DS16 DS11 Data Last data DS14 First data Data Last data Figure 19. DSPI classic SPI timing -- slave mode Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 43 NXP Semiconductors Peripheral operating requirements and behaviors 3.8.2 DSPI switching specifications (full voltage range) The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 34. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit Notes 1.71 3.6 V 1 -- 12.5 MHz 4 x tBUS -- ns DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 4 -- ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 4 -- ns 3 DS5 DSPI_SCK to DSPI_SOUT valid -- 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 24.6 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK (CPOL=0) DSPI_SIN DSPI_SOUT DS7 DS1 DS2 DS4 DS8 First data First data Data Last data DS5 DS6 Data Last data Figure 20. DSPI classic SPI timing -- master mode 44 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Peripheral operating requirements and behaviors Table 35. Slave mode DSPI timing (full voltage range) Num Description Min. Max. Unit 1.71 3.6 V -- 6.25 MHz 8 x tBUS -- ns Operating voltage Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS11 DSPI_SCK to DSPI_SOUT valid -- 29.5 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 3.2 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 25 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 25 ns DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 21. DSPI classic SPI timing -- slave mode 3.8.3 Inter-Integrated Circuit Interface (I2C) timing Table 36. I 2C timing Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum Unit SCL Clock Frequency fSCL 0 100 0 4001 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 -- 0.6 -- s LOW period of the SCL clock tLOW 4.7 -- 1.25 -- s HIGH period of the SCL clock tHIGH 4 -- 0.6 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- 0.6 -- s Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 45 NXP Semiconductors Peripheral operating requirements and behaviors Table 36. I 2C timing (continued) Characteristic Data hold time for I2C Symbol bus devices Data set-up time Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum tHD; DAT 02 3.453 04 0.92 s tSU; DAT 2505 -- 1003, 6 Rise time of SDA and SCL signals tr -- 1000 -- ns 7 300 ns 6 20 +0.1Cb Fall time of SDA and SCL signals tf -- 300 20 +0.1Cb 300 ns Set-up time for STOP condition tSU; STO 4 -- 0.6 -- s Bus free time between STOP and START condition tBUF 4.7 -- 1.3 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the High drive pins across the full voltage range and when using the Normal drive pins and VDD 2.7 V. 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; 2 DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released. 7. Cb = total capacitance of the one bus line in pF. Table 37. I 2C 1 Mbps timing Characteristic Symbol Minimum Maximum Unit MHz SCL Clock Frequency fSCL 0 11 Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 0.26 -- s LOW period of the SCL clock tLOW 0.5 -- s HIGH period of the SCL clock tHIGH 0.26 -- s Set-up time for a repeated START condition tSU; STA 0.26 -- s Data hold time for I2C bus devices tHD; DAT 0 -- s Data set-up time tSU; DAT 50 Rise time of SDA and SCL signals tr -- ns ,2 120 ns 2 120 ns -- s 20 +0.1Cb Fall time of SDA and SCL signals tf 20 +0.1Cb Set-up time for STOP condition tSU; STO 0.26 Bus free time between STOP and START condition tBUF 0.5 -- s Pulse width of spikes that must be suppressed by the input filter tSP 0 50 ns 1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across the full voltage range. 2. Cb = total capacitance of the one bus line in pF. 46 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Dimensions SDA tf tLOW tSU; DAT tr tf tHD; STA tSP tr tBUF SCL HD; STA S tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 22. Timing definition for devices on the I2C bus 3.8.4 UART switching specifications See General switching specifications. 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ARE10566D 48-pin LQFP 98ASH00962A 64-pin LQFP 98ASS23234W 5 Pinout 5.1 K02F Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 47 NXP Semiconductors Pinout 64 48 32 LQFP LQFP QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 1 -- -- PTE0/ CLKOUT32K DISABLED PTE0/ CLKOUT32K UART1_TX 2 -- -- PTE1/ LLWU_P0 DISABLED PTE1/ LLWU_P0 UART1_RX 3 1 1 VDD VDD VDD 4 2 2 VSS VSS VSS 5 3 3 PTE16 ADC0_SE4a/ ADC0_DP1 ADC0_SE4a/ ADC0_DP1 PTE16 SPI0_PCS0 UART1_TX FTM_CLKIN0 FTM0_FLT3 6 4 4 PTE17 ADC0_SE5a/ ADC0_DM1 ADC0_SE5a/ ADC0_DM1 PTE17 SPI0_SCK UART1_RX FTM_CLKIN1 LPTMR0_ ALT3 7 5 5 PTE18 ADC0_SE6a/ ADC0_DP2 ADC0_SE6a/ ADC0_DP2 PTE18 SPI0_SOUT UART1_CTS_ I2C0_SDA b 8 6 6 PTE19 ADC0_SE7a/ ADC0_DM2 ADC0_SE7a/ ADC0_DM2 PTE19 SPI0_SIN UART1_RTS_ I2C0_SCL b 9 7 -- ADC0_DP0 ADC0_DP0 ADC0_DP0 10 8 -- ADC0_DM0 ADC0_DM0 ADC0_DM0 11 -- -- ADC0_DP3 ADC0_DP3 ADC0_DP3 12 -- -- ADC0_DM3 ADC0_DM3 ADC0_DM3 13 9 7 VDDA VDDA VDDA 14 10 7 VREFH VREFH VREFH 15 11 8 VREFL VREFL VREFL 16 12 8 VSSA VSSA VSSA 17 13 -- VREF_OUT/ CMP1_IN5/ CMP0_IN5 VREF_OUT/ CMP1_IN5/ CMP0_IN5 VREF_OUT/ CMP1_IN5/ CMP0_IN5 18 14 9 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 19 -- -- CMP0_IN4 CMP0_IN4 CMP0_IN4 20 15 10 PTE24 ADC0_SE17 ADC0_SE17 PTE24 I2C0_SCL EWM_OUT_b 21 16 11 PTE25 ADC0_SE18 ADC0_SE18 PTE25 I2C0_SDA EWM_IN 22 17 12 PTA0 JTAG_TCLK/ SWD_CLK PTA0 UART0_CTS_ FTM0_CH5 b JTAG_TCLK/ SWD_CLK 23 18 13 PTA1 JTAG_TDI PTA1 UART0_RX JTAG_TDI 24 19 14 PTA2 JTAG_TDO/ TRACE_SWO PTA2 UART0_TX JTAG_TDO/ TRACE_SWO 25 20 15 PTA3 JTAG_TMS/ SWD_DIO PTA3 UART0_RTS_ FTM0_CH0 b JTAG_TMS/ SWD_DIO 26 21 16 PTA4/ LLWU_P3 NMI_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b 27 -- -- PTA5 DISABLED PTA5 FTM0_CH2 JTAG_TRST_ b 28 -- -- PTA12 DISABLED PTA12 FTM1_CH0 FTM1_QD_ PHA 48 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Pinout 64 48 32 LQFP LQFP QFN Pin Name Default ALT0 29 -- -- PTA13/ LLWU_P4 DISABLED 30 22 -- VDD VDD VDD 31 23 -- VSS VSS VSS 32 24 17 PTA18 EXTAL0 33 25 18 PTA19 34 26 19 35 27 20 36 28 37 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 PTA13/ LLWU_P4 FTM1_CH1 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 RESET_b RESET_b RESET_b PTB0/ LLWU_P5 ADC0_SE8 ADC0_SE8 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA 21 PTB1 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_ PHB 29 -- PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL UART0_RTS_ b FTM0_FLT3 38 30 -- PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA UART0_CTS_ b FTM0_FLT0 39 31 -- PTB16 DISABLED PTB16 UART0_RX FTM_CLKIN0 EWM_IN 40 32 -- PTB17 DISABLED PTB17 UART0_TX FTM_CLKIN1 EWM_OUT_b 41 -- -- PTB18 DISABLED PTB18 FTM2_CH0 FTM2_QD_ PHA 42 -- -- PTB19 DISABLED PTB19 FTM2_CH1 FTM2_QD_ PHB 43 33 -- PTC0 ADC0_SE14 ADC0_SE14 PTC0 SPI0_PCS4 PDB0_ EXTRG 44 34 22 PTC1/ LLWU_P6 ADC0_SE15 ADC0_SE15 PTC1/ LLWU_P6 SPI0_PCS3 UART1_RTS_ FTM0_CH0 b 45 35 23 PTC2 ADC0_SE4b/ CMP1_IN0 ADC0_SE4b/ CMP1_IN0 PTC2 SPI0_PCS2 UART1_CTS_ FTM0_CH1 b 46 36 24 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 47 -- -- VSS VSS VSS 48 -- -- VDD VDD VDD 49 37 25 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 50 38 26 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 51 39 27 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_ EXTRG 52 40 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN 53 -- -- PTC8 CMP0_IN2 CMP0_IN2 PTC8 54 -- -- PTC9 CMP0_IN3 CMP0_IN3 PTC9 55 -- -- PTC10 DISABLED PTC10 56 -- -- PTC11/ LLWU_P11 DISABLED PTC11/ LLWU_P11 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 ALT7 FTM1_QD_ PHB LPTMR0_ ALT1 CLKOUT CMP1_OUT CMP0_OUT FTM0_CH2 FTM2_FLT0 49 NXP Semiconductors Pinout 64 48 32 LQFP LQFP QFN Pin Name Default 57 41 -- PTD0/ LLWU_P12 DISABLED 58 42 -- PTD1 ADC0_SE5b 59 43 -- PTD2/ LLWU_P13 60 44 -- 61 45 62 ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 PTD0/ LLWU_P12 SPI0_PCS0 PTD1 SPI0_SCK DISABLED PTD2/ LLWU_P13 SPI0_SOUT I2C0_SCL PTD3 DISABLED PTD3 SPI0_SIN I2C0_SDA 29 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_ FTM0_CH4 b EWM_IN 46 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 b EWM_OUT_b 63 47 31 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH0 FTM0_FLT0 64 48 32 PTD7 DISABLED UART0_TX FTM0_CH1 FTM0_FLT1 ADC0_SE5b PTD7 5.2 Recommended connection for unused analog and digital pins The following table shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application. Table 38. Recommended connection for unused analog interfaces Pin Type Short recommendation Detailed recommendation Analog/non GPIO PGAx/ADCx Float Analog input - Float Analog/non GPIO ADCx/CMPx Float Analog input - Float Analog/non GPIO VREF_OUT Float Analog output - Float Analog/non GPIO DACx_OUT Float Analog output - Float Analog/non GPIO RTC_WAKEUP_B Float Analog output - Float Analog/non GPIO XTAL32 Float Analog output - Float Analog/non GPIO EXTAL32 Float Analog input - Float GPIO/Analog PTA18/EXTAL0 Float Analog input - Float GPIO/Analog PTA19/XTAL0 Float Analog output - Float GPIO/Analog PTx/ADCx Float Float (default is analog input) GPIO/Analog PTx/CMPx Float Float (default is analog input) GPIO/Digital PTA0/JTAG_TCLK Float Float (default is JTAG with pulldown) GPIO/Digital PTA1/JTAG_TDI Float Float (default is JTAG with pullup) GPIO/Digital PTA2/JTAG_TDO Float Float (default is JTAG with pullup) GPIO/Digital PTA3/JTAG_TMS Float Float (default is JTAG with pullup) Table continues on the next page... 50 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Pinout Table 38. Recommended connection for unused analog interfaces (continued) Pin Type Short recommendation Detailed recommendation GPIO/Digital PTA4/NMI_b 10k pullup or disable and float Pull high or disable in PCR & FOPT and float GPIO/Digital PTx Float Float (default is disabled) VDDA VDDA Always connect to VDD potential Always connect to VDD potential VREFH VREFH Always connect to VDD potential Always connect to VDD potential VREFL VREFL Always connect to VSS potential Always connect to VSS potential VSSA VSSA Always connect to VSS potential Always connect to VSS potential 5.3 K02F Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 51 NXP Semiconductors PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ADC0_DP0 9 40 PTB17 ADC0_DM0 10 39 PTB16 ADC0_DP3 11 38 PTB3 ADC0_DM3 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 32 PTB18 PTA18 41 31 8 VSS PTE19 30 PTB19 VDD 42 29 7 PTA13/LLWU_P4 PTE18 28 PTC0 PTA12 43 27 6 PTA5 PTE17 26 PTC1/LLWU_P6 PTA4/LLWU_P3 44 25 5 PTA3 PTE16 24 PTC2 PTA2 45 23 4 PTA1 VSS 22 PTC3/LLWU_P7 PTA0 46 21 3 PTE25 VDD 20 VSS PTE24 47 19 2 CMP0_IN4 PTE1/LLWU_P0 18 VDD DAC0_OUT/CMP1_IN3/ADC0_SE23 48 17 1 VREF_OUT/CMP1_IN5/CMP0_IN5 PTE0/CLKOUT32K Figure 23. K02F 64 LQFP pinout diagram (top view) 52 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 48 47 46 45 44 43 42 41 40 39 38 37 Pinout ADC0_DP0 7 30 PTB3 ADC0_DM0 8 29 PTB2 VDDA 9 28 PTB1 VREFH 10 27 PTB0/LLWU_P5 VREFL 11 26 RESET_b VSSA 12 25 PTA19 24 PTB16 PTA18 31 23 6 VSS PTE19 22 PTB17 VDD 32 21 5 PTA4/LLWU_P3 PTE18 20 PTC0 PTA3 33 19 4 PTA2 PTE17 18 PTC1/LLWU_P6 PTA1 34 17 3 PTA0 PTE16 16 PTC2 PTE25 35 15 2 PTE24 VSS 14 PTC3/LLWU_P7 DAC0_OUT/CMP1_IN3/ADC0_SE23 36 13 1 VREF_OUT/CMP1_IN5/CMP0_IN5 VDD Figure 24. K02F 48 LQFP pinout diagram Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 53 NXP Semiconductors PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 32 31 30 29 28 27 26 25 Part identification 4 21 PTB1 PTE18 5 20 PTB0/LLWU_P5 PTE19 6 19 RESET_b VDDA VREFH 7 18 PTA19 VREFL VSSA 8 17 PTA18 PTA4/LLWU_P3 PTE24 DAC0_OUT/CMP1_IN3/ADC0_SE23 16 PTE17 15 PTC1/LLWU_P6 PTA3 22 14 3 PTA2 PTE16 13 PTC2 PTA1 23 12 2 PTA0 VSS 11 PTC3/LLWU_P7 PTE25 24 10 1 9 VDD Figure 25. K02F 32 QFN pinout diagram 6 Part identification 6.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 54 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Part identification 6.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 6.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status * M = Fully qualified, general market flow, full reel * P = Prequalification * K = Fully qualified, general market flow, 100 piece reel K## Kinetis family * K02 A Key attribute * D = Cortex-M4 w/ DSP * F = Cortex-M4 w/ DSP and FPU M Flash memory type * N = Program flash only * X = Program flash and FlexMemory FFF Program flash memory size * * * * R Silicon revision * Z = Initial * (Blank) = Main * A = Revision after main T Temperature range (C) * V = -40 to 105 * C = -40 to 85 PP Package identifier * FM = 32 QFN (5 mm x 5 mm) * LF = 48 LQFP (7 mm x 7 mm) * LH = 64 LQFP (10 mm x 10 mm) CC Maximum CPU frequency (MHz) * * * * * N Packaging type * R = Tape and reel 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz 6.4 Example This is an example part number: Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 55 NXP Semiconductors Terminology and guidelines MK02FN128VLH10 6.5 48-pin LQFP part marking The 48-pin LQFP package parts follow the part-marking scheme in the following table. Table 39. 48-pin LQFP part marking MK Partnumber MK Part Marking MK02FN128VLF10 M02J7V MK02FN64VLF10 M02J6V 6.6 32-pin QFN part marking The 32-pin QFN package parts follow the part-marking scheme in the following table. Table 40. 32-pin QFN part marking MK Part number MK Part Marking MK02FN128VFM10 M02J7V MK02FN64VFM10 M02J6V 7 Terminology and guidelines 7.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Table continues on the next page... 56 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Terminology and guidelines Term Definition Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. 7.2 Examples EX AM PL E Operating rating: EX AM PL E Operating requirement: EX AM PL E Operating behavior that includes a typical value: 7.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 57 NXP Semiconductors Revision History Symbol Description Value Unit TA Ambient temperature 25 C VDD Supply voltage 3.3 V 7.4 Relationship between ratings and operating requirements O a gr tin ra pe g tin ( ) in. (m nt me n.) mi t era Op ing e uir req g tin era Op t en em uir req ax (m .) rat pe g tin ra ing ax (m .) O Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) dli n Ha ng ra g tin x.) ) in. (m li nd Ha ma g( tin a r ng Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 7.5 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8 Revision History The following table provides a revision history for this document. 58 NXP Semiconductors Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 Revision History Table 41. Revision History Rev. No. Date Substantial Changes 4 08/2016 * In "Power consumption operating behaviors" table, added "Low power mode peripheral adders--typical value" table * In "Thermal operating requirements" table, in footnote, corrected "TJ = TA + JA" to "TJ = TA + RJA"" * In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding maximum frequency of operation * Added new section, "Recommended connections for unused analog and digital pins" * Updated "NVM program/erase timing specifications" table; updated values for thversall (Erase All high-voltage time) * Added Terminology and Guidelines section * Updated Thermal Attributes value for 48LQFP * Added Device Revision Number table in front matter 3 4/2015 * Throughout: Modified notes related to 48-pin LQFP to say, "The 48-pin LQFP package for this product is not yet available; however, it is included in a Package Your Way program for Kinetis MCUs. Please visit www.Freescale.com/KPYW for more details." * On page 1: * In first bullet of introduction, updated power consumption data to align with the data in the "Power consumption operating behaviors" table * Under "Clocks," corrected second and third bullets--moved "with FLL" from "internal oscillators" to "multipurpose clock generator" bullet * Under "Communication interfaces," updated I2C bullet to indicate support for up to 1 Mbps operation * Under "Operating characteristics," specified that voltage range includes flash writes * In "Voltage and current operating requirements" table: * Removed content related to positive injection * Updated footnote 1 to say that all analog and I/O pins are internally clamped to VSS only (not VSS and VDD)through ESD protection diodes. * In "Power mode transition operating behaviors" table, removed rows for LLS2 and LLS3 * In "Power consumption operating behaviors" table: * Provided additional temperature data * Added Max IDD values based on characterization results equivalent to mean + 3 sigma * Removed rows for LLS2 and LLS3 * Updated "EMC radiated emissions operating behaviors" table * In "Thermal operating requirements" table, added the following footnote for ambient temperature: "Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + JA x chip power dissipation" * Updated "IRC48M Specifications": * Updated maximum values for firc48m_lv and firc48m_hv (full temperature) * Added specifications for firc48m_hv (-40C to 85C) * In "I2C timing" table, * Added the following footnote on maximum Fast mode value for SCL Clock Frequency: "The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the High drive pins across the full voltage range and when using the Normal drive pins and VDD 2.7 V." * Updated minimum Fast mode value for LOW period of the SCL clock to 1.25 * Added "I2C 1 Mbps timing" table Table continues on the next page... Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 59 NXP Semiconductors Revision History Table 41. Revision History (continued) Rev. No. Date Substantial Changes * Removed Section 6, "Ordering parts." * Added "48-pin LQFP part marking" section * Added "32-pin QFN part marking" section 2 8/2014 1 3/2014 60 NXP Semiconductors * On p. 1, under "Memories and memory interfaces," added bullet, "Preprogrammed Kinetis flashloader for one-time, in-system factory programming" * On p. 1, added parenthetical element to the following bullet under "Analog modules":Accurate internal voltage reference (not available for 32-pin QFN package) * On p. 1, added parenthetical element to the following bullet under "Timers":Two 2channel motor-control general-purpose timers with quadrature decoder functionality (FTM2 does not have external pins on the 32-pin QFN or the 48-pin LQFP package) * In "Voltage and current operating ratings" section, updated digital supply current maximum value * In "Voltage and current operating behaviors" section, updated input leakage information * In "Power consumption operating behaviors table": * Updated existing typical and maximum power measurements * Added new typical power measurements for the following: * IDD_HSRUN (High Speed Run mode, all peripheral clocks disabled, current executing CoreMark code) * IDD_HSRUN (High Speed Run mode, all peripheral clocks disabled, current executing while(1) loop) * IDD_RUN (Run mode current in Compute operation, all peripheral clocks disabled, executing CoreMark code) * IDD_RUN (Run mode current in Compute operation, all peripheral clocks disabled, executing while(1) loop) * IDD_VLPR (Very Low Power mode current in Compute operation, all peripheral clocks disabled, executing CoreMark code) * IDD_VLPR (Very Low Power Run mode current in Compute operation, all peripheral clocks disabled, executing while(1) loop) * Updated section, "EMC radiated emissions operating behaviors for 64 LQFP package" * In "Thermal attributes" section, added 64-pin LQFP and 32-pin QFN package values * Updated "MCG specifications" table * Updated "VREF full-range operating behaviors" table * In the "Part identification" section, added "Format" and "Fields" subsections Initial public release Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address:nxp.com/SalesTermsandConditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM, the ARM Powered logo, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. (c) 2014-2016 NXP B.V. Document Number K02P64M100SFA Revision 4, 08/2016