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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

1.3-MEGAPIXEL CMOS

ACTIVE-PIXEL DIGITAL

IMAGE SENSOR

MT9M413

Micron Part Number: MT9M413C36STC

Description

The MI-MV13 is a 1,280H x 1,024V (1.3 megapixel)

CMOS digital image sensor capable of 500 frames-per-

second (fps) operation. Its TrueSNAP™ electronic

shutter allows simultaneous exposure of the entire

pixel array. Available in color or monochrome, the sen-

sor has on-chip 10-bit analog-to-digital converters

(ADCs), which are self-calibrating, and a fully digital

interface. The chip's input clock rate is 66 MHz at

approximately 500 fps, providing compatibility with

many off-the-shelf interface components.

The sensor has ten 10-bit-wide digital output ports.

Its open architecture design provides access to internal

operations. ADC timing and pixel-read control are

integrated on-chip. At 60 fps, the sensor dissipates less

than 150mW, and at 500 fps less than 500mW; it oper-

ates on a 3.3V supply. Pixel size is 12 microns square,

and digital responsivity is 1,600 bits per lux-second.

Features/Top Level Specifications

• Array Format: 1,280H x 1,024 V (1,310,720 pixels)

• Pixel Size and Type: 12.0µm x 12.0µm TrueSNAP

(shuttered-node active pixel)

• Sensor Imaging Area: H: 15.36mm, V: 12.29mm,

Diagonal: 19.67mm

• Frame Rate: 0–500+ fps @ (1,280 x 1,024), >10,000

fps with partial scan, [e.g. 0–4000 fps @ (1,280 x 128)]

• Output Data Rate: 660 Mbs (master clock 66 MHz,

~500 fps)

• Power Consumption: < 500 mW @ 500 fps; <150 mW

@ 60 fps

• Digital Responsivity: Monochrome: 1,600 bits per

lux-second @ 550nm; ADC reference @ 1V

• Internal Intra-Scene Dynamic Range: 59dB

• Supply Voltage: +3.3V

• Operating Temperature: -5°C to +60°C

• Output: 10-bit digital through 10 parallel ports

•Conversion Gain = 13µV/e-

• Color: Monochrome or color RGB

• Shutter: TrueSNAP freeze-frame electronic shutter

• Shutter Efficiency: >99.9%

•Shutter Exposure Time: 2µs to > 33 msec

• ADC: On-chip, 10-bit column-parallel

• Package: 280-pin ceramic PGA

• Programmable Controls: Open architecture

On-chip:

•ADC controls

•Output multiplexing

•ADC calibration

Off-chip:

•Window size and location

•Frame rate and data rate

•Shutter exposure time (integration time)

•ADC reference

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

General

The MI-MV13 is a 1280H x 1024V (1.31 megapixel)

CMOS digital image sensor capable of 500 frames-per-

second (fps) operation. Its TrueSNAP™ electronic

shutter allows simultaneous exposure of the entire

pixel array. Available in color or monochrome, the sen-

sor has on-chip 10-bit analog-to-digital converters

(ADCs), which are self-calibrating, and a fully digital

interface. The chip’s input clock rate is 66 MHz at

approximately 500 fps, providing compatibility with

many off-the-shelf interface components as shown in

Figure 1.

The sensor has ten (10) 10-bit-wide digital output

ports. Its open architecture design provides access to

internal operations. ADC timing and pixel-read control

are integrated on-chip. At 60 fps, the sensor dissipates

less than 150 mW, and at 500 fps less than 500 mW; it

operates on a 3.3V supply. Pixel size is 12 microns

square and digital responsivity is 1600 bits per lux-sec-

ond.

The MI-MV13 CMOS image sensor has an open

architecture to provide access to its internal opera-

tions. A complete camera system can be built by using

the chip in conjunction with the following external

devices:

• An FPGA/CPLD/ASIC controller, to manage the

timing signals needed for sensor operation.

• A 20mm diagonal lens.

• Biasing circuits and bypass capacitors.

Figure 1: A Camera System Using the MI-MV13 CMOS Image Sensor

Controller

(FPGA, CPLD, ASIC, etc.)

System

Clock

System

Interface

Off-Chip

ADC

Pixel Array

(1280H x 1024V)

ADC Bias

+3.3V

System

Clock

Control

Timing

Port 1 D0~D9

Port 2 D10~D19

Port 3 D20~D29

Port 4 D30~D39

Port 5 D40~D49

Port 6 D50~D59

Port 7 D60~D69

Port 8 D70~D79

Port 9 D80~D89

Port 10 D90~D99

Memory

On-Chip Control

On-Chip

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 2: Sensor Architecture (not to scale)

Figure 3: Signal Path Diagram

BOTTOM ADCs

TOP ADCs

PIXEL ARRAY

MEMORY

SENSE AMPS

DIGITAL

CONTROL

Photo

Detector

Pixel

Memory

Sample

& Hold ADC

Per Column Processing

Pixel

DAC

ADC

Calibration

Offset

(VREF3-VCLAMP3)/20

BIAS

VLN2

ADC

registers

Bias

VLN1 Bias

VLP

VREF1 VREF4

VREF2

∑∑

Buffer

VRST_PIX

PG_N

TX_N

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 4: Functional Block Diagram

PIXEL ARRAY

Row Driver

Row Decoder

ROW

Row

Timing

Block

LogicRST

RowSTRT

RowDone

1280 x 10 SRAM

ADC Register

Sample

Data Shift /

Read 1280 x 10 SRAM

Output Register

Column Decoder

S/H

ADC

#1280

...

SRAM

Read

Control

10 x 10

Shift

Sense Amps

TX_N

PG_N

Output Ports

Pads

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

External Control Sequence

The MI-MV13 includes on-chip timing and control

circuitry to control most of the pixel, ADC, and output

multiplexing operations. However, the sensor still

requires a controller (FPGA, CPLD, ASIC, etc.) to guide

it through the full sequence of its operation.

With the TrueSNAP freeze-frame electronic shutter

signal charges are integrated in all pixels in parallel.

The charges are then sampled into pixel analog memo-

ries (one memory per pixel) and subsequently, row by

row, are digitized and read out of the sensor. The inte-

gration of photosignal is controlled by two control sig-

nals: PG_N and TX_N. To clear pixels and start new

integration, PG_N is made low. To transfer the data

into pixel memory, TX_N is made low. The time differ-

ence between the two procedures is the exposure time.

It should be noted that neither the PG_N or TX_N

pulses clear the pixel analog memory. Pixel memory

can be cleared during the previous readout (i.e., the

readout process resets the pixel analog memory), or by

applying PG_N and TX_N together (i.e., clearing both

pixel and pixel memory at the same time).

With the TrueSNAP freeze-frame electronic shutter

the sensor can operate in either simultaneous or

sequential mode in which it generates continuous

video output. In simultaneous mode, as a series of

frames are being captured, the PG_N and TX_N signals

are exercised while the previous frame is being read

out of the sensor. In simultaneous mode typically the

end of integration occurs in the last row of the frame

(row #1023) or in the last row of the window of interest.

The position of the start integration is then calculated

from the desired integration time. In sequential mode

the PG_N and TX_N signals are exercised to control the

integration time, and then digitization and readout of

the frame takes place. Alternatively, the sensor can run

in single frame or snapshot mode in which one image

is captured.

The sensor has a column-parallel ADC architecture

that allows the array of 1,280 analog-to-digital convert-

ers on the chip to digitize simultaneously the analog

data from an entire pixel row. The following input sig-

nals are utilized to control the conversion and readout

process:

The 10-bit ROW_ADDR (row address) input bus

selects the pixel row to be read for each readout cycle.

The ROW_STRT_N signal starts the process of reading

the analog data from the pixel row, the analog-to-digi-

tal conversion, and the storage of the digital values in

the ADC registers. When these actions are completed,

the sensor sends a response back to the system con-

troller using the ROW_DONE_N. Row address must be

valid for the first half of the row processing time (the

period between ROW_START_N and ROW_DONE_N).

The MI-MV13 contains a pipeline style memory

array, which is used to store the data after digitization.

This memory also allows the data from the previous

row conversion cycle to be read while a new conver-

sion is taking place.

The digital readout is controlled by lowering the

LD_SHFT_N signal, followed by the

DATA_READ_EN_N signal. LD_SHFT_N transfers the

digitized data from the ADC register to the output reg-

ister. DATA_READ_EN_N is used to enable the data

output from the output register. A new pixel row read-

out and conversion cycle can be started two clock

cycles after DATA_READ_EN_N is pulled low. The out-

put register allows the reading of the digital data from

the previous row to be performed at the same time as a

new conversion (pipeline mode). This means that the

total row time will be only that between when: (a) the

ROW_STRT_N signal is applied and ROW_DONE_N is

returned; and (b) LD_SHFT_N and DATA_READ_EN_N

are applied plus two clock cycles. The pipelined opera-

tion means there will always be 1 row of latency at the

start of sensor operation. The alternative to pipelined

operation is burst data operation in which a new pixel

row conversion is not initiated until after the output

high). The ratio of line active and blanking times can

be adjusted to easily match a variety of display and

collection formats. See “Timing Diagram For One

Row” on page 7.

Table 1: Conversion and Readout

Process

SIGNAL NAME DESCRIPTION

INPUT BUS

WIDTH

ROW_ADDR Row Address 10-bit

ROW_STRT_N Row Start 1-bit

LD_SHFT_N Load shift register 1-bit

DATA_READ_EN_N Data read enable 1-bit

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 5: Example 1 - Row 4 of the MI-MV13 Being Digitized

PG_N and TX_N

To start integration, the PG_N signal simultaneously

resets the photodetectors for the entire pixel array. To

end integration, the TX_N signal simultaneously trans-

fers charge from photodetector to memory inside each

pixel for the entire pixel array. In sequential mode the

PG_N and the TX_N pulses must have a minimum

duration of 64 SYSCLK cycles. In simultaneous mode

the PG_N and TX_N pulses must have a duration of 64

SYSCLK cycles and be applied in the window between

the 66th and 129th SYSCLK cycles. Additionally, in

simultaneous mode between exposures a single

SYSCLK duration pulse must be applied each row dur-

ing the 130th clock cycle.

ROW_ADDR

The address for the pixel row to be read is input

externally via this 10-bit input bus. Must be valid for at

least 66 SYSCLK cycles, must be valid when

ROW_STRT_N is pulled low.

ROW_STRT_N

This signal reads the contents of the pixel row speci-

fied by ROW_ADDR, converts the pixel row signal to

digital value, and stores the digital value in ADC regis-

ter (1280 x 10-bit).

This process is completed in 128-1291 SYSCLK

cycles. Must be valid for a minimum of two clock

cycles and a maximum of 100 clock cycles.

ROW_DONE_N

128-1291 SYSCLK cycles after ROW_STRT_N has

been pulled low the sensor acknowledges the comple-

tion of a row read operation/digitization by sending

out a low going pulse on this pin. Valid for two clock

cycles.

PIXEL ARRAY

Even

Columns

Odd

Columns

SYSCLK

Column Parallel 10 -bit

ADC 640 x 1

Column Parallel 10 -bit

ADC 640 x 1

Control

Logic/

Decoders

ADC

Controls

ADC

Controls

ROW_STRT_N

ROW_ADDR

1. Reads the contents of pixel row specified by ROW_ADDR

2. Converts pixel row signals to digital values

3. Stores digital values in ADC register (1280 x 10 bit)

Controller

ROW 4

PIXEL ARRAY

Even

Columns

Odd

Columns

SYSCLK

Column Parallel 10 -bit

ADC 640 x 1

Column Parallel 10 -bit

ADC 640 x 1

Control

Logic/

Decoders

ADC

Controls

ADC

Controls

ROW_STRT_N

ROW_ADDR

LD_SHFT_N

1. Reads the contents of pixel row specified by ROW_ADDR

2. Converts pixel row signals to digital values

3. Stores digital values in ADC register (1280 x 10 bit)

Controller

ROW 4

1. In order to minimize the sensor power con-

sumption, the row processing circuitry

operates at SYSCLK/2. Therefore, depend-

ing on the user’s implementation, there will

be either 128 or 129 SYSCLK cycles between

the start of ROW_STRT_N and

ROW_DONE_N.

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

LD_SHFT_N

This signal transfers the digitized data from the ADC

the power to the sense amplifiers. The first data (col-

umns 1-10) are available for output at the third rising

edge of SYSCLK after LD_SHFT_N is pulled low. May

be enabled simultaneously with or after the falling

edge of ROW_DONE_N. Must remain low the entire

time the data is being read out.

DATA_READ_EN_N

This signal is used to enable the data output from

the output register (1280 x 10-bit) to the ten, 10-bit

output ports. May be initiated simultaneously with or

after LD_SHFT_N is selected. Minimum width is one

clock cycle. Output Register

The use of an output register allows the processing

of a row to be performed while the digital data from

the previous operation is being read out of the sensor.

A new pixel readout and conversion cycle can be

started two clock cycles after DATA_READ_EN_N is

pulled low.

Figure 6: Timing Diagram For One Row

Table 2: Pixel Array

CLK 1 CLK 2 …CLK128

Port 1 Col. 1 Col. 11 … Col. 1271

Port 2 Col. 2 Col. 12 … Col. 1272

Port 3 Col. 3 Col. 13 … Col. 1273

Port 4 Col. 4 Col. 14 … Col. 1274

Port 5 Col. 5 Col. 15 … Col. 1275

Port 6 Col. 6 Col. 16 … Col. 1276

Port 7 Col. 7 Col. 17 … Col. 1277

Port 8 Col. 8 Col. 18 … Col. 1278

Port 9 Col. 9 Col. 19 … Col. 1279

Port 10 Col. 10 Col. 20 … Col. 1280

ROW_ADDR [0:9]

0 1 129 13167

ROW VA LI D XXXXXX

ROW_STRT_N

SYSCLK

ROW_DONE_N

LD_SHFT_N

DATA_READ_EN_N

DATA [0:99] 0 1 2 3 4 5 127

PG2

PG1

TX_N

1-3 nsec SKEW

66 130

2 0

PG_N

ROW_ADDR [0:9]

0 1 129 13167

ROW VA LI D XXXXXX

ROW_STRT_N

SYSCLK

ROW_DONE_N

LD_SHFT_N

DATA_READ_EN_N

DATA [0:99] 0 1 2 3 4 5 127

PG2

PG1

TX_N

1-3 nsec

66 130

2 0

PG_N

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 7: Frame Timing

The MI-MV13 contains special self-calibrating cir-

cuitry that enables it to reduce its own column-wise

fixed-pattern noise. This calibration process consists

of connecting a calibration signal (VREF2) to each of

the ADC inputs, and estimating and storing these off-

sets (7 bits) to subtract from subsequent samples. The

Typical I/O Signal Timing (Initialization Sequence)

diagram (Figure 8) shows the timing sequence to cali-

brate the sensor. Calibration occurs automatically after

logic reset (LRST_N) but it can also be started by the

user, by pulling CAL_STRT_N low. When calibration is

finished, the sensor generates the active low

CAL_DONE_N. Significant ambient temperature drift

may justify recalibration. See Figure 7 and Figure 8.

ROW_ST RT_N

ROW_DONE_N

LD_SHFT_N

DATA_READ_EN_N

1023

ROW_ADDR [0:9]

DATA [0:99]

1022

ROW1023

ROW1022

ROW1021

ROW0

ROW1

ROW1023

1023

N+1

ROW N-1

ROW N

PG_N=PG1+PG2

PG2

PG1

EXPOSURE TIM E (= 1023 –N rows)

TX_ N

READOUT (one full frame)

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 8: Typical I/O Signal Timing (Initialization Sequence)

CAL_STRT_N

CAL_STRT_N is a two-clock cycle-wide active-low

pulse that initiates the ADC calibration sequence. The

pulse must not be actuated for 1 microsecond after

either power-up or removal of the sensor from a

power-down state. Users may find it easiest to cali-

brate by means of the logic reset.

CAL_DONE_N

CAL_DONE_N is a two-clock cycle-wide active-low

output pulse that is asserted when the ADC calibration

is complete. The device will automatically initiate a

calibration sequence upon a logic reset. Completion of

this sequence, in cases where it is initiated by a reset, is

still with the CAL_DONE_N signal. This process is

complete within 112 SYSCLK cycles of CAL_STRT_N.

This process is complete within 112 SYSCLK cycles of

LRST_N.

LRST_N

LRST_N is a two-clock cycle-wide active-low pulse

that resets the digital logic. It puts all logic into a

known state (all flip-flops are reset). This signal also

initiates an ADC calibration sequence.

CAL_DONE_N

CAL_STRT_N

SYSCLK

CAL_DONE_N

LRST_N

SYSCLK

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Electronic Shutter

The MI-MV13 is intended to be operated primarily

with the TrueSNAP freeze-frame electronic shutter, but

is also capable of operating in Electronic Rolling Shut-

ter (ERS) mode. With TrueSNAP the shutter can be

operated to generate continuous video output (simul-

taneous mode or sequential mode) or capture single

images (single frame mode).

When considering timing for the various shutter

modes it is useful to keep in mind the functionality of

PG_N and TX_N. When PG_N is low, the photodetector

is shorted to a reset voltage source. When high, the

switch is open. When TX_N is low, the photodetector is

shorted to pixel memory. When high, they are discon-

nected. Please refer to the switches shown in the Signal

Path Diagram, Figure 3 on page 3. The memory is also

reset during readout. It occurs for the selected row in

the middle of the 0-66 clock interval after application

of ROW_STRT_N (approximately clocks 20 through

40).

TrueSNAP Simultaneous Mode

In simultaneous mode, as a series of frames are

being captured, the PG_N and TX_N signals are exer-

cised while the previous frame is being read out of the

sensor. In simultaneous mode typically the “end of

integration” occurs in the last row of the frame (row

#1023) or in the last row of the window of interest. The

position of the “start integration” is then calculated

from the desired integration time. Please note that

pixel memory is cleared during readout process

(Figure 9).

Figure 9: Typical Example of TrueSNAP

Simultaneous Mode: Exposure During

Readout

TrueSNAP Sequential Mode

In sequential mode the PG_N and TX_N signals are

exercised to control the integration time, and then dig-

itization and readout of the frame takes place. Please

note that pixel memory is cleared during readout pro-

cess. The photodetector is reset when PG_N is low.

Raising PG_N starts integration and lowering TX_N

while PG_N is still high ends integration by sampling

the signal into memory. There must be at least one

SYSCLK cycle after returning TX_N to the high state

until PG_N is lowered (Figure 10 on page 11).

Read row#0

Read row#1023

Exposure

time

Read row# 0

Read row#1023

Readout Time

ROW_ADDR

1023

PG_N

TX_N

Readout

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 10:

Typical Example of TrueSNAP

Sequential Mode: Exposure Following

Readout

TrueSNAP Single Frame

The MI-MV13 can run in single frame or snap-shot

mode in which one image is captured. In single frame

mode integration must be preceded with a void frame

read (selecting all addresses and applying

ROW_STRT_N) or PG_N and TX_N must be applied

together (for a minimum of 10 SYSCLK cycles) to clear

pixel and pixel memory. Holding PG_N and TX_N low

resets the photodioide (PG_N) and the analog memory

which is shorted to the photodiode by the TX_N

switch. To start integration both TX_N and PG_N are

released. To end integration and sample the signal into

memory TX_N is made low again for 10 clocks mini-

mum, up to 64 clocks (see Figure 6 on page 7). After

TX_N is returned to the high state there must be a

delay of >1 SYSCLK prior to lowering PG_N again to

erase charge in the photodetector.

Figure 11:

Typical Example of TrueSNAP Single

Frame Mode

ERS Mode

This mode is enabled by pulling PG_N high and

TX_N low.

Partial Scan Examples

The MI-MV13 can be partially scanned by sub-sam-

pling rows. The user may select which rows and how

many rows to include in a partial scan. For example,

with a 66-megahertz clock, a row time is approxi-

mately 2 microseconds, resulting in the following pos-

sibilities:

1 row in frame: 500,000 frames per second

2 rows in frame: 250,000 frames per second

10 rows in frame: 50,000 frames per second

100 rows in frame: 5,000 frames per second

256 rows in frame: 2,000 frames per second

512 rows in frame: 1,000 frames per second

1,024 rows in frame: 500 frames per second ...etc

Read row#0

Read row#1023

Readout Time

ROW_ADDR

1023

PG_N

TX_N

Read row#0

Read row#1023

Readout

Exposure

time

Exposure

time

TIME

ROW_ADDR

1023

PG_N

TX_N

READ ROW #0

EAD ROW #1023

EXPOSURE TIME

READOUT

“SLEEP” STATE “SLEEP” STATE

TIME

ROW_ADDR

1023

PG_N

TX_N

READ ROW #0

EAD ROW #1023

EXPOSURE TIME

READOUT

“SLEEP” STATE “SLEEP” STATE

Table 3: Pin Description

PIN NUMBER(S) SIGNAL NAME FUNCTION

DATA [99:0] Pixel data output bus that is ten pixels (100 bits) wide.

Bit 0 is the LSB (least significant bit) of the lowest order

pixel (See Table 2, Pixel Array, on page 7). In the group of ten pixels

being output, bit 9 is the MSB (most significant bit).

T13 DATA0

U14 DATA1

V15 DATA2

T14 DATA3

V16 DATA4