MPC8547ECHXAUJ - Freescale Semiconductor / Motorola

Freescale Semiconducto r

Technical Data

1Overview

This section provides a high-level overview of MP C8548E

features. Figure 1 shows the major functional units within

the MPC8548E.

Although this document is written from the perspective of

the MPC8548E, most of the material applies to the other

family members—MPC8547E, MPC8545E, and

MPC8543E—as well. When specific differences occur , such

as pinout differences and processor frequency ranges, they

will be identified as such.

For specific PVR and SVR numbers, refer to the MPC8548E

PowerQUICC™ III Integrated Pr ocessor Family Refer ence

Manual.

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8. Enhanced Three-Speed Ethernet (eTSEC) . . . . . . . . 26

9. Et hernet Management Int erface Electric al

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11. Programmable Interrupt Controller . . . . . . . . . . . . . 51

12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

14. PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15. High-S peed Serial I nterfaces (H SSI) . . . . . . . . . . . . 60

16. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

17. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 87

19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

21. System Design Information . . . . . . . . . . . . . . . . . . 128

22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 137

23. Document Revision History . . . . . . . . . . . . . . . . . . 141

MPC8548E PowerQUICC™ III

In tegrated Processor

Hardware Specificatio ns

Docu ment Numbe r: MPC854 8E EC

Rev. 6, 12/2009

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

2Freescale Semiconductor

Overview

Figure 1. MPC8548E Blo ck Diagr am

1.1 Key Features

The following list provides an overv iew of the MPC8548E feature set:

• High-performance 32- bit core built on Power Architecture™ technology.

— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can

be locked entirely or on a per-line basis, with separate locking for instructions and data.

— Signal-proce ssing engine (SPE) APU (auxiliary process ing unit). Provides an extensive

instruction set for vector (64-bit) integer and fractional operation s. These instructions use both

the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.

— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

— 36-bit real addressing

— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bi t) floating-point instructions.

— Memory management unit (MMU). E specially designed for embedded appli cations. Supports

4-Kbyte–4-Gbyte page sizes.

— Enhanced hardware and software debug support

Core Com plex

x8 PCI Express

4x RapidIO

66 MHz

PCI 32-bit

10/100/1Gb

MII, GMII, TBI,

RTBI, RGMII,

Serial

IRQs

SDRAM

DDR

Flash

SDRAM

GPIO

Bus

I2CI2C

Controller

eTSEC

32- b it P C I Bus In te r face

(If 64-bit not used)

e500

Coherency

Module

DDR/DDR2/

Memory Con troller

Local Bus Controller

Programmable Interrupt

Controller (PIC)

DUART

e500 Core

512-Kbyte

L2 Cache/

SRAM

32-bit PC I/

64-bit PCI/PCI-X

Bus Inter face

32-Kbyte L1

Instruction

Cache

32-Kbyte

L1 Data

Cache

OceaN

Switch

Fabric

Serial RapidIO™

PCI Express

4-Channel DMA

Controller

133 MHz

PCI/PCI-X

I2CI2C

Controller

RMII

10/100/1Gb

MII, GMII, TBI,

RTBI, RGMII, eTSEC

RMII

10/100/1Gb

MII, GMII, TBI,

RTBI, RGMII, eTSEC

RMII

10/100/1Gb

RTBI, RGMII, eTSEC

Security

Engine

XOR

Engine

RMII

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 3

Overview

— Performance monitor facility that is similar to, but separate from, the MPC8548E performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some features

that this device implements more specifically. An understanding of these differences can be critical to

ensure proper operations.

• 512-Kbyte L2 cache/SRAM

— Flexible configuration.

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— Cache mode supports ins truc tion caching, data caching, or both.

— External masters can force data to be allocated into the cache through programmed memory

ranges or spec ial transaction types (stashing).

— 1, 2, or 4 ways can be conf igured for stashing only.

— Eight-way set-associative cache organization (32-byte cache lines)

— Supports locking entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or by externally mastered transactions.

— Global locking and Flash clear ing done through writes to L2 configuration registers

— Instruction and data locks can be Fl ash cleared separately.

— SRAM features inc l ude the following:

– I/O devices access SRAM r egions by marking transactions as snoopa ble (global).

– Regions can reside at any aligned location in t he memory map.

– Byte-accessible EC C is protected using rea d-modif y-wri te trans act ion accesses for

s m all e r-th an -c ache - l in e acce sse s.

• Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 36-bit address space.

— Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express

– Four inbound windows plus a default window on RapidIO™

– Four outbound windows plus default tr anslation for PCI /PCI-X and PCI Express

– Eight outbound windows plus default translation for RapidIO with segmentation and

sub-segmentati on support

• DDR/DDR2 memory controller

— Programmable timing suppor ting DDR and D DR2 SDRAM

— 64-bit data interface

— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes

— DRAM chip configur ations from 64 Mbits to 4 Gbits with ×8/×16 data ports

— Full ECC suppor t

— Page mode support

– Up to 16 simultaneous open pages for DDR

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

4Freescale Semiconductor

Overview

– Up to 32 simultaneous open pages for DDR2

— Contiguous or discontiguous memory mapping

— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear

transactions

— Sleep mode support for self-refresh SDRAM

— On-die termination support when using DDR2

— Supports auto refr eshing

— On-the-fly power management using CKE signal

— Registered DIMM support

— Fast me mo ry access vi a JTAG port

— 2. 5-V SSTL_2 compatib le I/O (1.8 -V S STL_1.8 for DDR 2)

— Support for battery- backed main memory

• Programmable interrupt contr oller (PIC)

— Programming model is compliant with the OpenPIC architecture.

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 mess age interrupts with 32-bit messages

— Supports connection of an external interrupt controller s uch as the 8259 progr ammable

interrupt controlle r

— Four global high resolution timers/counters that can generate inte rrupts

— Supports a variety of other internal interrupt sources

— Supports fully neste d interrupt delivery

— Interrupts can be routed to external pin for external processing.

— Interrupts can be routed to the e500 core’s standar d or critical interr upt inputs.

— Interrupt summ ary registers allow fast identification of interrupt source.

• Integrated security engine (S EC) optimized to process all the algorithms associated with IPSec,

IKE, WTLS/WAP, SSL/TL S, and 3GPP

— Four crypto-channels, each supporting multi-command descriptor chains

– Dynamic assignment of crypto-execution units via an integrated contr olle r

– Buffer size of 256 bytes f or each execution unit, with flow control for large data sizes

— PKEU—public key execution unit

– RSA a nd Diffie-Hellman; progr ammable field size up to 2048 bits

– Elliptic c urve cryptography with F 2m and F(p) modes and programmable field size up to

511 bits

— DEU—Data Encryption Standard execution unit

– DES, 3DES

– Two key (K1, K2) or three key (K1, K2, K3)

– ECB a nd CBC modes for both DES and 3DES

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 5

Overview

— AESU—Advanced Encryption Standard unit

– Implements the Rijndael symmetric key cipher

– EC B, CBC, CT R, and CCM mod es

– 128-, 192-, and 256-bit key lengths

— AFEU—ARC four execution unit

– Implements a stream cipher compatibl e with the RC4 algorithm

– 40- to 128-bit programmable key

— MDEU—message digest execution unit

– SHA with 160- or 256-bit mess age digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— KEU—Kasumi execution unit

– Imple ments F8 algorithm for enc ryption and F9 algorithm for integrity check ing

– Also suppor ts A5/3 and GEA- 3 algorithms

— RNG—random number generator

— XOR engine for parity checking in RAID storage applications

• Dual I2C controllers

— Two- wire int erface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filter ing rejects spikes on t he bus

• Boot sequencer

— Optionally loads conf iguration data from s erial ROM at re set via the I2C interface

— Can be us ed to initialize conf iguration registers and/or memory

— Supports extended I2C addressing mode

— Data integrity checked with preamble signature and CRC

• DUART

— Two 4-wire interfaces (S IN, SOUT, RTS, CTS)

— Programming model compatibl e with the origi nal 16450 UART and the PC16550D

• Local bus contr oller (LBC)

— Multiplexed 32-bit address and data bus operating at up to 133 MHz

— Eight chip s elects support eight external slaves

— Up to eight-beat burst transfers

— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory cont roller.

— Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programm able ma chines (UPMs)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

6Freescale Semiconductor

Overview

– Dedicated singl e data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)

• Four enhanced three-speed Ethernet controllers (eTSECs)

— Three-speed support (10/100/1000 Mbps)

— Four controllers designe d to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™, 802.3z™,

802.3ac™, and 802.3ab™

— Support for var ious Ethernet physical interfaces:

– 1000 M bps full-duplex IEEE 802.3 GMII, IEEE 802. 3z TBI, RTBI, and RGMII

– 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII

— Flexibl e configu ration for mult iple PHY interface configura tions. See Section 8.1, “Enhanced

Th re e -Sp e e d Eth e rn e t Con troller (e TSEC)

(10/100/1Gb Mbps)—GMII/MII/ TBI/RGMII/RTBI/RMII Electrical Characteristics,” for

more information.

— TCP/IP acceleration and QoS features available

– IP v4 and IP v6 header recognition on rece ive

– IP v4 header checksum verification and generation

– TCP and UDP checksum verification and generation

– Per- packet configurable accelera tion

– Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2™, PPPoE session,

MPLS stac ks, and ESP/ AH IP-secur it y headers

– Supported in all FIFO modes

— Quality of servi ce support:

– Transmission fr om up to e ight physical queues

– Reception to up to eight physical queues

— Full- and half- duplex Ethernet support (1000 Mbps supports only full duplex):

– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or

software-programmed PAUSE frame gener ation and recognition)

— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and

IEEE Std. 802.1™ virtual local area network (VLAN) tags and priority

— VLAN insertion and deletion

– Per-frame VLAN control wo rd or defau lt V LAN fo r e a ch eTSEC

– Extracted VLAN control word passed to software separately

— Retrans miss ion following a collision

— CRC generation and verification of inbound/outbound frames

— Programmable Ethernet preamble insertion and extraction of up to 7 bytes

— MAC address recognition:

– Exact match on primary and virtual 48-bit unicast addresses

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 7

Overview

– VRRP and HSRP support for seamless router fail- over

– Up to 16 exact-match MAC addresses supported

– Broadcast address (accept/reject)

– Hash table match on up to 512 multicast addr esses

– Promis cuous mode

— Buffe r descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet

programming models

— RMON statistics support

— 10-Kbyte internal trans mit and 2-Kbyte rec eiv e FIFOs

— MII management interface for control and status

— Ability to force allocation of header information and buffer descriptors into L2 cache

• O CeaN swi tch f abric

— Full cross b ar packet switch

— Reorders packets fr om a source based on prior ities

— Reorders packets to bypa ss blocked packets

— Implements starvation avoidance algorithms

— Supports packets with payloads of up to 256 bytes

• Integrated DMA controller

— Four- channel controller

— All channels accessible by both the local and remote masters

— Extended DMA functions (advanced chaining and stridi ng capability)

— Support for scatter and gather transfers

— Misalig ned trans fer capabili ty

— Interrupt on completed segment, link, lis t , and error

— Supports transfers to or from any loca l memory or I /O port

— Selectable hardware -enforced coherency (snoop/no snoop)

— Ability to st art and flow control each DMA channel from external 3-pin interf ace

— Ability to launch DMA from single write transaction

• Two PCI/PCI-X controllers

— PCI 2.2 and PCI-X 1.0 compatible

— One 32-/64-bit PCI /PCI-X port with support for speeds of up to 133 M Hz (maximum PCI - X

frequency in synchronous mode is 1 10 MHz)

— One 32-bit PCI por t with support for speeds from 16 to 66 MHz (available when the other port

is in 32-bit mode)

— Host and agent mode support

— 64-bit dual addr es s cycle (DAC) support

— PCI-X suppor ts multiple split transactions

— Supports PCI-to- memory and memory-to-PCI streaming

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

8Freescale Semiconductor

Overview

— Memory prefetching of PCI read accesses

— Supports posting of processor- to-PCI and PCI-to-memory writes

— PCI 3.3-V compatible

— Selectable hardw are-enfor ced coher ency

• Serial RapidIO™ interf ace unit

— Supports RapidIO™ Interconnect Specification, Revision 1.2

— Both 1× and 4× LP-serial link interfaces

— Long- and short-haul electricals with selectable pre-compensation

— T ransmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per l ane

— Auto detection of 1×- and 4×-mode opera tion during port initialization

— Link initialization and synchr onization

— Large and small size transport information field support selectable at initialization time

— 34-bit addressing

— Up to 256 bytes data payload

— All transa cti on flows and priorities

— Atomic set/clr /inc /dec for read- modify- write operations

— Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at

a remote memory system

— Receiver-controlled flow control

— Error detection, recovery, and time-out for packets and control symbols as require d by the

RapidIO specification

— Register and register bit extensions as described in part VIII (Error Management) of the

RapidIO specification

— Hardware recovery only

— Register support is not required for so ftware- mediated error recovery.

— Accept-all mode of operation for fail-over support

— Support for R apidIO error injection

— Internal LP-serial and application interface-level loopback modes

— Memory and PHY BIST for at-speed production test

• RapidIO-compatible message unit

— 4 Kbytes of payload per message

— Up to sixteen 256-byte segments per message

— Two inbound data message structures within the inbox

— Capable of receiving three letters at any mailbox

— Two outbound data message structures within the outbox

— Capable of sending three l etters simultaneously

— Single segment multicast to up to 32 devIDs

— Chaining and direct modes in the outbox

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 9

Overview

— Single inbound doorbell message structure

— Facility to accept port-write messages

• PCI E xpres s in terface

— PCI Express 1.0a compatible

— Supports ×8, ×4, ×2, and ×1 link widths

— Auto-detection of number of connected lanes

— Selectable operation as root complex or endpoint

— Both 32- and 64-bit addressing

— 256-byte maximum payload size

— Virtual channel 0 only

— T r a f fic class 0 only

— Full 64-bit decode with 32-bit wide windows

• Pin multiple xing for the high speed I/O interfaces supports one of the following conf igurations:

— ×8 PCI Express

— ×4 PCI Express and 4× serial RapidIO

• Power management

— Supports power saving modes: doze, nap, and sleep

— Employs dynamic power management, which automatically min imizes power consumption of

blocks when they are idle

• System performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter-specific events

— Supports 64 ref erence events that can be counted on any of the e i ght counters

— Supports duration and quantity threshold counting

— Burstiness featur e that permits counting of burst events with a programmable time between

bursts

— Triggering and chaining capability

— Ability to generate an int errupt on overflow

• System access port

— Uses JTAG interface and a TAP controller to access entire system memory map

— Supports 32-bit accesses to configuration registers

— Supports cache-line burst accesses to main memory

— Supports large block (4-Kbyte) uploa ds and downloads

— Supports continuous bit streaming of entir e block for fast upload and download

• JTAG boundary scan, designed to comply with IEEE Std. 1149.1™

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

10 Freescale Semiconductor

Elect rical Characteristi cs

2 Electrical Characteristics

This section provides th e AC and DC electrical specif i cati ons and the rmal charact er isti cs f or the

MPC8548E. This device is cur rently targeted to these specifications. Some of thes e specifi cations are

independent of the I/O cell, but are included for a more complete reference. These are not pur ely I/O buf fer

design specifications.

2.1 Over all DC Electrical Ch aracteristi cs

This s ection covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Rat ings

Table 1 provides the absolute maximum ra tings .

Table 1. Absolute Maximum Ratings 1

Characteristic Symbol Max Valu e Unit Notes

Core s u pply voltage VDD –0.3 to 1 .21 V —

PLL supply voltage AV DD –0.3 to 1.21 V —

Core power supply for SerDes transceiv ers SVDD –0.3 to 1 .21 V —

P ad power suppl y for SerD es transceivers XVDD –0 .3 t o 1.21 V —

DDR and DDR2 DRAM I/O voltage GVDD –0.3 t o 2.75

–0.3 to 1.98 V—

Three-speed Ethern et I/O voltage LV DD (for eTSEC1

and eTSEC2) –0.3 to 3.63

–0.3 to 2.75 V3

TVDD (for eTSEC3

and eTSEC4) –0.3 to 3.63

–0.3 to 2.75 3

PCI/PCI-X, DUART, system control and power mana gement,

I2C, Ethernet MII man agem ent, and JTAG I/O voltage OVDD –0.3 to 3.63 V —

Local bus I/O vo lt age BVDD –0 .3 t o 3.63

–0.3 to 2.75 V—

Input voltage DDR/DDR2 DRAM signal s MVIN –0.3 to (GVDD + 0.3) V 4

DDR/DDR2 DRAM reference MVREF –0.3 to

(GVDD/2 + 0.3) V—

Three-speed Ethernet I/O signals LVIN

TVIN

–0.3 to (LVDD + 0.3)

–0.3 to (TVDD + 0.3) V4

Local bus signal s BVIN –0.3 to (BVDD + 0.3) — —

DUAR T, SYSCLK, system con tr ol and power

mana gem ent, I2C, Et hernet MII management,

and JTAG signals

OVIN –0.3 to (OVDD + 0.3) V 4

PCI/PCI-X OVIN –0.3 to (OVDD + 0.3) V 4

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 11

Elect rical Characteristi cs

2.1.2 Re commended Operating Co nditions

Table 2 provides the recommended operating conditions for this device. Note that the values in Table 2 are

the recommended a nd tested opera ting conditions. Proper de vice operation outs ide these conditio ns is not

guaranteed.

Storage temperature range TSTG –55 to 150 °C—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute max imum ratin gs are stress ratings only, and

functi onal operation at the maxim um s is not guaranteed . Str esses beyond those listed may af fect device rel iability or cause

permanent dam age to the device.

2. The –0.3 to 2.75 V range is f or DDR and –0.3 t o 1.98 V range i s f or DDR2 .

3. The 3.63 V maximum is only supported when th e port is c onfigured in GMII, MII, RMII, or TBI modes; other wise the 2.75 V

maximum applies. See Sectio n 8 .2 , “F I F O, GMII, MII, T B I, R G MII, RM I I, a nd RTBI AC Tim in g Spe c ificatio n s,” for details on

the recommended operating conditions per protocol.

4. (M,L,O)VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

Tabl e 2. Recommended Operating Conditions

Characteristic Symbol Recommended

Value Unit Notes

Core supply voltage VDD 1 .1 V ± 55 mV V —

PLL supply voltage AVDD 1.1 V ± 55 mV V 1

Core power supply for SerDes transceivers SVDD 1.1 V ± 55 mV V —

Pad power supply for SerDes transceivers XVDD 1.1 V ± 55 mV V —

DDR and DDR2 DRAM I/O voltage GVDD 2.5 V ± 125 mV

1.8 V ± 90 mV V—

Three-speed Ethernet I/O voltage LV DD 3.3 V ± 165 mV

2.5 V ± 125 mV V4

TVDD 3.3 V ± 165 mV

2.5 V ± 125 mV —4

PCI/PCI-X, DUAR T, system control and power managem ent, I2C,

Ethernet MII man agem ent, and JTAG I/O vo ltage OVDD 3.3 V ± 165 mV V 3

Local bus I/O v oltage BVDD 3.3 V ± 165 mV

2.5 V ± 125 mV V—

Input voltage DDR and DDR2 DRAM signal s MVIN GND to GVDD V2

DDR and DDR2 DRAM reference MVREF GND to GVDD/2 V 2

Three-speed Ethernet signa ls LVIN

TVIN

GND to LVDD

GND to TVDD

Local bus signals BVIN GND to BVDD V—

PCI, DUART, SYSCLK, system control and power

management, I2C, Ethe rnet MII mana gem ent, and

JTAG signals

OVIN GND to OVDD V3

Table 1. Absolute Maximum Ratings 1 (conti nued)

Characteristic Symbol Max Valu e Unit Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

12 Freescale Semiconductor

Elect rical Characteristi cs

Figure 2 shows the undershoot and overshoot voltages at the interfaces of this device.

Figu re 2. Over sh oot/Undershoot Vol t age for G V DD/OVDD/LVDD/BVDD/TVDD

The core voltage must always be provided at nominal 1.1 V. Voltage to the processor inte rface I/Os are

provided thr ough s eparate s ets of supply pins and must be provided at the voltages shown in Table 2. The

input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based

receivers ar e simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications . The DDR

SDRAM interface uses a single-ended differential receiver referenced the externally supplied MVREF

signal (nominally set to GVDD/2) as is appropriate for the SSTL2 ele ctrical signaling standard.

Junction tempe rature range Tj 0 to 105 °C—

Notes:

1. This vol tage is the input to the filter discussed in Sec tion 21. 2, “PLL Po w er Supply Fi ltering ,” and not necessari ly the v olt age

at the AVDD pin, which may be reduced f rom VDD by the filter.

2. Caution: MV IN must not e xceed GVDD b y mor e than 0.3 V. This lim it may be e xceeded for a ma ximum of 20 ms during

power-on reset and power-down sequences .

3. Caution: OVIN must not e xceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences .

4. Caution: L/ TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms durin g

power-on reset and power-down sequences .

Table 2. Recommended Operating Conditions (continued)

Characteristic Symbol Recommended

Value Unit Notes

GND

GND – 0.3 V

GND – 0.7 V Not to Exceed 10%

B/G/L/O/TVDD + 20%

B/G/L/O/TVDD

B/G/L/O/TVDD + 5 %

of tCLOCK1

1. tCLOCK re fers to the cl ock period associated wit h the respective interface:

VIH

VIL

Notes:

2. Please note that with the PCI ov ershoot all owed (as speci fi ed above ), the device

does not ful ly comply with the maximum AC ratings and device protection

guidel ine outlined in the PCI rev. 2.2 standard (section 4.2.2.3 ).

For I2C and JTAG, tCLOCK ref erences SYSCLK.

For DDR, tCLOCK references MCLK.

Fo r eT S EC, tCLOCK ref erences EC_GTX_CLK125.

For L B IU, tCLOCK references LC LK.

For P CI, tCLOCK re ferenc es PCI

_CLK or SYSCLK.

For S e rDe s, tCLOCK r eferences SD_REF_CLK.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 13

Elect rical Characteristi cs

2.1.3 O utput Driver Characteristics

Table 3 provides information on the characteristics of th e output driver strengths. The values are

prelimina ry estimates .

2.2 Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device

operation. These r equir ements are as follows for power-up:

1. VDD, AVDD_n, B VDD, LV DD, OVDD, SVDD, TVDD, X V DD

2. GVDD

All supplies must be at their stable values within 50 ms.

NOTE

Items on the same line have no or der ing requirement with respect to one

another. Items on separate lines must be ordered sequentially such that

voltage rails on a previous step must reach 90% of their value before the

voltage rails on the cur re nt ste p reach 10% of theirs.

Tabl e 3. Ou t put D ri v e C apabili ty

Driver Type Programmable

Output Impedance

(Ω)

Supply

Voltage Notes

Local bus interface utiliti es signals 25

25 BVDD = 3.3 V

BVDD = 2.5 V 1

45(default)

45(default) BVDD = 3.3 V

BVDD = 2.5 V

PCI signals 25 OVDD = 3. 3 V 2

45(default)

DDR signal 18

36 (half str ength mode) GVDD = 2.5 V 3

DDR2 signal 18

36 (half str ength mode) GVDD = 1.8 V 3

TSEC/10/100 signals 45 L/TVDD = 2.5/3.3 V —

DUART, syste m co ntrol, JTAG 45 OVDD = 3. 3 V —

I2C 150 OVDD = 3. 3 V —

Notes:

1. The driv e strength of the lo cal bus interface is determined by the conf iguration of the appropriat e bits in PORIM PSCR.

2. The driv e strength of the PCI interface is determi ned by the setting of the PCI_GNT1 signal at reset.

3. The driv e strength of the DDR interface in hal f-strength mode is at Tj = 105°C and at GVDD (min ).

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

14 Freescale Semiconductor

Power Characteristics

NOTE

In order to guarantee MCKE low during power-up, the above sequencing for

GVDD is required. If there is no concern about any of the DDR signals being

in an indeterminate state during power-up, then the sequencing for GVDD is

not required.

NOTE

From a system standpoint, if any of the I/O power supplies ramp prior to the

VDD core suppl y, the I/Os associated with that I/O supply may dr ive a logic

one or zero during power -up, and extra current may be drawn by the device.

3 P ower Characteristics

The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this

family of PowerQUICC III devices is shown in Table 4.

Table 4. MPC8548E Po wer Dissipation

CCB Frequency1Cor e Frequency SLEEP2Typical-653Typical-1054Maximum5Unit

400 800 2.7 4.6 7.5 8.1 W

1000 2.7 5.0 7.9 8.5 W

1200 2.7 5.4 8.3 8.9

500 1500 11.5 13.6 16.5 18.6 W

533 1333 6.2 7.9 10.8 12.8 W

Notes:

1. CCB frequency is t he SoC plat form frequency, which co rr esponds to the DDR data rate.

2. SLEEP is based on VDD = 1. 1 V, Tj = 65°C.

3. Typical-65 is based on VDD = 1.1 V, Tj = 65°C, running Dhrystone.

4. Typical-105 is based on VDD = 1 .1 V, Tj = 105°C, running Dhrystone.

5. Maxim um is based on VDD = 1.1 V, Tj = 105°C, running a smoke tes t.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 15

Input Cloc ks

4 Input Clocks

This section discusses the timing for the input clocks.

4.1 System Clo ck Ti mi ng

Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8548E.

4.2 Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the s ampling latch is the n

used as an input to the counters of the PIC and the Time Bas e unit of the e500. There is no jitter

specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB

clock. That is, minimum clock high time is 2 × tCCB, and minimum clock low time is 2 × tCCB. There is

no minimum RTC frequency; RTC may be grounded if not needed.

Tab le 5. SYSC LK AC Timing Spec ificat io ns

At recommended operati ng conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition Symbol Min Typ Max Unit Notes

SYSCLK frequency fSYSCLK 16 — 133 MHz 1, 6, 7, 8

SYSCLK cycle tim e tSYSCLK 7.5 — 60 ns 6, 7, 8

SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns 2

SYSCLK duty cycl e tKHK/tSYSCLK 40 — 60 % 3

SYSCLK jitter — — — ± 150 ps 4, 5

Notes:

1. Caution: The CCB cloc k to SYSCLK rat io and e500 core to CCB cloc k rati o settings must be cho sen such that the resulti ng

SYSCLK frequenc y, e500 (core ) frequen cy, and CCB cloc k frequency do not exceed th eir resp ective maximum or mini mum

operating frequencies .Refer to Sectio n 1 9.2, “CCB/SYSCLK PLL Rati o,” and Secti on 1 9.3, “e500 Core PLL Ratio,” f or ratio

settings.

2. Rise and f all times for SYSCLK are measured at 0.6 and 2.7 V.

3. Timing i s guaranteed by design and characterization.

4. This repr esents the total input jitter— short term and long term—and is guar anteed by design.

5. The SYSCLK driv er’s closed loop j it ter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connect ed PLL-based devices to track SYSCLK drivers with the spec if ied jitter.

6. This par am eter has been adjusted slower according to the workaround fo r device erratum GEN 13.

7. For s pread spectrum clocki ng. Guidelines are + 0% to –1% down sp read at mo dulation rat e between 20 and 60 kHz on

SYSCLK.

8. System with operating core f requency less than 1200 M Hz m ust limit SYSCLK frequency to 100 MHz maxi m um ..

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

16 Freescale Semiconductor

Input Clocks

4.3 eTSEC Gigabit Reference Clock Timing

Table 6 provides the eTSEC gigabit reference clocks (EC_GT X_CLK125) AC timing specifications for

the MPC8548E.

4.4 PCI/PCI-X Reference Clock Timing

When the PCI/PCI-X controller is conf igured for asynchronous operation, the refe rence clock for the

PCI/PCI-x controller is not the SYSCLK input, but instead the PCIn_CLK. Table 7 provides the

PCI/PCI-X reference clock AC timing specifications for the MPC8548E.

Table 6. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit Notes

EC_GTX_CLK125 frequency fG125 —125—MHz—

EC_GTX_CLK125 cycle time tG125 —8—ns

EC_GTX_CLK125 r ise and fall time

L/TVDD = 2.5 V

L/TVDD = 3.3 V

tG125R, tG125F ——

0.75

1.0

ns 1

EC_GTX_CLK125 duty cycle G MII, TB I

1000Base-T f or RGM II , RTBI

tG125H/tG125 45

—55

%2, 3

Notes:

1. Rise and f all times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TVDD = 2.5 V, and from 0.6 and 2.7 V f or

L/TVDD = 3.3 V.

2. Timing i s guaranteed by design and characterization.

3. EC_GTX_CLK12 5 is used to gener ate the GTX clock TSEC

_GTX_ CLK for the eTSEC transmitter with 2% degradation.

EC_GTX_CLK125 duty cycle can be lo osened from 47/53% as long as the PHY dev ic e can toler ate the duty cycle generated

by the TSEC

_ GTX_CLK. See Sect ion 8.2.6, “RGM II and RTBI AC Timing Specifications,” for d uty cycle for 10Base-T and

100Base-T reference clock.

Table 7. PCI

_C LK AC Tim ing Specifica tions

At recommended operati ng conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition Symbol Min Typ Max Unit Notes

PCI

_CLK frequency fPCICLK 16 — 133 MHz —

PCI

_CLK cycle time tPCICLK 7.5 — 60 ns —

PCI

_CLK r ise and fall time tPCIKH, tPCIKL 0. 6 1.0 2.1 ns 1, 2

PCI

_CLK du ty cyc l e t PCIKHKL/tPCICLK 40 — 60 % 2

Notes:

1. Rise and f all times for SYSCLK are measured at 0.6 and 2.7 V.

2. Timing i s guaranteed by design and characterization.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 17

Input Cloc ks

4.5 Platform to FIFO Restrictions

Please note the foll owing FIFO maximum speed restrictions based on platform speed.

For FIFO GMII mode:

FIFO TX/RX clock frequency ≤ platform clock f r equency/4.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more

than 127 MHz

For FIFO encoded mode:

FIFO TX/RX clock frequency ≤ platform clock f r equency/4.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more

than 167 MHz.

4.6 Platform Frequency Requirements for PCI-Express and Serial

RapidIO

The CCB clock frequency must be considered for proper ope ra tion of the high-speed PCI-Express and

Serial RapidIO interfaces as described below.

For proper PCI Express operation, the CCB c lock frequency must be gre ater than:

527 MHz × (PCI -E x p re s s lin k wi dt h )

See MPC8548ERM, Rev. 2, PowerQUICC™ III Integr ated Process or Family Reference Manual,

Section 18.1.3. 2, “Link Width,” for PCI Express interface width details.

For proper serial RapidIO operation, the C CB clock frequency must be greater than:

2 × (0.80) × (Serial RapidIO interface frequency) × (Seria l Rapi dIO link widt h)

See MPC8548ERM, Rev. 2, PowerQUICC™ III Integr ated Process or Family Reference Manual,

Section 17.4, “1x/4x LP-Serial Signal Descriptions,” for serial RapidIO interface width and frequency

details.

4.7 Other Input Clocks

For infor mation on the input clocks of other functional blocks of the platform see the specifi c section of

this document.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

18 Freescale Semiconductor

RESET Initialization

5 RESET Initialization

This section describes the AC electrical specifications for the RESE T initialization timing requirements of

the MPC8548E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM

component(s).

Table 9 provides the PLL lock times.

5.1 Power-On Ramp Rate

This section describes the AC electrical specifications for the power-on ramp rate requirements.

Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ES D circuitry.

Table 10 pr ovides the power supply ramp rate specifications.

Table 8. RESET In itiali za t io n Ti min g Specificat io ns

Parameter/Condition Min Max Unit Notes

Required asser tion time of HRESET 100 — μs—

Minimum assertion time for SRESET 3 — SYSCLKs 1

PLL input set up ti me with stable SYSCLK before HRESET negation 100 — μs—

Input set up time f or POR conf igs (other than PLL confi g) wi th respect to

negati on of HRESET 4 — SYSCLKs 1

Input hold time fo r al l POR configs ( including PLL config) with respect to

negati on of HRESET 2 — SYSCLKs 1

Maximum valid-to-high impedance time for actively driven POR confi gs with

respect to negation of HRESET — 5 SYSCLKs 1

Note:

1. SYSCLK is the primary cloc k input for the MP C8548E.

Ta ble 9. PLL Lo ck Times

Parameter/Condition Min Max Unit

Core and plat form PLL lock ti m es — 100 μs

Local bus PLL loc k ti m e — 50 μs

PCI/PCI-X bus PLL lock ti me — 50 μs

Table 10. Po wer Supply Ramp Rate

Parameter Min Max Unit Notes

Requir ed ramp rat e for MVREF — 3500 V/s 1

Requir ed ramp rat e for VDD — 4000 V/ s 1, 2

Note:

1. Maximum ramp rate from 200 to 500 mV is most critical as this range ma y falsel y trigger the ESD circuit ry.

2. VDD itself is not vulnerable to false ESD triggering; however, as per Secti on 21.2, “P LL Po wer Supply Filt eri ng,” th e

recommended AVDD_CORE, AVD D_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters ar e all connecte d to VDD.

Their ramp rates should be equal to or less than the VDD ram p rate.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 19

DDR and DDR2 SDRAM

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8548E. Note that GVDD(typ) = 2.5 V for DDR SDRAM, and GVDD(typ) = 1.8 V for DDR2

SDRAM.

6.1 DDR SDRAM DC El ectrical Characteristics

Table 11 provides the recommended operating conditions for the DDR2 SDRAM controller of the

MPC8548E when GVDD(typ) = 1.8 V.

Table 12 provides the DDR2 I/O capacitance when GVDD(typ) = 1.8 V.

Table 11. DDR2 SDRAM DC Electrical Char acteristics fo r GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GVDD 1.71 1.89 V 1

I/O reference voltage MVREF 0.49 ×GVDD 0.51 ×GVDD V2

I /O t e rm in atio n voltag e V TT MVREF –0.04 MV

REF + 0.04 V 3

Input high volt age VIH MVREF +0.125 GV

DD +0.3 V —

Input low voltage VIL –0.3 MVREF – 0.125 V —

Output leakage current IOZ –50 50 μA4

Output high current (VOUT = 1.420 V) IOH –13.4 — mA —

Output l o w c u rre n t (VOUT = 0. 280 V) IOL 13.4 — mA —

Notes:

1. GVDD is expected to be withi n 50 mV of the DRAM VDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to trac k GVDD DC variations as measured at the r eceiver. P eak-to-pe ak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not appl ied directly to the device. It is the supply to which f ar end signal termin ation is made and is expected to be

equal to MVREF. This rail should t rack var iations in the DC level of MVREF.

4. Output l eakage is m easured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

Table 12. DDR2 SDRAM Capacitance for GVDD(typ) =1.8 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capac it ance: DQ, DQS, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF1

Note:

1. This par am eter is s am pled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C , V OUT = GVDD/2 , VOUT (peak-to-peak) = 0.2 V.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

20 Freescale Semiconductor

DDR and DDR2 SDRAM

Table 13 provides the recommended operating conditions for the DDR SDRAM controller when

GVDD(typ) = 2.5 V.

Table 14 provides the DDR I/O capacitance when GVDD(typ) = 2.5 V.

Table 15 pr ovide s the current draw character i stics f or MV REF.

Table 13. DDR SDRAM DC Electrical Characteristics for GVDD(typ ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GVDD 2.375 2.625 V 1

I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V2

I /O t e rm in atio n voltag e V TT MVREF – 0. 04 MVREF + 0.04 V 3

Input high volt age VIH MVREF + 0.15 GVDD + 0.3 V —

Input low voltage VIL –0.3 MVREF – 0.15 V —

Output leakage current IOZ –50 50 μA4

Output high current (VOUT = 1.95 V) IOH –16.2 — mA —

Output l o w c u rre n t (VOUT = 0. 35 V ) IOL 16.2 — mA —

Notes:

1. GVDD is expected to be withi n 50 mV of the DRAM VDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to trac k GVDD DC variations as measured at the r eceiver. P eak-to-pe ak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not appl ied directly to the device. It is the supply to which f ar end signal termin ation is made and is expected to be

equal to MVREF. This r ail should tr ack variations in the DC le vel of MVREF.

4. Output l eakage is m easured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

Table 14. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

Input/ output capac it ance: DQ, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS CDIO —0.5pF1

Note:

1. This par am eter is s am pled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA =25°C, V

OUT = G V DD/2 , VOUT (peak-to-peak) = 0.2 V.

Table 15. Current Draw Characteristics for MVREF

Parameter/Condition Symbol Min Max Unit Notes

Current draw f or MVREF IMVREF — 500 μA1

Note:

1. The voltage regulator for MVREF must be able to supply up to 500 μA cur rent.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 21

DDR and DDR2 SDRAM

6.2 DDR SDRAM AC Electrical Characteristic s

This section provides th e AC electrica l character i stics for the DDR SDRAM interface. The DDR

controller supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings

at data rates of 333 MHz. DDR2 is supported with the following AC timings at data rates down to

333 MHz.

6.2.1 DDR SDRAM Input AC Timing Specifications

Table 16 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 1.8 V.

Table 17 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.

Table 18 provides the input AC timing specifications for the DDR SDRAM interface.

Table 16. DDR2 SDRAM Input AC Timing Specification s for 1.8-V Interface

At rec om m end ed oper a ting co nd ition s

Parameter Symbol Min Max Unit

AC input low voltage VIL —MV

REF – 0.25 V

A C input high voltage VIH MVREF + 0.25 — V

Tabl e 17. DDR SDRAM Input AC Timing Specifications f or 2.5-V Interface

At rec om m end ed oper a ting co nd ition s.

Parameter Symbol Min Max Unit

AC input low voltage VIL —MV

REF – 0.31 V

A C input high voltage VIH MVREF + 0.31 — V

Table 1 8. DDR SDRAM Input AC T iming S pecifications

At rec om m end ed oper a ting co nd ition s.

Parameter Symbol Min Max Unit Notes

Controller Skew for MDQS—MDQ/MECC

533 MHz

400 MHz

333 MHz

tCISKEW

–300

–365

–390

300

365

390

ps 1, 2

Notes:

1. tCISKEW represents the tota l amount o f skew consumed b y the controller between MDQS[n] and any c orresponding bit that

will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW = ± (T/4 – abs(tCISKEW)) where T is the cl ock period and abs(tCISKEW) is the

absolute value of tCISKEW.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

22 Freescale Semiconductor

DDR and DDR2 SDRAM

6.2.2 DDR SDRAM Output AC Timing Specifications

Table 19. DDR SDRAM Output AC Timing Specifications

At rec om m end ed oper a ting co nd ition s.

Parameter Symbol1Min Max Unit Notes

MCK[n] c ycle time, MCK[

]/MCK[

] cro s si ng tMCK 3.75 6 ns 2

ADDR/CMD output set up wit h respect t o MCK

533 MHz

400 MHz

333 MHz

tDDKHAS

1.48

1.95

2.40

—

ns 3

ADDR/CMD output hold with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHAX

1.48

1.95

2.40

—

ns 3

MCS[

] o u tput se tup with re s p e ct to MCK

533 MHz

400 MHz

333 MHz

tDDKHCS

1.48

1.95

2.40

—

ns 3

MCS[

] output hold with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHCX

1.48

1.95

2.40

—

ns 3

MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4

MDQ/MECC/MDM output setup with re spect

to MDQS 533 MHz

400 MHz

333 MHz

tDDKHDS,

tDDKLDS 538

700

900

—

ps 5

MDQ/MECC/MDM ou tput hold wi th re spec t to

MDQS 533 MHz

400 MHz

333 MHz

tDDKHDX,

tDDKLDX 538

700

900

—

ps 5

MDQS preamble start tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK + 0.6 ns 6

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 23

DDR and DDR2 SDRAM

NOTE

For the ADDR/CMD setup and hold specifications in Table 19, it is

assumed that the clock control register is set to adjust the memory clocks by

1/2 applied cycle.

Figure 3 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).

Figure 3. Timin g Diag ram for tDDKHMH

MDQS epilogue end tDDKHME –0.6 0.6 ns 6

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

inputs and t(first two letters of functional bl ock)(reference)(state)(si gna l)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock ( KH or KL) unt il the output went invalid (AX or DX). For e xam ple,

tDDKHAS sy mbolizes DDR t iming (DD) f or t he ti me t MCK memory clock ref erence (K) goes from the high (H) stat e until output s

(A) are s etup (S) or output valid time. Also, tDDKLDX symbol izes DDR timing (DD) for the time tMCK memory clock referenc e

(K) goes lo w (L) until data outputs (D) are in valid (X) or data out put hold time.

2. All MCK/MCK referenced measurements are m ade f rom the crossing of the t wo signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MC S , and MDQ/MECC/MDM /MDQS .

4. Note t hat tDDKHMH f ollows the symbol conventions de scribed i n note 1. F or example, tDDKHMH d escribes the DDR timing (DD)

from the rising edge of the MCK[

] clock (KH) unt il the MDQS signal is valid (MH). tDDKHMH c an be modified through cont rol

of the MDQS overr ide bits (called WR_DATA_DELAY) in the TIMING_CFG _2 register. This will typically be set to the same

delay as in DDR_ SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these 2

parameters have been set to the sam e adj ustment value. See the

MPC8548E Power QUICC™ III Integrated Processor

Reference Manual

for a descripti on and understandi ng of the ti m ing mo dif icatio ns enabled by use of these bit s.

5. Determined b y ma ximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (M DM ). The data strobe should be centered inside of the data ey e at the pins of the microprocessor.

6. All outputs a re re ferenc ed to the rising edg e of MC K[

] at th e pins of the microprocess or. Note that tDDKHMP follows th e

symbol conventions described in note 1.

Table 19. DDR SDRAM Output AC Timing Specifications (con tinued)

At rec om m end ed oper a ting co nd ition s.

Parameter Symbol1Min Max Unit Notes

tDDKHMHmax) = 0. 6 ns

MDQS

MCK[

]

MCK[

]tMCK

tDDKHMH(min) = –0.6 ns

MDQS

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

24 Freescale Semiconductor

DDR and DDR2 SDRAM

Figure 4 shows the DDR SDRAM output timing diagram.+

Figure 4. DDR SDRAM Output Timing Diagram

Figure 5 provides the AC test load for the DDR bus.

Figure 5. DDR AC Test Load

ADDR/CMD

DDKHAS

, t

DDKHCS

DDKLDS

DDKHDS

MDQ[x]

MDQS[

]

MCK

[

]

MCK[

]

MCK

DDKLDX

DDKHDX

D1D0

DDKHAX

, t

DDKHCX

Write A0 NOOP

DDKHME

DDKHMP

DDKHMH

Output Z0 = 50 ΩGVDD/2

RL = 50 Ω

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 25

DUART

7DUART

This section describes the DC and AC electrical s pecif i cations for the DUART interface of the

MPC8548E.

7.1 DUART DC Electrical Characteristics

Table 20 provides the DC elect rical characteristics for the DUART interface.

7.2 DUART AC Electrical Sp ecifications

Table 21 provides the AC timing parameters for the DUART interface.

Table 20. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-l evel input voltage VIL –0.3 0.8 V

Input cur rent (VIN1 = 0 V or VIN = VDD) IIN —±5 μA

High-level output voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V

Low-lev el output voltage (OVDD = min, IOL = 2 mA) V OL —0.4V

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.

Table 21. DUART AC Ti m in g S pe ci f ic a t io ns

Parameter Value Unit Notes

Minimum baud rate fCCB/1,048,576 baud 1 , 2

Maximum baud rate fCCB/16 baud 1, 2, 3

Oversample rate 16 — 1, 4

Notes:

1. Guaranteed by desi gn.

2. fCCB ref ers to the internal platf orm clock.

3. Actual att ainable baud rate will be limited by the latency of int errupt processing.

4. The m iddle of a start bit is detected a s the 8th sampled 0 aft er the 1-to-0 t ransi tion of the start bit. Subsequ ent bit val ues are

sampled each 16th sampl e.

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26 Freescale Semiconductor

Enha nced Thr ee- Spe e d Ethernet ( eTSEC)

8 Enhanced Three-Speed Ethernet (eTSEC)

This section provides the AC and DC electrical characteri stics for the enhanced three-speed Ethernet

controller. The el ectrical charac teris tics for MDIO and MDC are specif i ed in Section 9, “Ethernet

Management Inte rface Electri cal Char acteristics.”

8.1 En hanced Three-S peed Ethernet Control ler (eTSEC)

(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RT BI/R MII Electrical

Characteristics

The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media

independent interface (MI I), ten-bit interface (TBI), reduced gigabit media independent interface

(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals

except management data input/output (MDIO) and management data clock (MDC). The RGMII and R TBI

interfaces are defined for 2.5 V, while the GMII, MII, and TBI interfaces can be oper ated at 3.3 or 2. 5 V.

The GMII, MII, or TBI interface timing is compliant with the IEEE 802.3. The RGMII and R TBI interfaces

follow the Reduced Gigabit Media-Independent Inte rface (R GMII) Specification Version 1.3

(12/10/2000). The RM II interface follows the RMII Consortium RMII Spec ific ation Version 1.2

(3/20/1998). The electr ical char acter istics for MDIO and MDC a re specified in Section 9, “Ethernet

Management Inte rface Electri cal Char acteristics.”

8.1.1 eTSEC DC Electrical Characteristics

All GMII, MII, TBI, RGMII, RMII, and RTBI drivers and receivers comply with the DC parametric

attributes specified in Table 22 and Table 23. The RGMII and RTBI signals are based on a 2.5-V CMOS

interface voltage as defined by JEDEC EIA/JESD8-5.

Table 22. GMII, MII, RMII, and TBI DC Electrical Chara cteristics

Parameter Symbol Min Max Unit Notes

Supply voltage 3.3 V LVDD

TVDD

3.13 3.47 V 1, 2

Output hi gh volt age (LVDD/TVDD = min, IOH = –4.0 mA) VOH 2.40 LVDD/TVDD + 0.3 V —

Output low volt age (LVDD/TVDD = min, IOL = 4.0 mA) VOL GND 0.50 V —

Input high volt age VIH 2.0 LVDD/TVDD + 0.3 V —

Input low voltage VIL –0.3 0.90 V —

Input hi gh current (VIN = LVDD, VIN = TVDD)I

IH —40μA 1, 2, 3

Input low current (VIN = GND) IIL –600 — μA—

Notes:

1. LVDD suppor t s eTSECs 1 and 2.

2. TVDD supports eTSECs 3 and 4.

3. The symbol VIN, in this case , represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 27

Enhanced Three-Speed Ethernet (eTSEC)

8.2 FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing

Specifications

The AC timing specif ic at ions for FIFO, GMII, MII, TBI, RGMII , RMII, and RTBI are presen ted in this

section.

8.2.1 FIFO AC Specifications

The basis for the AC s pecifications for the eTSE C’ s FIFO modes is the double data rate RGMII and R T BI

specifications, since they have similar perform ances and are described in a source-synchronous fashi on

like FIF O modes. However, the FIFO i nterface pr ovides deliberate skew between the transmitted data and

source clock in GMII fashion.

When the eTSEC is configured for FIFO modes , all clocks are supplied f rom external sources to the

relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,

while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit

clock to synchronously generate transmit dat a and outputs an echoed copy of the transmit clock back out

onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is

intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a

source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since

the clock is delayed by th e eT SEC to allow acceptable set-up margin at the recei ver. Note that there is

relationship betwe en the maximum FIFO speed and the platfor m speed. For more information s ee

Section 4. 5, “Platform to FIFO R estrictions.”

Table 23. GMII, MII, RMII , TBI, RGMI I, RTBI, and FIFO DC Electrica l Charac te r is t ics

Parameters Symbol Min Max Unit Notes

Supply voltage 2.5 V LVDD/TVDD 2.37 2.63 V 1, 2

Output hi gh volta ge (LV DD/TVDD = Mi n,

IOH = –1.0 mA) VOH 2.00 LVDD/TVDD + 0.3 V —

Output low volt age (LVDD/TVDD = Min,

IOL = 1.0 mA) VOL GND –0.3 0.40 V —

Input high volt age VIH 1.70 LVDD/TVDD + 0.3 V —

Input low voltage VIL –0.3 0.90 V —

Input hi gh current (VIN = LVDD, VIN = TVDD)I

IH —10μA 1, 2, 3

Input low current (VIN = GND) IIL –15 — μA3

Notes:

1. LVDD suppor t s eTSECs 1 and 2.

2. TVDD supports eTSECs 3 and 4.

3. Note that the symbol VIN, in this case, represents the LVIN and TVIN symb ols refere nced in Table 1 and Table 2.

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28 Freescale Semiconductor

Enha nced Thr ee- Spe e d Ethernet ( eTSEC)

A summary of the FIFO AC specif icati ons appear s in Table 24 and Table 25.

Timing diagrams for FI FO appear in Figure 6 and Figure 7.

Figu re 6. FI FO Tr ansm i t AC Timin g D iagr a m

Tabl e 2 4. FIFO Mod e Trans m it AC Tim in g S pec i fication

Parameter/Condition Symbol Min Typ Max Unit

TX_CLK, GTX_CLK clock period tFIT 5.3 8.0 100 ns

TX_CLK, GTX_CLK duty cycle tFITH/tFIT 45 50 55 %

TX_CLK, GTX_CLK peak-to-peak jitter tFITJ ——250ps

Rise time TX_CLK (20%–80%) tFITR — — 0.75 ns

Fall time TX_CLK (80 %– 20% ) tFITF — — 0.75 ns

FIFO data TXD[7 :0] , TX_ER, TX_EN set up ti m e to GTX_CLK tFITDV 2.0 — — ns

GTX_CLK to FIFO data TXD[7:0], T X_ER, TX_EN hol d ti me tFITDX 0.5 — 3.0 ns

Tab le 25. FIFO Mode Rece ive AC Timing Specification

Parameter/Condition Symbol Min Typ Max Unit

RX_CLK clock period tFIR 5.3 8.0 100 ns

RX_CLK duty cycl e tFIRH/tFIR 45 50 55 %

RX_CLK peak-to-peak jit ter tFIRJ ——250ps

Rise time RX_CLK (20%–80%) tFIRR — — 0.75 ns

Fall time RX_CLK (80 %–2 0%) tFIRF — — 0.75 ns

RXD[7:0], RX_DV, RX_ER set up tim e to RX_CLK tFIRDV 1.5 — — ns

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tFIRDX 0.5 — — ns

Note:

1. The minim um c ycle pe riod of the TX_ CLK and RX_CLK is depen dent on the maxim um plat f orm frequenc y of t he spee d bins

the part belongs to as well as the FIFO mode under operati on. Refer to Section 4.5, “Platform to FIFO Restrictions.”

tFIT

FITH

tFITF

TXD[7:0]

TX_EN

GTX_CLK

TX_ER

tFITR

tFITDV tFITDX

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Freescale Semiconductor 29

Enhanced Three-Speed Ethernet (eTSEC)

Figure 7. FIFO Receive AC Ti mi ng Diagram

8.2.2 GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specif ications.

8.2.2.1 GMII Transmit AC Timing Specifications

Table 26 pr ovides the GMII transmit AC timing spec ifications.

Table 26. GM II Trans m it AC Tim ing Specifica tions

Parameter/Condition Symbol1Min Typ Max Unit

GMII data TXD[7:0], TX_ ER, TX_EN set up ti m e tGTKHDV 2.5 — — ns

GTX_CLK to GMII data TXD[7: 0], TX_ER, TX_EN del ay tGTKHDX 0.5 — 5.0 ns

GTX_CLK data clock rise time (20%–80%) tGTXR2——1.0ns

GTX_CLK data clock fall time (80%–20%) tGTXF2——1.0ns

Notes:

1. The symb ols used f or timing specifi cations f ollow t he pattern t(first two letters of functional block)(signa l)(state)(reference)(state) for inputs

and t(first two letters of functional block )(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbol izes GM II t ransmit ti ming

(GT) with respect to the tGTX cloc k refe rence (K) going to the high stat e (H) r ela tiv e to the time dat e inp ut signal s (D) reachi ng

the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit ti ming (GT ) wit h respect to the t GTX clock

reference (K) goi ng to the high st ate (H) relative to t he time date input signals (D) g oing in valid (X) or hold tim e. Note that, in

genera l, the cloc k ref er ence symbol repr ese ntation i s base d on three l etter s repre senti ng the clo c k of a particular functiona l.

F or e xampl e, t he su bscript of tGTX r epresent s the GM II(G) tran smit (TX) cloc k. For rise and fall times, th e latt er con v enti on is

used with the appropriate letter : R (rise) or F (fall).

2. Guaranteed by desi gn.

tFIR

tFIRH tFIRF

tFIRR

RX_CLK

RXD[7:0]

RX_DV

RX_ER Valid Data

tFIRDV tFIRDX

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30 Freescale Semiconductor

Enha nced Thr ee- Spe e d Ethernet ( eTSEC)

Figure 8 shows the GMII transmit AC timing diagra m.

Fi gure 8. GMII Tr ansmi t A C Timi ng Diagr am

8.2.2.2 GMII Receive AC Timing Specifications

Table 27 provid es the GMII receive AC timing specifi cations.

Figure 9 provides the AC test load for eTSEC.

Figure 9. eTSEC AC Test Load

Table 27. GMII Receive AC Timi ng Specifications

Parameter/Condition Symbol1Min Typ Max Unit

RX_CLK clock period tGRX —8.0—ns

RX_CLK duty cycl e tGRXH/tGRX 35 — 75 ns

RXD[7:0], RX_DV, RX_ER set up tim e to RX_CLK tGRDVKH 2.0 — — ns

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tGRDXKH 0——ns

RX_CLK clock ris e (20%-80%) tGRXR2——1.0ns

RX_CLK clock fa ll ti m e (80%-20%) tGRXF2——1.0ns

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

input s a nd t(first t wo letter s of functional b lock) (reference)(state)(sig nal)(state) fo r output s. For e xample, tGRDVKH symbolizes GMII receive

timi ng (GR) wi th respect to the ti me data i nput signals (D) reaching the valid state (V) rel ati ve to the tRX clock refere nce (K)

going to the high state (H) or setup tim e. Also, tGRDXKL symboli zes GMII receive timi ng (GR) wi th r espect to the time data

input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) sta te or hold time. Note that, in

genera l, the cloc k ref er ence symbol repr ese ntation i s base d on three l etter s repre senti ng the clo c k of a particular functiona l.

For example, the subscript of t GRX represents the GMII (G) receive ( RX) clock. For rise and fall times, the latter convention

is used with the appropriat e letter: R (rise) or F (fall).

2. Guaranteed by desi gn.

GTX_CLK

TXD[7:0]

tGTKHDX

tGTX

tGTXH

tGTXR

tGTXF

tGTKHDV

TX_EN

TX_ER

Output Z0 = 50 ΩLVDD/2

RL = 50 Ω

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 31

Enhanced Three-Speed Ethernet (eTSEC)

Figure 10 shows the GMII receive AC timing diagram.

Fi gure 10. GMII Receive AC Timin g Diagram

8.2.3 MII AC Timing Specifications

This section describes the MII transm it and recei ve AC timing specificati ons.

8.2.3.1 MII Transmit AC Timing Specifications

Table 28 provides the MII trans mit AC timing specifications.

Table 28. MII Transmit AC Timing Specifications

Parameter/Condition Symbol1Min Typ Max Unit

TX_CLK clock period 10 Mbps tMTX2—400—ns

TX_CLK clock period 100 Mbps tMTX —40—ns

TX_CLK duty cycle tMTXH/tMTX 35 — 65 %

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN del ay tMTKHDX 1 5 15 ns

TX_CLK data clock rise (20%–80%) tMTXR21.0 — 4.0 ns

TX_CLK data clock fall (80%–20 %) tMTXF21.0 — 4.0 ns

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

inputs and t (f irst t wo letters of functional block)(reference)(state)(signal)(state) for outputs. For e xam ple, tMTKHDX symbolize s MII t ransm it

timi ng (MT) for the ti m e tMTX clock reference (K) going high (H) unti l dat a outputs (D) are invalid (X). Note that, i n general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit ( TX) clock. For rise and fall ti me s, the latter convention is

used with the appropriate letter : R (rise) or F (fall).

2. Guaranteed by desi gn.

RX_CLK

RXD[7:0]

tGRDXKH

tGRX

tGRXH

tGRXR

tGRXF

tGRDVKH

RX_DV

RX_ER

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32 Freescale Semiconductor

Enha nced Thr ee- Spe e d Ethernet ( eTSEC)

Figure 11 shows the M II transmit AC timing diagram.

Figure 11. MII Trans mit AC Tim ing Diagram

8.2.3.2 MII Receive AC Timing Specifications

Table 29 provid es the MII recei ve AC timing specificati ons.

Figure 12 provides the AC test load for eTSEC.

Figure 1 2. eTSEC AC Test Load

Ta ble 29. MII Receive AC Tim ing Specific ations

Parameter/Condition Symbol1Min Typ Max Unit

RX_CLK clock period 10 Mbps tMRX2—400—ns

RX_CLK clock period 100 Mbps tMRX —40—ns

RX_CLK duty cycl e tMRXH/tMRX 35 — 65 %

RXD[3:0], RX_DV, RX_ER set up tim e to RX_CLK tMRDVKH 10.0 — — ns

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns

RX_CLK clock ris e (20%–80%) tMRXR21.0 — 4.0 ns

RX_CLK clock fa ll ti m e (80%–20%) tMRXF21.0 — 4.0 ns

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(refere nce)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes M II recei ve

timi ng (MR) wi th respect to the tim e data input signals (D) reach the valid stat e (V) relative t o the tMRX cloc k refer ence ( K)

going to the high (H) state or setup time. Also , tMRDXKL symbolizes MII receiv e timi ng (GR) with respec t to the time data inpu t

signal s (D) went in valid (X) relat ive t o the tMRX clo ck ref erence (K) going to th e low (L) state or hold time. Note that, i n general,

the clock reference symbol representation is based on three letters r epresenting the clock of a particular functional. For

exam ple , the subs cript of tMRX repr esen ts the MII (M) rec eiv e (RX) cl oc k. F o r rise a nd f al l time s, t he lat ter con vent ion is used

with the appropria te l etter: R (rise) or F (f all).

2. Guaranteed by desi gn.

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

Output Z0 = 50 ΩLVDD/2

RL = 50 Ω

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 33

Enhanced Three-Speed Ethernet (eTSEC)

Figure 13 shows the MII rec eiv e AC timing diagram.

Figure 13. MII Receive AC Tim ing Diagram

8.2.4 T BI AC Timing Specifications

This section describes the TBI transmit and r eceive AC timing specifications.

8.2.4.1 TBI Transmit AC Timing Specifications

Table 30 provid es the TBI trans mit AC timing specifica tions .

Table 30. TBI Transmi t AC Timi ng Spec ifications

Parameter/Condition Symbol1Min Typ Max Unit

TCG[9:0] setup time GTX_CLK going high tTTKHDV 2.0 — — ns

TCG[9:0] hold time f rom GTX_CLK going high tTTKHDX 1.0 — — ns

GTX_CLK rise (20%–80%) tTTXR2——1.0ns

GTX_CLK fall time (80%–20%) tTTXF2——1.0ns

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate )(reference)(state) for

inputs and t(first two letters of functional bl ock)(reference)(state)(si gna l)(state) for outputs. For example, tTTKHDV sy mb oli zes the TBI

transmit timing (TT) with respect to the time from tTTX (K) going hig h (H) until the ref er enc ed da ta signal s (D) reach the v ali d

state (V ) or setu p t ime. Also, tTTKHDX s ymbolize s the TBI trans mit timing (TT) with r espect to the time from tTTX ( K) going high

(H) unti l the referenced d ata signals (D) reach the inval id state (X) or hold time. Note that, i n general, the clock reference

symbol represent ati on is based on three letters representing the clock of a part icular funct ional. F or example, the subsc ript

of tTTX rep resents the TBI (T) transmit (TX) clock. For rise and fal l time s, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. Guaranteed by desi gn.

RX_CLK

RXD[3:0]

tMRDXKL

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER tMRDVKH

Valid Data

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

34 Freescale Semiconductor

Enha nced Thr ee- Spe e d Ethernet ( eTSEC)

Figure 14 shows the TBI trans mit AC timing diagram.

Fi gure 14 . TBI Tr ansmi t AC Timi ng Dia gra m

8.2.4.2 TBI Receive AC Timing Specifications

Table 31 pr ovides the TBI receive AC timing specifications.

Table 31. TBI Receive AC Timing Specifications

Parameter/Condition Symbol1Min Typ Max Unit

TSEC

_RX_CLK[0:1] clock per iod tTRX — 16.0 — ns

TSEC

_RX_CLK[0:1] skew tSKTRX 7.5 — 8.5 ns

TSEC

_RX_CLK[0:1] duty cycle tTRXH/tTRX 40 — 60 %

RC G[9 :0 ] setu p tim e to r is in g TS E C

_RX_CLK tTRDVKH 2.5 — — ns

RCG[9:0] hold time to rising TSEC

_RX_CLK tTRDXKH 1.5 — — ns

TSEC

_RX_CLK[0:1] clock rise time (20% –80%) tTRXR20.7 — 2.4 ns

TSEC

_RX_CLK[0:1] clock fall time (80%–20%) tTRXF20.7 — 2.4 ns

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

inputs and t(first two letters of functional block)(re f erence)(state)(signal)(state) for outputs. For example, tTRDVKH symbol izes TBI receive

timing (TR) with respect to the time data input signals (D) reach the valid stat e (V) relati ve to t he tTRX cloc k refer ence (K)

going to the hi gh (H) stat e or setup time . Also , t TRDXKH sy mbol izes TBI r eceiv e timin g ( TR) with r esp ect t o the t ime data i nput

signals (D) went invalid (X) r elativ e to t he tTRX clock ref ere nce (K) goi ng to the hig h (H) stat e. Note that, i n g eneral , the cl ock

reference sym bol repr esentation is based on three letters representin g the cloc k of a parti cular fun cti onal. For e xample, the

subscript of t TRX represents the TBI (T) receive (RX) clock. For rise and fall ti mes, the latter convention is used with the

appropriate letter : R ( rise) or F (fall). For symbols representing skews, the subscript is skew (SK) foll owed by the clock that

is being skewed (TRX).

2. Guaranteed by desi gn.

GTX_CLK

TCG[9:0]

tTTXR

tTTX

tTTXH

tTTXR

tTTXF

tTTKHDV tTTKHDX

tTTXF

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

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Enhanced Three-Speed Ethernet (eTSEC)

Figure 15 shows the TBI r eceive AC timing diagram.

Figure 1 5. TBI Receive AC Timin g Diagram

8.2.5 TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant

eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1, a 125-MHz TBI receive clock

is supplied on the TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CL K in this mode,

whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied

on the TSE C_GT X_CLK125 pin in all TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appear s in Table 32.

Table 3 2. TBI single-clock Mode Recei ve AC Tim ing Specification

Parameter/Condition Symbol Min Typ Max Unit

RX_CLK clock period tTRRX 7.5 8.0 8.5 ns

RX_CLK duty cycl e tTRRH/TRRX 40 50 60 %

RX_CLK peak-to-peak jit ter tTRRJ ——250ps

Rise time RX_CLK (20%–80%) tTRRR ——1.0ns

Fall time RX_CLK (80 %–2 0%) tTRRF ——1.0ns

RCG[9:0] setup time to RX_CLK rising edge tTRRDVKH 2.0 — — ns

RCG[9:0] hold ti me to RX_CLK rising edge tTRRDXKH 1.0 — — ns

TSEC

_RX_CLK1

RCG[9:0]

tTRX

tTRXH

tTRXR

tTRXF

tTRDVKH

TSEC

_RX_CLK0

tTRDXKH

tTRDVKH

tTRDXKH

tSKTRX

tTRXH

Valid Data Valid Data

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

36 Freescale Semiconductor

Enha nced Thr ee- Spe e d Ethernet ( eTSEC)

A timing diagram for TBI rec ei ve appears in Figure 16.

Figure 16. TBI Single-Clock Mode Receive AC Timing Diagram

8.2.6 RGMII and RTBI AC Timing Specifications

Table 33 pres ents the RGMII and RTBI AC timing spec ifica tions .

Table 33. RGMII and RTBI AC Timing Specif ications

Parameter/Condition Symbol1Min Typ Max Unit

Data to cl ock output skew (at transmitter) tSKRGT5–50060 5006ps

Data to clock in put ske w (at receiver) 2tSKRGT 1.0 — 2.8 ns

Clock pe riod 3tRGT57.2 8.0 8.8 ns

Duty cycle for 10BASE-T and 100BASE-TX3, 4 tRGTH/tRGT545 50 55 %

Rise time (20%–80%) tRGTR5— — 0.75 ns

Fall time (20%–80%) tRGTF5— — 0.75 ns

Notes:

1. In general, the clock reference sym bol representation for this section is based on the symbols RG T to represent RGMII and

RTBI timing. For example, the subscript of tRGT re present s the TBI (T) r ece ive (RX) clo ck. No te also that th e notati on f or rise

(R) and fall (F) times follo ws the cloc k sym bol that is being represented. For sym bols representing skews, the subscrip t is

skew (SK) f ollowed by the clock th at is being skewed (RGT).

2. This impl ies that PC board design wil l r equire clocks to be routed such tha t an addi tional trace dela y of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cyc le ma y be stret ched/shrunk du ring speed chan ges or while transi tioni ng to a rec eived packet's clock do ma ins as long

as the mini mum dut y cycle i s not viol ated and st retchi ng occur s f or no more t han three tRGT of the l o west speed transi t ioned

between.

5. Guaranteed by characterization.

6. In rev 1.0 silicon, due to err ata, tSKRGT is -650 ps (min) and 650 ps (max). Ple ase refer to “eTSEC 10” in the devic e err ata

document.

tTRRX

tTRRH tTRRF

tTRRR

RX_CLK

RCG[9:0] Valid Data

tTRRDXKH

tTRRDVKH

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 37

Enhanced Three-Speed Ethernet (eTSEC)

Figure 17 shows the R GMII and RTBI AC timing and multiplexing diagrams.

Figure 17. RGMII and RTBI A C Timing and Mult iplexing Diagrams

8.2.7 RMII AC Timing Specifications

This section describes the RMII tra nsmit and receive AC timing specifications .

8.2.7.1 RMII Transmit AC Timing Specifications

The RMII transm it AC timing spec ificati ons are in Table 34.

Table 34. RMII Transmit A C Timing Specifications

Parameter/Condition Symbol1Min Typ Max Unit

TSEC

_TX _CLK clock p er iod t RMT 15.0 20.0 25.0 ns

TSEC

_TX_CLK duty cycle tRMTH 35 50 65 %

TSEC

_TX_CLK peak-to-peak jit ter tRMTJ ——250ps

Rise time TSEC

_TX_CLK (20%–80% ) tRMTR 1.0 — 2.0 ns

Fall time TSEC

_TX_CLK (80%–20%) tRMTF 1.0 — 2.0 ns

GTX_CLK

tRGT

tRGTH

tSKRGT

TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitter)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RXD[8:5][3:0]

RXD[7:4][3:0]

RX_CLK

(At PHY)

tSKRGT

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

38 Freescale Semiconductor

Enha nced Thr ee- Spe e d Ethernet ( eTSEC)

Figure 18 shows the R MII transmit AC timing diagram.

Figure 18. RMII Trans mit AC Tim ing Diagram

8.2.7.2 RMII Receive AC Timing Specifications

TSEC

_T X _CLK to RM II d at a TX D[1 :0] , T X _EN d el ay tRMTDX 1.0 — 10.0 ns

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

inputs and t (f irst t wo letters of functional block)(reference)(state)(signal)(state) for outputs. For e xam ple, tMTKHDX symbolize s MII t ransm it

timi ng (MT) for the ti m e tMTX clock reference (K) going high (H) unti l dat a outputs (D) are invalid (X). Note that, i n general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit ( TX) clock. For rise and fall ti me s, the latter convention is

used with the appropriate letter : R (rise) or F (fall).

Ta ble 35. RM I I Receive AC Timi ng Spec ifications

Parameter/Condition Symbol1Min Typ Max Unit

TSEC

_TX _CLK clock p er iod tRMR 15.0 20.0 25.0 ns

TSEC

_TX_CLK duty cycle tRMRH 35 50 65 %

TSEC

_TX_CLK peak-to-peak jit ter tRMRJ ——250ps

Rise time TSEC

_TX_CLK(20%–80%) tRMRR 1.0 — 2.0 ns

Fall time TSEC

_TX_CLK (80%–20%) tRMRF 1.0 — 2.0 ns

RXD[1:0], CRS_DV, RX_ER setu p ti me to REF_CLK rising edge tRMRDV 4.0 — — ns

RXD[1:0], CRS_DV, RX_ER hold ti me to REF_CLK rising edge tRMRDX 2.0 — — ns

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(refere nce)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes M II recei ve

timi ng (MR) wi th respect to the tim e data input signals (D) reach the valid stat e (V) relative t o the tMRX cloc k refer ence ( K)

going to the high (H) state or setup time. Also , tMRDXKL symbolizes MII receiv e timi ng (GR) with respec t to the time data inpu t

signal s (D) went in valid (X) relat ive t o the tMRX clo ck ref erence (K) going to th e low (L) state or hold time. Note that, i n general,

the clock reference symbol representation is based on three letters r epresenting the clock of a particular functional. For

exam ple , the subs cript of tMRX repr esen ts the MII (M) rec eiv e (RX) cl oc k. F o r rise a nd f al l time s, t he lat ter con vent ion is used

with the appropria te l etter: R (rise) or F (f all).

Table 34. RMII Transmit AC Ti ming Specifications (continue d)

Parameter/Condition Symbol1Min Typ Max Unit

TSEC

_TX_CLK

TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TX_EN

TX_ER

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 39

E th ernet Mana g e me nt Int e r fac e E le ct rica l Ch ar a ct e r ist i cs

Figure 19 provides the AC test load for eTSEC.

Figure 1 9. eTSEC AC Test Load

Figure 20 shows the RMII receive AC timing diagra m.

Figure 20. RMII Receive AC T iming Diagram

9 Ethernet Management Interface Electrical

Characteristics

The electrical char acter i stics specified here apply to MII management interf ace si gnals MDIO

(managem ent data input/output) and MDC (manageme nt data clock). The electr i cal char act er isti cs for

GMII, RGMII, RMII, TBI, and RTBI are specified in “Section 8, “Enhanced Three-Speed Ethernet

(eTSEC).”

9.1 MII Managemen t DC Electrical Cha racteristi cs

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical charact eristics

for MDIO and MDC are provided in Table 36.

Ta ble 36. MII Manag em ent DC Electrical Charac te ristics

Parameter Symbol Min Max Unit

Supply voltage (3. 3 V) OVDD 3.13 3.47 V

Output hi gh volta ge (OVDD = Min, IOH = –1.0 m A ) VOH 2.10 OVDD + 0.3 V

Output low volt age (OVDD =Min, IOL = 1.0 mA) VOL GND 0.50 V

Input high volt age VIH 2.0 — V

Input low voltage VIL —0.90V

Output Z0 = 50 ΩLVDD/2

RL = 50 Ω

TSEC

_TX_CLK

RXD[1:0]

tRMRDX

tRMR

tRMRH

tRMRR

tRMRF

CRS_DV

RX_ER tRMRDV

Valid Data

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

40 Freescale Semiconductor

Ethernet Management Int erface Electrical Characteristics

9.2 MII Management AC Ele c t rical S pecifications

Table 37 provid es the MII management AC timing specifi cations.

Input hi gh current (OVDD = Max, VIN1 = 2 .1 V) IIH —40μA

Input low current (OVDD = Max, VIN = 0.5 V) IIL –600 — μA

Note:

1. Note that the symbol VIN, i n thi s case, repr esents the OVIN symbol refer enced in Table 1 and Table 2.

Table 37. MII Management A C Timing Specifications

At r ecommended operating conditions with OVDD is 3.3 V ± 5%.

Parameter Symbol1Min Typ Max Unit Notes

MDC frequency fMDC 0 .7 2 2.5 8.3 MH z 2, 3, 4

MDC period tMDC 120.5 — 1389 ns —

MDC clock pulse width high tMDCH 32 — — ns —

MDC to MDIO valid tMDKHDV 16 × tCCB ——ns5

MDC to MDIO d e la y tMDKHDX (16 × tptb_clk × 8) – 3 — (16 × tptb_clk × 8) + 3 ns 5

MDIO to MDC setup time tMDDVKH 5——ns—

MDIO to MDC hold time tMDDXKH 0——ns—

MDC rise ti me tMDCR ——10ns4

MDC fall time tMDHF —10ns4

Notes:

1. The sym bols used f or timing specifications follow t he pattern of t(first two letters of functional blo ck)(signal)(state)(reference)(state) fo r

inpu ts and t(first two l etters of fun ctional bloc k)(ref erence)(state)(signal)(state) f or outputs. For example, tMDKHDX symboli zes manage ment

data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) ar e inval id (X) or data hold time.

Also, tMDDVKH symboli zes man agement data t iming (MD) with respect to the time data inpu t signals (D) reach the val id state

(V ) rel ativ e to the tMDC clock refer ence (K) goi ng to the h igh (H) st ate or set up time. F or rise and fal l times , the latter c onvent ion

is used wit h the appropriate letter: R (rise) or F (fall).

2. This pa rame ter is dependent on the eTSEC system clock speed, which is hal f of the Pla tform F requency (fCCB). Th e a ctual

ECn_M DC output cloc k fr equency for a speci fic eTSEC port can be programmed b y configuring the MgmtClk bit field of

MPC85 48E’s MIIMCFG r egister , based on the platform (CCB) clock run ning for the de vice . The f ormula i s: Platform F requ ency

(CCB) ÷(2 × Frequency Divider determined by MIICFG[MgmtClk] encoding sele cti on). For example, if

MIICFG[MgmtClk] = 000 and the pl atform (CCB) is cur rent ly running at 533 MHz, fMDC = 533) ÷(2 × 4 × 8) = 533) ÷64 =

8.3 MHz. That i s, fo r a syste m runni ng at a pa rticul ar pl atform frequenc y ( fCCB), the ECn_MDC o utp ut cl ock f requenc y c an be

programmed between maximum fMDC = fCCB ÷64 and minimum fMDC = fCCB ÷448. Re fer to M PC8572E reference manual’s

MIIMCFG register section for more detai l.3.The maximum ECn_MDC output cl ock frequency is defined based on the

max imum platf orm frequenc y f or MP C8548E ( 533 MHz ) divided b y 64, whi le the mi nim um ECn_MDC out put cl ock f requenc y

is def ined based on the minim um platform frequency for MPC8548E (333 MHz) divided by 448, following the formula

de scri bed in No te 2 above.

4. Guaranteed by design.

5. tCCB is the plat form (CCB) clock period.

Ta ble 36. MII Manag em en t DC Electrical Charac teristics (continued)

Parameter Symbol Min Max Unit

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 41

Local Bus

Figure 21 shows the MII management AC timing diagram.

Figure 21. MII Management Interface Timing Diagram

10 Lo cal Bus

This section descr ibes t he DC and AC electrical speci f icat ions for the local bus interf ace of the

MPC8548E.

10.1 Local Bus DC Ele ctrical Char acteristics

Table 38 provides the DC elect rical characteristics for the local bus interface operating at BVDD =

3.3 V DC.

Table 38. Local Bus DC E lectrical Characteristic s (3.3 V DC)

Parameter Symbol Min Max Unit

High-level input voltage VIH 2BV

DD + 0.3 V

Low-l evel input voltage VIL –0.3 0.8 V

Input cur rent (VIN1 = 0 V or VIN = BVDD)I

IN —±5 μA

High-level output voltage (BVDD = min, I OH = –2 mA) VOH 2.4 — V

Low-lev el output voltage (BVDD = m in, IOL = 2 mA) VOL —0.4V

Note:

1. Note that the symbol VIN, in thi s case, represents the BVIN symbol referenced in Table 1 and Table 2.

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

42 Freescale Semiconductor

Local Bus

Table 39 provides the DC elect rical characteristics for the local bus interface operating at

BVDD =2.5VDC.

10.2 Local Bus AC Elect rical Specifications

Table 40 describes the timing parameters of the local bus interface at BVDD = 3.3 V. For information about

the frequency range of local bus, see Section 19.1, “Clock Ranges.”

Table 39. Local Bus DC E lectrical Characteristic s (2.5 V DC)

Parameter Symbol Min Max Unit

High-level input voltage VIH 1.70 BVDD + 0.3 V

Low-l evel input voltage VIL –0.3 0.7 V

Input cur rent (VIN1 = 0 V or VIN = BVDD)I

IH —10μA

IIL –15

High-level output voltage (BVDD = min, I OH = –1 mA) VOH 2.0 — V

Low-lev el output voltage (BVDD = m in, IOL = 1 mA) VOL —0.4V

Note:

1. Note that the symbol VIN, in thi s case, represents the BVIN symbol referenced in Table 1 and Table 2.

Tab le 40. Local Bus Timi ng Pa ram eters (BVDD = 3.3 V)—P LL Enabled

Parameter Symbol1Min Max Unit Notes

Loca l bus cycle t ime tLBK 7.5 12 ns 2

Local bus duty cycl e tLBKH/tLBK 43 57 % —

LCLK[n] sk ew to LCLK[m] or LSYNC_OUT tLBKSKEW — 150 ps 7, 8

Input set up to local bus cl ock (except LGTA/LUPWAIT) tLBIVKH1 1. 8 — ns 3, 4

LGTA/LUPWAIT input setup to l ocal bus clock tLBIVKH2 1.7 — ns 3, 4

Input hol d from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 1.0 — ns 3 , 4

LGTA/LUPWAIT input hold from local bus clock tLBIXKH2 1. 0 — ns 3, 4

LALE output transiti on to LAD/LDP output t ransi tion (LATCH hold tim e) tLBOTOT 1.5 — ns 6

Local bus cloc k to output valid (except LAD/LDP and LALE) tLBKHOV1 —2.0ns—

Local bus cloc k to da ta valid for LAD/LDP tLBKHOV2 —2.2ns3

Local bus clock to address valid for LAD tLBKHOV3 —2.3ns3

Local bus clock to LALE assertion tLBKHOV4 —2.3ns3

Output hol d from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.7 — ns 3

Output hol d from local bus clock for LAD/LDP tLBKHOX2 0.7 — ns 3

Local bus cloc k to output high Impedance (except LAD/LDP and LALE) tLBKHOZ1 —2.5ns5

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 43

Local Bus

Table 41 descr ibes the timing parameters of the local bus interface at BVDD = 2.5 V.

Local bus cloc k to output high impedance for LAD/LDP tLBKHOZ2 —2.5ns5

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

inputs and t(first two letters of functional bl ock)(reference)(state)(si gna l)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timi ng (LB) f or t he input (I) to go in v ali d (X) with re spec t to the time t he tLBK cloc k ref erenc e (K) goes high ( H), in t his case f or

clock one (1). Also, tLBKHOX symbolizes loc al bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to

the output ( O) going invalid (X) or out put hold time.

2. All timings are in ref erence to LSYNC_IN for PLL enabl ed and internal l ocal bus cl ock for PLL bypass mode .

3. All signals are measure d fro m BVDD/2 of the rising edge of LSYNC_ IN for PLL enab led or internal local bus cloc k for PLL

bypass mode to 0.4 ×BVDD of the signal in question for 3.3-V signaling lev els.

4. Input t imings are measur ed at t he pin.

5. For pu rposes of ac ti ve/float timing measurements, the Hi-Z or off st ate is def ined to be when the total curr ent delivered

through the component pin is less than or equal to the leakage current specificati on.

6. tLBOTOT is a measurement of t he minimum time between the negation of LALE and any change in LAD. tLBOTOT is

progr am med wit h the LBCR[AHD] parame ter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[

]. Skew measur ed between

complementar y si gnals at BVDD/2.

8. Guaranteed by desi gn.

Tab le 41. Local Bus Timi ng Pa ram eters (BVDD = 2.5 V)—P LL Enabled

Parameter Symbol1Min Max Unit Notes

Loca l bus cycle t ime tLBK 7.5 12 ns 2

Local bus duty cycl e tLBKH/tLBK 43 57 % —

LCLK[n] sk ew to LCLK[m] or LSYNC_OUT tLBKSKEW — 150 ps 7, 8

Input set up to local bus cl ock (except LGTA/UPWAIT) tLBIVKH1 1.9 — ns 3, 4

LGTA/LUPWAIT input setup to l ocal bus clock tLBIVKH2 1.8 — ns 3, 4

Input hol d from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 1.1 — ns 3 , 4

LGTA/LUPWAIT input hold from local bus clock tLBIXKH2 1. 1 — ns 3, 4

LALE output transiti on to LAD/LDP output t ransi tion (LATCH hold tim e) tLBOTOT 1.5 — ns 6

Local bus cloc k to output valid (except LAD/LDP and LALE) tLBKHOV1 —2.1ns—

Local bus cloc k to da ta valid for LAD/LDP tLBKHOV2 —2.3ns3

Local bus clock to address valid for LAD tLBKHOV3 —2.4ns3

Local bus clock to LALE assertion tLBKHOV4 —2.4ns3

Output hol d from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.8 — ns 3

Output hol d from local bus clock for LAD/LDP tLBKHOX2 0.8 — ns 3

Ta ble 40. L ocal Bus Timing Parameters (BVDD = 3.3 V)—PLL Enabled (continued)

Parameter Symbol1Min Max Unit Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

44 Freescale Semiconductor

Local Bus

Figure 22 provides the AC test load for the local bus.

Figure 22. Local Bus AC Test Load

NOTE

PLL bypass mode is required when LBIU frequency is at or below 83 MHz.

When LBIU operates above 83 MH z, LBIU PLL is recommended to be

enabled.

Local bus cloc k to output high Impedance (except LAD/LDP and LALE) tLBKHOZ1 —2.6ns5

Local bus cloc k to output high impedance for LAD/LDP tLBKHOZ2 —2.6ns5

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

inputs and t(first two letters of functional bl ock)(reference)(state)(si gna l)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timi ng (LB) f or t he input (I) to go in v ali d (X) with re spec t to the time t he tLBK cloc k ref erenc e (K) goes high ( H), in t his case f or

clock one (1). Also, tLBKHOX symbolizes loc al bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to

the output ( O) going invalid (X) or out put hold time.

2. All timings are in ref erence to LSYNC_IN for PLL enabl ed and internal l ocal bus cl ock for PLL bypass mode .

3. All signals are measure d fro m BVDD/2 of the rising edge of LSYNC_ IN for PLL enab led or internal local bus cloc k for PLL

bypass mode to 0.4 ×BVDD of the signal in questi on for 3. 3-V signaling level s.

4. Input t imings are measur ed at t he pin.

5. For pu rposes of ac ti ve/float timing measurements, the Hi-Z or off st ate is def ined to be when the total curr ent delivered

through the component pin is less than or equal to the leakage current specificati on.

6. tLBOTOT is a measurement of t he minimum time between the negation of LALE and any change in LAD. tLBOTOT is

progr am med wit h the LBCR[AHD] parame ter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementar y si gnals at BVDD/2.

8. Guaranteed by desi gn.

Ta ble 41. L ocal Bus Timing Parameters (BVDD = 2.5 V)—PLL Enabled (continued)

Parameter Symbol1Min Max Unit Notes

Output Z0 = 50 ΩBVDD/2

RL = 50 Ω

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 45

Local Bus

Figure 23 through Figure 28 show the local bus signals.

Figure 23. Local Bus Signals (PLL Enabl ed)

Table 42 descr ibes the timing parameters of the local bus interface at BVDD = 3.3 V with PLL disabled.

Table 42. Local Bus Timing Parameters—PLL Bypassed

Parameter Symbol1Min Max Unit Notes

Loca l bus cycle t ime tLBK 12 — ns 2

Local bus duty cycl e tLBKH/tLBK 43 57 % —

Internal launch/capture clock to LCLK delay tLBKHKT 2.3 4.4 ns 8

Input set up to local bus cl ock (except LGTA/LUPWAIT) tLBIVKH1 6. 2 — ns 4, 5

LGTA/LUPWAIT input setup to l ocal bus clock tLBIVKL2 6.1 — ns 4, 5

Input hol d from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 –1.8 — ns 4 , 5

LGTA/LUPWAIT input hold from local bus clock t LBIXKL2 –1.3 — ns 4, 5

LALE output transiti on to LAD/LDP output t ransi tion (LATCH hold tim e) tLBOTOT 1.5 — ns 6

Local bus cloc k to output valid (except LAD/LDP and LALE) tLBKLOV1 — –0.3 ns —

Local bus cloc k to da ta valid for LAD/LDP tLBKLOV2 — –0.1 ns 4

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKHOV1

tLBKHOV2

tLBKHOV3

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Output ( Da ta) Signals:

LAD[0:31]/LDP[0:3]

Output (Address ) Si gnal:

LAD[0:31]

LALE

tLBIXKH1

tLBIVKH1

tLBIVKH2 tLBIXKH2

tLBKHOX1

tLBKHOZ1

tLBKHOX2

tLBKHOZ2

Input Signal:

LGTA

tLBOTOT

tLBKHOZ2

tLBKHOX2

tLBKHOV4

LUPWAIT

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

46 Freescale Semiconductor

Local Bus

Local bus clock to address valid for LAD tLBKLOV3 —0ns4

Local bus clock to LALE assertion tLBKLOV4 —0ns4

Output hol d from local bus clock (except LAD/LDP and LALE) tLBKLOX1 –3.7 — ns 4

Output hol d from local bus clock for LAD/LDP tLBKLOX2 –3.7 — ns 4

Local bus cloc k to output high Impedance (except LAD/LDP and LALE) tLBKLOZ1 —0.2ns7

Local bus cloc k to output high impedance for LAD/LDP tLBKLOZ2 —0.2ns7

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

inputs and t(first two letters of functional bl ock)(reference)(state)(si gna l)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timi ng (LB) f or t he input (I) to go in v ali d (X) with re spec t to the time t he tLBK cloc k ref erenc e (K) goes high ( H), in t his case f or

clock one (1). Also, tLBKHOX symbolizes loc al bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to

the output ( O) going invalid (X) or out put hold time.

2. All timings are in reference to local bus clock for PLL bypass mode. Tim ings may be negative with respect to the local bus

cloc k bec ause the ac tual l aunch and c apt ure of si gnals i s done wit h the i nternal launc h/capt ure c loc k, which precedes LCLK

by tLBKHKT.

3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[

]. Skew measur ed between

complementar y si gnals at BVDD/2.

4. All s ignals are measured fr om BVDD/2 of the rising e dge of local bus clock for PLL bypass mode to 0.4 × BVDD of the signal

in question for 3.3-V signaling levels.

5. Input t imings are measur ed at t he pin.

6. The value of tLBOTOT is the meas urement of the m ini m um ti m e between the negation of LALE and any chan ge in LAD.

7. For pu rposes of ac ti ve/float timing measurements, the Hi-Z or off st ate is def ined to be when the total curr ent delivered

through the component pin is less than or equal to the leakage current specificati on.

8. Guaranteed by characterization.

9. Guaranteed by desi gn.

Table 42. Local Bus Timing Parameter s—PLL Bypassed (continued)

Parameter Symbol1Min Max Unit Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 47

Local Bus

Figure 24. Local Bus Signals (PLL Bypass Mo de)

NOTE

In PL L bypass mode, LCLK[n] is the inverted version of the internal clock

with the delay of tLBKHKT. In this mode, signals are launched at the rising edge

of the internal clock and are captured at falling edge of th e internal clock

with the exception of LGTA/LUPWAIT (which is captured on the rising

edge of the internal clock).

Output Signal s:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3] tLBKLOV2

LCLK[

]

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Dat a) Signals:

LAD[0:31]/LDP[0:3]

LALE

tLBIXKH1

Input Signal:

LGTA

Output (Address) Signal :

LAD[0:31]

tLBIVKH1

tLBIXKL2

tLBIVKL2

tLBKLOX1

tLBKLOZ2

tLBOTOT

Internal Launch/Capture Clock

tLBKLOX2

tLBKLOV1

tLBKLOV3

tLBKLOZ1

tLBKHKT

tLBKLOV4

LUPWAIT

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

48 Freescale Semiconductor

Local Bus

Figure 25. Lo cal Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enabled)

LSYNC_IN

UPM Mode Input Signal:

LUPWAIT

tLBIXKH2

tLBIVKH2

tLBIVKH1

tLBIXKH1

tLBKHOZ1

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signal s:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

tLBKHOV1

tLBKHOV1 tLBKHOZ1

GPCM Mode Inpu t Si gnal:

LGTA

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 49

Local Bus

Figure 26. Local Bus Signals, G PCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)

tLBIVKH1

tLBIXKL2

Internal Launch/Capture Clock

UPM Mode In put Si gnal:

LUPWAIT

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Outpu t Sig nals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Sig nals:

LCS[0:7]/LWE

tLBKLOV1

tLBKLOZ1

LCLK

tLBKLOX1

tLBIXKH1

GPCM Mode Input Signal:

LGTA tLBIVKL2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

50 Freescale Semiconductor

Local Bus

Figure 27. Local Bus Signals, GP CM/U PM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Enabl ed)

LSYNC_IN

UPM Mode Input Si gnal:

LUPWAIT

tLBIXKH2

tLBIVKH2

tLBIVKH1

tLBIXKH1

tLBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

tLBKHOV1

tLBKHOV1 tLBKHOZ1

Input Signals:

LAD[0:31]/LDP[0:3]

GPCM Mode Inp ut Si gnal:

LGTA

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 51

Programmable Interrupt Controller

Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Byp ass Mode)

11 Programmable Interrupt Controller

In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed

polarity), it must remain the assertion for at leas t 3 syste m clocks (SYSCLK periods).

12 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG ) interface of

the MPC8548E.

tLBIXKL2

tLBIVKH1

Internal Launch/Capture Clock

UPM Mode Input Si gnal:

LUPWAIT

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

Input Signals:

LAD[0:31]/LDP[0:3]

LCLK

tLBKLOV1

tLBKLOZ1

tLBKLOX1

tLBIXKH1

GPCM Mode Input Signal:

LGTA tLBIVKL2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

52 Freescale Semiconductor

JTAG

12.1 JTAG DC Electrical Characteristics

Table 43 provides the DC elect rical characteristics for the JTAG interface.

12.2 JTAG AC Electrical S p ecifications

Table 44 pr ovides the JTAG AC timing specifications as defined in Figure 30 through Figure 32.

Table 43. JTAG DC Electrical Characteri sti cs

Parameter Symbol1Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-l evel input voltage VIL –0.3 0.8 V

Input cur rent (VIN1 = 0 V or VIN = VDD)I

IN —±5μA

High-level output voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V

Low-lev el output voltage (OVDD = min, IOL = 2 mA) V OL —0.4V

Note:

1. Note that the symbol VIN, in this case, represents the OVIN.

Table 44. JTAG AC Ti min g Specifications (Indep end ent of SYSCLK )1

Parameter Symbol2Min Max Unit Notes

JTAG external clock freque ncy of operation fJTG 0 33.3 MHz —

JTAG external clock cycle time t JTG 30 — ns —

JTAG external clock pul se width measured at 1.4 V tJTKHKL 15 — ns —

JTAG external clock rise and fall times tJTGR & tJTGF 02ns6

TRST assert ti m e tTRST 25 — ns 3

Input set up times: Boundary -scan data

TMS , TDI tJTDVKH

tJTIVKH

0—

—

ns 4

Input hol d ti m es: Boundary-scan data

TMS , TDI tJTDXKH

tJTIXKH

25 —

—

ns 4

Valid times: Boundary-scan data

TDO tJTKLDV

tJTKLOV

420

ns 5

Output hold times: Boundary-scan data

TDO tJTKLDX

tJTKLOX

30 —

—

ns 5

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 53

JTAG

Figure 29 provides the AC test load for TDO and the boundary-scan outputs.

Figur e 29 . AC Test L oad for the JTAG Interface

Figure 30 provides the JTAG clock input timing diagram.

Figure 30. JTAG Clock Input Timing Diagram

Figure 31 provides the TRST timing diagra m.

Fi gure 31 . TRST Timi ng Di ag ram

JTAG external clock to output high impedance:

Boundary-scan data

TDO tJTKLDZ

tJTKLOZ

319

ns 5, 6

Notes:

1. All o utputs are meas ured from t he midpoin t v ol tage of the fall ing/risi ng edge of tTCLK to t he midpoi nt of t he si gnal i n qu estio n.

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 29).

Time-of-flight delays must be added for trace lengt hs, vias, and connectors in the system.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

inputs and t (f irst t wo letters of functio nal block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH sym bo liz es JTAG de vice

timi ng (JT) with respect to the time data input signals (D) reaching the valid state (V) r elative to the tJTG clock referen ce (K)

going t o the high (H) state or setup tim e. Also , tJTDXKH symbolizes JTA G timing (JT ) with respect to the time d ata input s ignals

(D) went invalid (X) relative to the tJTG cloc k ref erence (K) going t o the hig h (H) stat e. Note t hat, in general, th e clock refer ence

symbol represent ati on is b ased on three letter s represent ing the clock of a particular functional. For rise and fall times, the

latter convention is used with the appropriate letter : R (rise) or F (fall).

3. TRST is an asynchronous leve l sensitive signal. The setup time is for test purposes only.

4. Non-JTA G signal input timing with re spect to tTCLK.

5. Non-JTA G signal output timing with respect to tTCLK.

6. Guaranteed by desi gn.

Table 44. JTAG AC Timing Speci fications (Independ ent of SYSCLK )1 (c ontinue d)

Parameter Symbol2Min Max Unit Notes

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

JTAG

tJTKHKL tJTGR

External Clock VMVMVM

tJTG tJTGF

VM = Midpoint Voltage (OVDD/2)

TRST

VM = Midpoint Voltage (OVDD/2)

VM VM

tTRST

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

54 Freescale Semiconductor

I2C

Figure 32 provides the boundary-scan timing diagram.

Figu re 32. Bound ary-Scan Ti m in g Diagram

13 I2C

This section describes the DC and AC electrical ch aracteristics for the I2C interfaces of the MPC8548E.

13.1 I2C DC Electrical Characteristics

Table 45 provides the DC elect rical characteristics for the I2C interfaces.

Table 45. I2C DC Electrical Chara cterist ics

Parameter Symbol Min Max Unit Notes

Input high volt age level VIH 0.7 × OVDD OVDD +0.3 V —

Input low voltage level VIL –0.3 0.3 × OVDD V—

Low level output voltage VOL 00.2 × OVDD V1

Pulse width of spikes which mu st be sup pressed by th e

input filter tI2KHKL 050ns2

Input current each I/O pin (input volt age is between

0.1 ×OVDD and 0.9 × OVDD(max) II–10 10 μA3

Capacitance for each I/O pin CI—10pF—

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Ref er to the

MPC8548E

P owe rQUICC™ III Integrated Processor F amily Ref erence Manual

, f or inf ormation on the digi tal filt er

used.

3. I/O pins will obstr uct the SDA and SCL lines if OVDD is switched off.

VM = Midpoint Voltage (OV

DD/2)

VM VM

JTDVKH

JTDXKH

Boundary

Da ta Ou tp u ts

Boundary

Da ta Ou tp u ts

JTAG

External Clock

Boundary

Data Inputs

Output Data Valid

JTKLDX

JTKLDZ

JTKLDV

Input

Data Valid

Outp ut Data Valid

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 55

I2C

13.2 I2C AC Electrical Specificatio ns

Table 46 provid es the AC timing parameters for the I2C interf aces .

Ta ble 46. I2C AC Electri cal Specifications

Parameter Symbol1Min Max Unit Notes

SCL clock frequency fI2C 0400kHz—

Low period of the SCL clock tI2CL 1.3 — μs4

High pe riod o f the S C L cl o ck tI2CH 0.6 — μs4

Setup time for a repeated START condition tI2SVKH 0.6 — μs4

Hold time (repeated) START condition (after this period,

the fi rst clock pulse is gener ated) tI2SXKL 0.6 — μs4

Data setup time tI2DVKH 100 — ns 4

Data input hold time: CBUS compatib le masters

I2C bus devices

tI2DXKL —

0—

—

μs2

Data output delay time: tI2OVKL —0.9—3

Set-up time for STOP condition tI2PVKH 0.6 — μs—

Bus free time between a STOP and START condition tI2KHDX 1.3 — μs—

Noise mar gin at the LOW le vel f or e ach connected device

(incl uding hysteresis) VNL 0.1 × OVDD —V—

Noise margi n at the HIGH lev el for each connected

device (including hysteresis) VNH 0.2 × OVDD —V—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional bloc k)(sign al)(s tate)(reference)(state) for

input s an d t(first two letters of functional b loc k)(ref erence)(state)(signal)(state) fo r outputs. F or exampl e, tI2DVKH symbolizes I2C timi ng (I2)

with r espect t o the t ime dat a inpu t signal s (D ) rea ch the v alid state ( V) rel ativ e t o t he tI2C cloc k r ef er ence (K) going to the hi gh

(H) state or setup time. Al so, tI2SXKL symb oliz es I2C timing (I 2) for the tim e that the data with respect to the start condition

(S) went inval id (X) rel ativ e to t he tI2C cloc k ref erenc e (K) goi ng to the low (L) stat e or hold t ime. Also , tI2PVKH symbol iz es I2C

timi ng (I2) f or t he time tha t the data with respect t o the stop con dition (P) reachi ng the va lid st ate (V ) relati ve to the tI2C cl oc k

ref erence (K) going t o the high (H) stat e or setup time. F or rise and fa ll t imes , the l atter convent ion is u sed with t he appropriate

letter: R (rise) or F (fall).

2. As a transmi tter , the M PC8548E provi des a delay time of at least 300 ns f or the SDA si gnal (refer to the VIH(min ) of the SCL

signal ) to bridg e the undefined regi on of the falling edge of SCL to a void uni ntended gener ation of Start or Stop condition.

When MPC8548E acts as the I2C bus master whil e transmitting, MPC8548E driv es both SCL and SDA. As long as the load

on SCL and SDA ar e balanced, MPC8548E would not cause unintended generation of Star t or Stop condition. Therefor e,

the 300 ns SD A output del ay t ime is not a concern. If , unde r s ome rare con dition, the 300 ns SDA ou tput dela y time is requi red

for MPC8548E as tra nsm itter, the follow ing setting i s recommended fo r the FDR bit fiel d of the I2CFDR register to ensure

both t he desir ed I2C SCL cl ock f requency and SDA output del ay time ar e ac hie v ed, ass umin g that t he desi red I2C SCL clock

frequency is 400 kHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is p rogrammed wit h it s defaul t set ting of

0x10 (decimal 16):

I2C source clock frequency 333 MHz 266 MHz 200 MHz 133 MHz

FDR bit setting 0x2A 0x05 0x26 0x00

Actual FDR divi der selected 89 6 704 512 384

Actual I2C SCL frequency generated 371 kHz 378 kHz 390 kHz 346 kHz

For the detail of I2C frequency calculation, refer to Freescale Application No te AN2919,

Determining the I2C Frequency

Divider Rat io for SCL

. Note that the I2C source clock frequency is hal f of the CCB cl ock frequen cy for MPC8548E.

3. The maximum tI2DXKL has onl y to be met if the d evice does not stretch the LOW period (tI2CL) of the SCL si gnal.

4. Guaranteed by desi gn.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

56 Freescale Semiconductor

PCI/PCI-X

Figure 29 provides the AC test load for the I2C.

Figu re 33. I 2C AC Test Load

Figure 34 shows the AC timing diagram for the I2C bus.

Figure 34. I2C Bus AC Timing Diagram

14 PCI/PCI-X

This section describes the DC and AC electrical specifications for the PCI/PCI-X bus of t he MPC8548E.

Note that the maximum PCI-X fr equency in synchronous mode is 110 MHz.

14.1 PCI/PCI-X DC Electrical Characteristics

Table 47 provides the DC elect rical characteristics for the PCI/PCI-X interface.

Table 47. PCI /P CI-X DC El ectrical Characteristics1

Parameter Symbol Min Max Unit Notes

High-level input voltage VIH 2OV

DD + 0.3 V —

Low-l evel input voltage VIL –0.3 0.8 V —

Input cur rent (VIN = 0 V or VIN = VDD)I

IN —±5 μA2

High-level output voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V —

Low-lev el output voltage (OVDD = min, IOL = 2 mA) VOL —0.4V—

Notes:

1. Ranges listed do not meet the full range of the DC specifications of the

PCI 2.2 Local Bus Specifications

2. Note that the symbol VIN, in this case, repr esents the OVIN symbol refer enced in Table 1 and Table 2.

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

SrS

SDA

SCL

tI2CF

tI2SXKL

tI2CL

tI2CH

tI2DXKL,tI2OVKL

tI2DVKH tI2SXKL

tI2SVKH

tI2KHKL

tI2PVKH

tI2CR

tI2CF

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 57

PCI/PCI-X

14.2 PCI/PCI-X AC Electrical Specifications

This section des cribes the general AC timing parameters of the PCI/PCI-X bus. Note that the clock

reference CLK is represented by SYSCLK when the PCI controller is configur ed for as ynchronous mode

and by PCIn_CLK when it is configured for asynchronous mode.

Table 48 provid es the PCI AC timing specifications at 66 MHz.

Figure 35 provides the AC test load for PCI and PCI-X.

Figure 35. PCI/P CI-X AC Test Load

Table 48. PCI AC Timing Specifications at 66 MHz

Parameter Symbol1Min Max Unit Notes

CLK to output val id tPCKHOV — 6.0 ns 2, 3

Output hol d fr om CLK tPCKHOX 2.0 — ns 2, 10

CLK to output high impedance tPCKHOZ — 14 ns 2, 4, 1 1

Input set up to CLK tPCIVKH 3. 0 — ns 2, 5, 10

Input hold from CLK tPCIXKH 0 — ns 2, 5, 1 0

REQ64 to HRESET 9 setup time tPCRVRH 10 × tSYS — clocks 6, 7 , 11

HRESET to REQ 6 4 hold t ime tPCRHRX 050ns7, 11

HRESET high to first FRAME assertion tPCRHFV 10 — clocks 8, 11

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(s tate)(reference)(state) for

inputs and t(first two letters of functional bl ock)(reference)(state)(si gna l)(state) for outputs. For example, tPCIVKH symbolizes PCI/PCI-X

timing (PC) with respe ct to the time the input signa ls (I) reach the v alid state (V) rela tiv e to the SYSCLK cloc k, tSYS, ref erence

(K) going to the high (H) stat e or setup time. Also, tPCRHFV sym b o li ze s P C I/ P C I-X ti m in g (P C) w ith re s pe c t to th e ti m e hard

reset ( R) went high (H) rela ti ve to the frame signal (F) going to th e valid (V) state.

2. See the ti ming m easurement condi tions in the

PCI 2.2 Local Bus Specifications

3. All PCI si gnals are measu red from OVDD/2 of the risi ng edge of SYSCLK or PCI_CLK

to 0.4 × OVDD of the signal in qu estion

for 3.3-V PCI signaling levels.

4. For pu rposes of ac ti ve/float timing measurements, the Hi-Z or off st ate is def ined to be when the total curr ent delivered

through the component pin is less than or equal to the leakage current specificati on.

5. Input t imings are measur ed at t he pin.

6. The timing param eter tSYS indicat es the minimum and maximum CLK cycle ti m es for the various specif ied frequ encies. The

system clock period must be kept within the minimum and maxim um defined r anges. For values see Section 19, “Clocking.”

7. The setup and hol d time is with respect to the rising edge of HRESET.

8. The timi ng parameter tPCRHFV is a mini mu m of 10 clocks r ather than the minimum of 5 clocks in the

PCI 2.2 Local Bus

Specifications

9. The reset assertion ti ming requirement for HRESET is 100 μs.

10.Guaranteed by char acterizati on.

11.Guaranteed by design.

Output Z0 = 50 ΩLVDD/2

RL = 50 Ω

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

58 Freescale Semiconductor

PCI/PCI-X

Figure 36 shows the PCI/PCI-X input AC timing conditions.

Figure 36. PCI/PCI-X Input AC Timing Measurement Conditions

Figure 37 shows the PCI /PCI-X output AC timing conditions.

Figure 3 7 . PC I/ P C I-X Output AC Tim in g Measurem e nt C ondit io n

Table 49 provid es the PCI-X AC timing specifications at 66 MHz.

Table 49. PCI-X AC Timing Specifications at 66 MHz

Parameter Symbol Min Max Unit Notes

SYSCLK to signal valid delay tPCKHOV — 3.8 ns 1, 2, 3, 7, 8

Output hold fr om SYSCLK tPCKHOX 0.7 — ns 1, 10

SYSCLK to output high impedance tPCKHOZ — 7 ns 1, 4, 8, 11

Input se tup t ime to SYSCLK tPCIVKH 1.7 — ns 3, 5

Input hold ti me fr om SYSCLK tPCIXKH 0.5 — ns 10

REQ64 to HRESET setup time tPCRVRH 10 — clocks 11

HRESET to REQ 6 4 hold t ime tPCRHRX 050ns 11

HRESET high to first FRAME assertion tPCRHFV 10 — clocks 9, 11

PCI-X init ialization pattern to HRESET setup ti m e tPCIVRH 10 — clocks 11

tPCIVKH

CLK

Input

tPCIXKH

CLK

Output Delay

tPCKHOV

High-Impedance

tPCKHOZ

Output

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 59

PCI/PCI-X

Table 50 provides the PCI-X AC timing specifications at 133 MHz.

Note that the maximum PCI-X fr equency in synchronous mode is 110 MHz.

HRESET t o PCI- X ini tializat ion pattern hold time tPCRHIX 050ns6, 11

Notes:

1. See the ti ming m easurement condi tions in the

PCI-X 1.0a Specification

2. Minimum times ar e m easured at the package pin (not the test point) . Maximum times are measured wit h the test point and

load circuit.

3. Setup time for point-to-point signals applies to REQ and GNT only. Al l ot her signals are bused.

4. For pu rposes of ac ti ve/float timing measurements, the Hi-Z or off st ate is def ined to be when the total current deliv ered

through the component pin is less than or equal to the leakage current specificati on.

5. Setup time applies only when the device is not driving the pin. Devices cannot dri ve and r eceive signals at the same time.

6. Maximum v a lue is a lso l imit ed by dela y to t he fi rst t rans action (ti me f or HRESET high to first configuration access, tPCRHFV).

The PCI-X initialization pattern contro l si gnals after the rising edge of HRESET must be negated no later than two clocks

before the first FRAME and must be fl oated no later than one cloc k before FRAME is asserted.

7. A PCI-X devi ce is permitted to ha ve the minim um v alues sho wn for tPCKHOV and tCYC only in PCI -X mode. In conve nti onal

mode , the device must meet the requirements specified in PCI 2. 2 for the appropriate clock frequency.

8. Device must meet thi s specification independent of how many outputs switch simultaneously.

9. The ti ming p arameter t PCRHFV is a minimum of 10 clo cks rat her than t he minimum of 5 c lo cks in t he

PCI-X 1.0a Specificat ion.

10.Guaranteed by characteri zation.

11.Guaranteed by design.

Table 5 0. PCI-X AC Tim ing Specifica tions at 133 MHz

Parameter Symbol Min Max Unit Notes

SYSCLK to signal valid delay tPCKHOV — 3.8 ns 1, 2, 3, 7, 8

Output hold from SYSCLK tPCKHOX 0.7 — ns 1, 11

SYSCLK to outp ut hi gh impedance tPCKHOZ — 7 ns 1, 4, 8, 12

Input setup time to SYSCLK tPCIVKH 1.2 — ns 3, 5, 9, 11

Input hold time fr om SYSCLK tPCIXKH 0.5 — ns 11

REQ64 to HRESET setup time tPCRVRH 10 — clocks 12

HRESET to REQ64 hold t ime tPCRHRX 050ns 12

HRESET high to first FRAME ass ertion tPCRHFV 10 — cloc ks 10, 12

PCI-X initializ ati on pattern to HRESET setup time tPCIVRH 10 — clocks 12

Tabl e 49. PCI-X AC Timing Specifications at 66 MHz (contin ued)

Parameter Symbol Min Max Unit Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

60 Freescale Semiconductor

High-Speed Serial Interfaces (H SSI)

15 Hig h-Speed Serial Interface s (HSSI)

The MPC8548E f ea tures one Serializer/Deserializer (SerDes) interface to be used for high-speed serial

interconnect applic ations. The SerDes interface can be used for PCI Express and/or serial R apidIO data

transfers.

This section describes the common portion of SerDes DC electr ical specifications, which is the DC

requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits

are also shown.

15.1 Signal Term s Definition

The SerDes util izes dif ferential signaling to transf er data acr oss the serial link. Th is section define s terms

used in the description and specif ication of differential signals.

Figure 38 shows how the signals are defined. For illustr ation purpose, only one SerDes lane is used for the

description. The figure shows a waveform for either a transmitter output (SD_TX and SD_TX) o r a

receiver input (SD_RX and SD_RX). Each signal swings between A volts and B volts where A > B .

HRESET to PCI-X ini ti alization pattern hold time tPCRHIX 050ns6, 12

Notes:

1. See the timing measurement conditions in t he

PCI-X 1. 0a Specification

2. Mini mum ti mes are measured at the pac kage pin (n ot the test poi nt). Maxi mum ti mes are measured with the tes t point and

load circuit.

3. Setup time for point-to-p oint signals applies to REQ and GNT only. All othe r si gnals are bus ed.

4. For purposes of active/float timing measur em ents, the Hi- Z or off state is define d to be when the total current deliver ed

through the component pin is less than or equal to the le akage c urrent specifi cation.

5. Setup time applies only when the de vice is not driving the pin. Devices cannot drive and recei ve signal s at the sam e ti m e.

6. Maximu m value is also limite d by dela y to the first trans action (time f or HRESET high to first configuration acces s, tPCRHFV).

The PCI-X initialization patter n control signals after the rising edge of HRESET must be negated no later than two clocks

befo re the fir st FR A ME and must be floated no lat er th an one clock before FRAME is asserted.

7. A PCI-X de v ice is permitted to ha v e the min imu m values sho wn for tPCKHOV and tCYC onl y in PCI- X mode. In con vention al

mode , the devic e m ust meet the r equirements specified in PCI 2.2 for the appropri ate clock frequency.

8. Device must meet thi s specificat ion independe nt of how m any o utputs sw it ch simulta neously.

9. The timing parameter tPCIVKH is a mini m um of 1. 4 ns rather than the minimum of 1.2 ns in the

PCI-X 1.0a Specification.

10.The timing parameter tPCRHFV is a minim um of 10 clocks rather than the minim um of 5 clocks in the

PCI-X 1. 0a

Specification.

11.Guaranteed by characterization.

11.Guaranteed by design.

Table 50. PCI-X AC Timing Speci fications at 133 MHz (continued)

Parameter Symbol Min Max Unit Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 61

High-Speed Serial Interfaces (HSSI)

Using this wa veform, the definitions are a s f ollows. To simplify the illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetr ical diff er ential signaling

environment.

1. Single-ended swing

The transmitter output signals and the receiver input signals SD_TX, SD_TX, SD_RX and SD_RX

each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s

single-ended swing.

2. Differ ential output volta ge, VOD (or differential output swing):

The differential output voltage (or swing) of the transmitter, VOD, is defined as the dif ference of

the two complimentary output voltages: VSD_TX –V

SD_TX. The VOD value can be either positive

or negative.

3. Differ ential input volta ge, VID (or differential input swing):

The differential input voltage (or swing) of the receiver , VID, is defined as the difference of the two

complimentary input voltages: VSD_RX –V

SD_RX. Th e VID value can be either positive or

negative.

4. Differential peak voltage, VDIFFp

The peak value of the diff ere ntial transmitter output signal or t he dif ferential receiver input signal

is defined as differential peak voltage, VDIFFp = |A – B| volts.

5. Dif ferential peak-to-peak, VDIFFp-p

Since the differential output signal of the transmitter and the differential in put signal of the receiver

each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter

output signal or the differential receiver input signal is defined as dif ferential peak-to-peak voltage,

VDIFFp-p = 2 × VDIF Fp = 2 ×|(A – B)| volts, which is twice of dif ferential swing in ampl itude, or

twice of the differential peak. For example, the output differential peak-to-peak voltage can also be

cal culat ed as VTX-DIFFp-p = 2 × |VOD|.

6. Common mode voltage, Vcm

The common mode voltage is equal to one half of the sum of the v oltages between each conductor

of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = VSD_TX

+ VSD_TX = (A + B)/2, which is the arithmetic mean of the two complimentary output voltages

within a differentia l pair. In a system, the common mode voltage may often differ from one

component’s output to the other’ s input. S omet imes, it may be even different between t he receiver

input and driver output circuits within the same component. It is also referred to as the DC offset.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

62 Freescale Semiconductor

High-Speed Serial Interfaces (H SSI)

Figure 38. Differential Voltage Definitions for Transm itter or Receiver

To illustrate these defini tions using real values, consider the case of a CM L (current mode logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or

TD) is 500 mVp-p, which is refer red as the single-ended swing for each signal. In this example, since the

differential signaling environment is fully symmetric al, the trans mitter output’s differential swing (VOD)

has the same amplitude as each signal’ s single-ended swing. The differential output signal ranges between

500 and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak

differential voltage (VDIFFp) is 500 mV. The peak-to-peak diff erential voltage (VDIFFp-p) is 1000 mVp- p.

15.2 SerD es R ef er ence C lo cks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the cor r esponding SerDes lanes. The Ser Des reference clocks inputs a re SD_REF_CLK and

SD_REF_CLK for PCI Express and serial RapidIO.

The following sections describe the SerDes reference clock requirements and some application

information.

15.2.1 SerDes Reference Clock Receiver Characteristics

Figure 39 shows a receiver reference diagram of the SerDes reference clocks.

• The supply voltage requirements for XVDD_SRDS2 are specified in Table 1 and Table 2.

• SerDes Ref er ence cl ock rece iver reference circuit structure:

— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown

in Figure 39. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω

termination to SGND_SRDSn (xcorevss) followed by on-c hip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the

differential mode and single-ended mode description below for further detail ed requirements.

D iffer e nt ia l S win g , VID or VOD = A – B

A Volts

B Volts

SD_TX or

SD_RX

SD_TX or

SD_RX

D iffer e nt ia l Peak Volta g e, VDIFFp = |A – B|

Differenti al Peak-Peak Voltage, V

DIFFpp

= 2*V

DIFFp

(not shown)

Vcm = (A + B)/2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 63

High-Speed Serial Interfaces (HSSI)

• The maximum average c urrent re quir e men t that also de termine s the co mmon mode volta ge ra nge:

— When the SerDes reference clock differential inputs are DC coupled externally with the clock

driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the

exact common mode input voltage is not critical as long as it is within the range allowed by the

maximum average current of 8 mA ( refer to the following bullet for more detail), since the

input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V

(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above

SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by

a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that

each phase of the differential input has a single-ended swing from 0 V to 800 mV with the

common mode voltage at 400 mV.

— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 Ω to

SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations , then it

must be AC-c oupled off-chip.

• The input amplitude requirement:

— This requirement is des cribed in detail in the following sections .

Figure 39. Receiver of SerDes Ref erence Cloc ks

15.2.2 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8548E SerDes reference clock inputs is dif ferent depending on the

signaling mode used to connect the clock driver chip and SerDes ref erence clock inputs as described

below:

• Differentia l mode

— The input amplitude of the diff erential clock must be between 400 and 1600 mV diff erential

peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of

the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV.

This requirement is the same for both external DC-coupled or AC-coupled connection.

— For external DC-coupled connection, as described in Section 15.2.1, “SerDes Reference Clock

Receiver Characteristics,” the maximum average current requirements sets the requirement for

Input

Amp

50 Ω

SD_REF_CLK

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

64 Freescale Semiconductor

High-Speed Serial Interfaces (H SSI)

average voltage (common mode vol tage) to be between 100 and 400 mV. Figure 40 shows the

SerDes reference clock input r equirement for DC-coupled c onnection scheme.

— For external AC-coupled connection, ther e is no common mode voltage requirement for the

clock driver. Since the ext ern al AC- coupli ng capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above

the command mode voltage (SGND_SRDSn). Figure 41 shows the SerDes reference clock

input require ment for AC-coupled connection scheme.

• Single-ended mode

— The reference clock can also be single- ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400 and 800 mV peak-to-peak (from Vmin to Vmax) with

SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 20 0 and 400 mV. Figure 42 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the ref erence clock inputs might need to be DC- or

AC-coupled externally . For the best noise performance, the reference of the clock could be DC-

or AC-coupled i nto the unused phase (SD_REF_CLK) through the s ame source impedance as

the clock input (SD_REF_CLK) in use.

Figu re 40 . Di f feren t ia l Re fe rence Cloc k Inp ut D C Re quirements (Ext ernal D C-Coup le d)

Figure 41. Differen tial Reference Clock Input DC Req uiremen ts (Exter nal AC-Coupled)

SD_REF_CLK

Vmax < 800 mV

Vmin > 0V

100 mV < Vcm < 400 mV

200 mV < I nput Amplitude or Differential Peak < 800 mV

SD_REF_CLK

Vcm

200 mV < Input Amp li tude or Diff erential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm – 400 mV

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 65

High-Speed Serial Interfaces (HSSI)

Figure 42. S ing le-Ended Reference Clock In pu t DC Requirements

15.2.3 Interfacing With Other Differential Signaling Levels

• W ith on-chip termination to SGND_SRDSn (xcorevss), the dif ferential reference clocks inputs are

HCSL (high-speed current steering logic) compatible DC-coupled.

• Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can

be used but may need to be AC-coupled due to the limited common mode input range allowed (100

to 400 mV) for DC-coupled connection.

• LVPECL outputs can produce signal with too large amplitude and m ay need to be DC-biased at

clock driver output first, then followed with series at tenuation resistor to reduce the amplitude, in

addition to AC-coupling.

NOTE

Figure 43 through Figure 46 belo w are for conceptual refer ence onl y. Due

to the fact that clock driver chip's internal structure, output impedance and

termination requirements are different between various clock driver chip

manufacturers, it’s very possible that the clock circuit reference designs

provided by c lock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Ther ef or e,

Freescale Semiconductor can neither provide the optimal clock driver

reference circuits, nor guarantee the correctness of the following clock

driver connection reference circuits. The system designer is recommended

to contact the selecte d clock driver chip vendor for the optimal reference

circuits with the MPC8548E SerDes reference clock receiver requirement

provided in this document.

SD_REF_CLK

400 m V < SD_REF_CLK Input Amplitude < 800 mV

0 V

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

66 Freescale Semiconductor

High-Speed Serial Interfaces (H SSI)

Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MP C8548E SerDes reference clock

input’s DC requirement.

Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mo de voltage is higher than the MPC8548E SerDes referenc e clock

input’s allowed range (100 to 400mV), AC-coupled con nection scheme must be used. It assumes the

LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter

establishes its ow n common mode level without relying on the receiver or other external component.

Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’ s DC levels (both common mode voltages and output swing) are incompatible with

the MPC8548E SerDes ref er ence clock input’s DC requirement, AC-coupling has to be us ed. Figure 45

assumes that the LVPECL clock dr iver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL

50 Ω

SD_REF_CLK

Clock Driver 100 Ω Diff erential PWB Trace

Clock driver vendor dependent

source term ination resi stor

CLK_Out

HCSL CLK Driver Chip

33 Ω

Total 5 0 Ω. Assume clock driver’s

output impedance is about 16 Ω.

MPC8548E

CLK_Out

SerDes Refer.

CLK Receive r

Clock Driver

SD_REF_CLK

Clock Driver 100 Ω D iffe rential PWB Trace

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8548E

SerDes Re fer.

CLK Receiv er

50 Ω

Clock Driver

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 67

High-Speed Serial Interfaces (HSSI)

outputs prior to AC-coupling. Its value could be ranged f rom 140 to 240 Ω depending on the clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination

resistor to attenuate the LVPECL output’ s diff erential peak level such that it meets the MPC8548E SerDes

reference clock’s diff erential input amplitude requirement (between 200 and 800 mV differential peak).

For example, if the LVPECL output’s dif f erential peak is 900 mV and the desired SerDes reference clock

input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. C onsult a

clock driver chip manufacturer to verify whether this connecti on scheme is compatible with a particular

clock driver chip.

Figure 4 5. AC-Coupled Differential Connection with LVPECL Clock Driver (Refe rence Only)

Figure 46 s hows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with the MPC8548E SerDes r efe rence cloc k

input’s DC requirement.

Figure 46. Single-Ended Connection (Reference Only)

SD_REF_CLK

Clock Driver 100 Ω Differential PWB Trace Ser Des Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK Driver Chip

MPC8548E

10 nF

CLK_Out

Clock Driver

50 Ω

SD_REF_CLK

100 Ω Differ ential PWB Trace

Clock Driver

CLK_Out

Single-Ended CLK

Driver Chip MPC8548E

33 Ω

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

50 Ω

SerDes Refer.

CLK Receiver

50 Ω

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

68 Freescale Semiconductor

PCI Expr ess

15.2.4 AC Requirements for SerDes Reference Clocks

The clock driver selecte d should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise l ess than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phas e nois e above 15 M Hz is fi ltered by the PLL. The most problematic phase nois e

occurs in the 1–15-MHz range. The source impedance of the clock dr iver should be 50 Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

The detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based

on application usage. Refer to the foll owing sections for detailed information:

•Section 16. 2, “AC Requirements for PCI Express SerDes Clocks”

• Section 17. 2, “AC Requirements for Serial RapidIO SD_RE F_CL K and SD_REF_C LK”

15.2.4.1 Spread Spectrum Clock

SD_REF_CLK/SD_REF_CLK ar e designed to work with a spread spectrum clock (+0% to –0.5%

spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,

a source without significant unintended modulation should be used.

15.3 SerDes Transmitter and Receiver Reference Circ uits

Figure 47 shows t he refere nce circuits for SerDes dat a lane’s transmi tter and receive r.

Figure 47. SerDes Tra nsmi tter and Rece iver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol sec tion below

(PCI Express , Serial Rapid IO, or SG MII) in this document based on the application usage:

•Section 16, “PCI Express”

•Section 17, “Serial RapidIO”

Note that external a n AC coupling ca pacitor is required for the above three serial transmission protocols

with the capacitor value defined in the specification of each protocol section.

16 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8548E .

SD_TX

SD_RX

50 ΩReceiver

Transmitter

50 Ω

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 69

PCI Expr ess

16.1 DC Requirement s for PCI Express SD_REF_CLK and

SD_REF_CLK

Fo r more i n for m a t ion , se e Section 15.2, “SerDes Reference Clocks.”

16 .2 AC Requ irements for PCI Expres s SerDes Clocks

Table 51 lists the AC requir ements for the PCI Express SerDes clocks.

16.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

16.4 Physical Layer Sp ecifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer refer to PCI Exp ress Ba se

Specification. Rev. 1.0a.

16.4.1 Differential Transmitter (TX) Output

Table 52 def ines the specific ations for the dif fe rential output at a ll transmitte rs (TXs). The parame ters are

specified at the component pins.

Tabl e 51. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol P arameter Description Min T yp Max Unit Notes

tREF REFCLK cycle time — 10 — ns 1

tREFCJ REFCLK cycle-to-cycle jitter. Difference i n the period of an y two

adjacent REFCLK cycles. — — 100 ps —

tREFPJ Phase jitter. Deviation in edge location with respect to mean edge

location. –50 — 50 ps —

Note:

1. Typical based on

PCI Express Specific ation 2.0

Ta ble 52. Di fferential Transmi tter (TX) Outpu t Specifications

Symbol Parameter Min Nom Max Unit Comments

UI Unit int erval 399. 88 400 400.12 ps Each UI i s 400 ps ± 300 ppm. UI d oes not account

for spread spec trum clock dictated variations.

See Note 1.

VTX-DIFFp-p Differential

peak-to-peak

output voltage

0.8 — 1.2 V VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D–|. See Note 2.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

70 Freescale Semiconductor

PCI Expr ess

VTX-DE-RATIO De- emphasized

differential

output voltage

(ratio)

–3.0 –3.5 –4.0 dB Ratio of the VTX-DIFFp-p of the second and

follow ing bits after a tr ansition divi ded by the

VTX-DIFFp-p of th e fi rs t bi t afte r a trans itio n .

See Note 2.

TTX-EYE Minimum TX eye

width 0.70 — — UI The max imum transmitter jitter can be deri ved as

TTX-MAX-JITTER = 1 – TTX-EYE = 0.3 UI.

See Notes 2 and 3.

TTX-EYE-MEDIAN-to-

MAX-JITTER

Maximum time

between the

jitter median and

maximum

deviation from

the median.

— — 0.15 UI Jitter is defi ned as the measurement variat ion of

t h e cro ssing po ints (V TX-DIFFp-p = 0 V) in relation

to a reco vered TX UI. A recovered TX UI is

calcul ated o v er 3500 co nsecu tiv e un it in terval s of

sample data . Jitter is measur ed using all edges of

the 250 consecutive UI in the center of the 3500

UI used for calculating the TX UI.

See Notes 2 and 3.

TTX-RISE, T TX-FALL D+/D– TX output

rise/fa ll time 0.125 — — UI See Notes 2 and 5.

VTX-CM-ACp RMS AC peak

common mode

output voltage

——20mVV

TX-CM-ACp = RMS(|VTXD+ + VTXD–|/2 –

VTX-CM-DC)

VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D–|/2.

See Note 2.

VTX-CM-DC-ACTIVE-

IDLE-DELTA

Absolute delta of

dc common

mode v oltage

during L0 and

electric al i dle

0—100mV|V

TX- CM - DC (during L0) + VTX-CM-Idle-DC (duri ng

electrical idle)| ≤ 100 mV

VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D–|/2 [L0]

VTX-CM-Idle-DC = DC(avg) of |VTX-D+ +V

TX-D–|/2

[electrical idle]

See Note 2.

VTX-CM-DC-LINE-DELTA Absolute delta of

DC common

mode between

D+ and D–

0—25mV|V

TX-CM-DC-D+ – VTX-CM-DC-D–| ≤ 25 mV

VTX-CM-DC-D+ = DC(avg) of |VTX-D+|

VTX-CM-DC-D–= D C (avg) of |VTX-D–|.

See Note 2.

VTX-IDLE-DIFFp Electrical idle

diff erent ial pea k

output voltage

0—20mVV

TX-IDLE-DIFFp = |VTX-IDLE-D+ – VTX-IDLE-D–|

≤20 mV.

See Note 2.

VTX-RCV-DETECT The amount of

voltage chang e

allowed during

receiver

detection

— — 600 mV The total amount of voltage change that a

transmitter can apply to s ense whether a low

impedance receiver is present. See Note 6.

VTX-DC-CM The TX DC

common mode

voltage

0 — 3.6 V The allowed DC common mode voltage under any

conditions. See Note 6.

ITX-SHORT TX short c ir cuit

current limit — — 90 mA The total curren t the transmit ter can pr ovide when

shor ted t o its gr ound

Tabl e 52. Differential Transmitter (TX) Output Specifications (continued)

Symbol Parameter Min Nom Max Unit Comments

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 71

PCI Expr ess

TTX-IDLE-MIN Minimum time

spent in

electric al i dle

50 — UI Minimum time a transmit ter must be in electric al

idle ut il ized by the re ceiver to start looking for an

electri cal idle exit after successfull y receiving an

electric al i dle ordered set

TTX-IDLE-SET-TO-IDLE Maximum time

to transition to a

valid electrical

idle af te r

sending an

electric al i dle

ordered set

— — 20 UI After sending an electrica l i dle order ed set, the

transmitter must meet all electrical idle

specifications within this time. This is co nsidered

a debounce time for the transmitter to meet

electric al i dle after transitioning f rom L0.

TTX-IDLE-TO-DIFF-DATA Maximum time

to transition to

valid TX

specifications

after leaving an

electric al i dle

condition

— — 20 UI Maxi mum t ime t o meet all TX spe ci ficati ons when

transitioni ng from e lectrical idle to sendi ng

differential data. This is considered a deboun ce

time f or the TX to meet all TX specificat ions after

leaving el ectrical idle

RLTX-DIFF Differential

return loss 12 — — dB Measured over 50 MHz to 1.25 GHz.

See Note 4.

RLTX-CM Common mode

return loss 6 — — dB Measured ov er 50 M Hz to 1.25 GHz.

See Note 4.

ZTX-DIFF-DC DC differential

TX impedance 80 100 120 ΩTX DC differential mode low impedance

ZTX-DC Transmitter DC

impedance 40 — — ΩRequired TX D+ as well as D– DC impedance

during al l st ates

LTX-SKEW Lane-to-lane

output skew — — 500

+2UI ps Static ske w between any two transmitt er lanes

within a singl e Link

CTX AC coupling

capacitor 75 — 200 nF All tran sm it ters shall be AC c oupled. The A C

coupling is r equired either within the media or

within t he tra nsmi ttin g compon ent itsel f . See note

Tabl e 52. Differential Transmitter (TX) Output Specifications (continued)

Symbol Parameter Min Nom Max Unit Comments

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

72 Freescale Semiconductor

PCI Expr ess

16.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram i n Figure 48 is spec ified using the passive compliance/test measurement load (see

Figure 50) in place of any real PCI Express interconnect +RX component.

Ther e are two eye diagrams that must be met for the tra nsmitter. Both e ye diagrams must be a ligned in

time using the jitter media n to locate the c e nter of the eye diag r am. T he different e ye diagra ms will diff er

in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level

of the de-emphasized bit will always be relative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the

TX UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in

the 3500 conse cutive UI interval with a fit algorithm using a minimization

merit func tion (for example, le ast squares and median devia tion fits).

Tcrosslink Crosslink

random timeout 0 — 1 ms This random timeout helps resolve conflicts in

crosslink configuration b y eventually resulting in

only one downstrea m and one upstr eam port.

See Note 7.

Notes:

1. No test load is necessarily associ ated with this v alue.

2. Specified at the measurement point int o a timi ng and volt age compliance te st load as sho wn in Figure 50 and mea sur ed ov e r

any 250 consecutive TX UIs. (Al so refe r to t he tr ansmitte r compliance e ye diagr am shown in Figure 48.)

3. A TTX-EYE = 0.70 UI provides for a tot al sum of determin istic and random jitter b udget of TTX-JITTER-MAX = 0.30 UI for the

tran smitt er col lecte d o ver an y 25 0 consecu tiv e TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER med ian i s less tha n half of the t otal

TX jitter bud get collect ed o ver any 250 con secuti ve TX UIs . It should be not ed tha t the median is not the same as the mean .

The jitter me dian describes the point in ti me where the number of jit ter points on eit her side is appr oximately equal as

opposed to the av eraged time v alue.

4. The transmi tter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode

return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impeda nce requir em ent

appli es to a ll v a lid i nput l evels. Th e ref e rence i mpedan ce f or return los s meas uremen ts is 50 Ω t o grou nd f or both t he D+ and

D– li ne (t hat i s , as meas ured b y a vect or ne two rk anal yz er wi th 50- Ω probes—see Figure 50). Note that the seri es capacitor s

CTX i s optional for the return loss measurement.

5. Measur ed betwee n 20% –80% at tr ansm itter p ac kage pin s into a test l oad a s shown i n Figure 50 for both VTX-D+ and VTX-D–.

6. See Section 4.3.1.8 of the

PCI Express Base Specifications Rev 1.0a.

7. See Section 4.2.6.3 of the

PCI Express Base Specifications Rev 1.0a.

8. MPC8548E SerDes transmitter does not have CTX built in. An ext ernal AC coupling capacitor is required.

Tabl e 52. Differential Transmitter (TX) Output Specifications (continued)

Symbol Parameter Min Nom Max Unit Comments

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 73

PCI Expr ess

Figure 48. Minimum Transmitter Timing and Voltage Output Compliance Specifications

16.4.3 Differential Receiver (RX) Input Specifications

Table 53 defines the specifications for the diff e rential input at all receivers (RXs). The parameters are

specified at the component pins.

Tabl e 53. Differential Receiver (RX) Input Specifications

Symbol Parameter Min Nom Max Unit Comments

UI Unit int erval 399. 88 400 400.12 ps Each UI i s 400 ps ± 300 ppm. UI d oes not account

for spread spec trum clock dictated variations.

See Note 1.

VRX-DIFFp-p Dif ferential

peak-to-peak

input vol tage

0.175 — 1.200 V VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–|. See Note 2.

TRX-EYE Minimum

receiver eye

width

0.4 — — UI The maximum interconnect media and transmitter

jit ter that can be tolerated by the receiver can be

deriv ed as T RX-MAX-JITTER =1 – T

RX-EYE = 0. 6 UI.

See Notes 2 and 3.

TRX-EYE-MEDIAN-to-

MAX-JITTER

Maximum time

between the

jitter median and

maximum

deviation from

the median

— — 0.3 UI Jitter is defined as the measurement var iation of

the crossing points (VRX-DIFFp-p = 0 V) in relati on

to a reco vered TX UI. A recovered TX UI is

calcul ated o v er 3500 co nsecu tiv e un it in terval s of

sample data . Jitter is measur ed using all edges of

the 250 consecutive UI in the center of the

3500 UI us ed for calculating the TX UI.

See Notes 2, 3, and 7.

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

[De-Emphasized Bit]

0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX)

566 mV (3 dB) >=

TX-DIFFp-p-MIN

>= 505 mV (4 dB)

[Transition Bit]

TX-DIFFp-p-MIN

= 800 mV

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

[Transition Bit]

TX-DIFFp-p-MIN

= 800 mV

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

74 Freescale Semiconductor

PCI Expr ess

VRX-CM-ACp AC peak

common mode

input vol tage

——150mVV

RX-CM-ACp = |VRXD+ – VRXD-|/2 + VRX-CM-DC

VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D–|÷ 2.

See Note 2.

RLRX-DIFF Differenti al

return loss 15 — — dB Measured over 50 MHz to 1. 25 G Hz wit h the D+

and D– lines biased at +300 mV and –300 m V,

respectively. See Note 4.

RLRX-CM Common mode

return loss 6 — — dB Measur ed over 50 MHz to 1. 25 G H z wit h the D+

and D– lines biased at 0 V. See Note 4.

ZRX-DIFF-DC DC diff erential

input imp edance 80 100 120 ΩRX DC differential m ode impedance. See Note 5.

ZRX-DC DC input

impedance 40 50 60 ΩRequired RX D+ as well as D– DC impedance

(50 ± 20% tolerance). See Notes 2 and 5.

ZRX-HIGH-IMP-DC Powe red down

DC input

impedance

200 k — — ΩRequired RX D+ as well as D– DC im pedance

when the receiver terminations do not have

power. See Note 6.

VRX-IDLE-DET-DIFFp-p Electrical idle

detect threshold 65 — 175 mV VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ –VRX-D–|.

Measured at the package pins of the receiver

TRX-IDLE-DET-DIFF-

ENTERTIME

Unexpected

electric al i dle

enter detect

threshold

integration time

— — 10 ms An unexpected electrical idle (VRX-DIFFp-p <

VRX-IDLE-DET-DIFFp-p) mu st be r ecognized no

longer than TRX-IDLE-DET-DIFF-ENTERING to si gnal

an unexpected id le condition.

Tabl e 53. Differential Receiv er (RX) Input Specifications (continued)

Symbol Parameter Min Nom Max Unit Comments

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 75

PCI Expr ess

16 .5 Receiver Compliance Ey e Diagr ams

The RX eye diagram in Figure 49 is specif ied usi ng the passive comp lia nce/t est m easur ement lo ad (see

Figure 50) in place of any real PCI Express RX component.

Note: In general, the minimum receiver eye diagram measured with the compliance/test measurement load

(see Figure 50) will be larger than the minimum receiver eye diagram measured over a range of systems

at the input receiver of any real PCI Expr es s component. The degraded eye diagram at the input receiver

is due to traces intern al to the package as we ll as s ilic on para sitic c haract eristics which cause the re al PCI

Express component to vary in impedance from the compliance/test measurement load. T he i nput r e ceiver

eye diagram is implementation specific and is not speci fied. RX component designer should provide

additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in

Figure 49) expected at the input receiver based on some adequate combi nat ion of system sim ulat ions and

the return loss measured looking into the RX package and silicon. The RX eye diagram must be aligned

in time using the jitter median to locate the center of the eye diagram.

LTX-SKEW Total Skew — — 20 ns Skew across all lanes on a Link. This includes

vari ation in the length of SKP ord ered set (for

example, COM and one to five symbols) at the RX

as well as any delay dif ferences arising from the

interconnect itself.

Notes:

1. No test load is necessarily associ ated with this v alue.

2. Speci fied at the meas uremen t point and measur ed ov er an y 25 0 c onsecut ive UIs . The test loa d in Figure 50 should be us ed

as the RX device when tak ing measurements (also refer to the r eceiver com pliance eye diagram shown in Figure 49). If the

cloc ks to t he RX and TX ar e not deriv ed f rom the sa me ref er ence c lock , the TX UI recov e red fr om 3500 con secuti ve UI must

be used as a reference for the e ye diagr am .

3. A TRX-EYE = 0.40 UI pro vides f or a total sum of 0.60 UI deterministic and random jitter budget for t he transmitter and

interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specifi cation ensures a ji tter distribution

in whi ch the median and the ma ximum deviation from the me dian is less than half of the total. UI ji tter b udget col lec ted over

any 250 consecutive TX UIs. It should be noted tha t the median is not the same as the mean. The jitter medi an descri bes

the point in time wher e the n um ber of jitter points on either side is approxima tely equal as opposed to the averaged time

value. If the cloc ks to the RX and TX are not derived from the same reference cl ock, the TX UI recovered fr om 3500

consecutiv e UI m ust b e used as the refer ence for the eye diagram.

4. The recei ver inp ut i mp edance s hall re sult in a dif ferent ial return loss greater than or equal to 15 dB with the D+ line biased

to 300 mV and the D– line biased to –{300 mV and a common mode return loss greater than or equal to 6 dB (no bia s

requir ed) over a frequency range of 50 MHz to 1.25 GHz. This input impedance require me nt applies to all valid input le vels.

The ref erence impedanc e for return lo ss measurem ents f or is 5 0 Ω to ground f or bot h the D+ a nd D– line (that i s, as measured

by a vect or network analyzer with 50-Ω probes—see Figure 50). Note: that the series capaci tors CTX i s optiona l f or the r eturn

loss measurement.

5. Impedance during all LTSSM states. When transitioning from a fundamental r eset to detect (the initi al state of the LTSSM)

there i s a 5 ms transition tim e before receiver termination values must be met on all unconfigured lanes of a port.

6. The RX DC common mode Impedance that exists when no power is present or fundamental reset i s asserted. This helps

ensure that the receiver detect cir cuit will not falsely assume a recei ver is powered on when it is not. This term must be

measured at 30 0 mV abo ve the RX groun d.

7. It is recommended that t he recovered TX UI is calculat ed using al l edges in the 3500 consecutive UI interval wit h a fit

algori thm using a minimization merit f unction. Least squares and media n deviation fits hav e worked well with exp erimental

and simulated data.

Tabl e 53. Differential Receiv er (RX) Input Specifications (continued)

Symbol Parameter Min Nom Max Unit Comments

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76 Freescale Semiconductor

PCI Expr ess

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the

TX UI.

NOTE

The reference impedance for return loss measurements is 50. to ground for

both the D+ and D– line (th at is, as measured by a vector network analyzer

with 50-Ω probes—see Figure 50). Note that the series capacitors, CTX, are

optional for the return loss measuremen t.

Figure 49. Minimum Receive r Eye Timing and Vo ltag e Compli ance Specification

16.5.1 Compliance Test and Measurement Load

The AC timing and voltag e paramete rs must be verified at the measurement point, as specif ied within

0.2 inches of the package pins, into a test/measurement load shown in Figure 50.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is me ant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in le ngth at the package

pin boundary.

Figure 50. Compliance Test/Meas uremen t Load

VRX-DIFF = 0 mV

(D+ D– Crossi ng Point)

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

RX-DIFFp-p-MIN

> 175 mV

0.4 UI = TRX-EYE-MIN

Silicon

+ Package

C = CTX

R = 50 ΩR = 50 Ω

D+ P ackage

D– P ackage

D+ P ackage

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17 S erial RapidIO

This section descr ibes t he DC and AC electrical speci f icat ions for the RapidI O inte rface of the

MPC8548E, for the LP-Serial physical layer. The electrical specifications cover both single- and

multiple-lane links. Two transmitters (short and long run) and a s ingle receiver are specified for each of

three baud ra tes, 1.25, 2.50, and 3.125 GBaud.

Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to

driving t wo connectors across a backplane. A s ingle receiver specification is given that will accept signals

from both the short- and long-run transmitter specifications.

The short-run tr ansmitter should be used mainly for chi p-to-chip connecti ons on either the same

printed-cir cui t board or across a single connect or. This covers the case where connections ar e made to a

mezzanine (daughter) card. The minimum swings of the short-run specification reduce the overall power

used by the transceivers .

The long-run transmitter specifications use lar ger voltage swings that are capable of driving signals across

backplanes. This allows a user to drive signals across two connectors and a backplane. The s pecifications

allow a distance of at least 50 cm at all baud rates.

All unit i ntervals are specified with a tolerance of ± 100 ppm. The worst case frequency difference between

any transmit and receive clock will be 200 ppm.

To ensure interoperability between drivers and re ceivers of differ ent vendors and technologies, AC

coupling at the rece iver input must be used.

17.1 DC Requ irements for Serial RapidIO SD_REF_CLK and

SD_REF_CLK

Fo r more i n for m a t ion , se e Section 15.2, “SerDes Reference Clocks.”

17.2 AC Requirements for Serial RapidIO SD_REF_CLK and

SD_REF_CLK

Table 54 lists the Serial RapidIO SD_REF_CLK and SD_REF _CLK AC requirements.

Tabl e 54. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol Paramet er Description Mi n Typ Ma x Unit Comments

tREF REFCLK cycle time — 10(8) — ns 8 ns applies only to serial

RapidIO with 125-MHz ref erenc e

clock

tREFCJ REFCLK cycle- to-cycle ji tter . Diff ere nce in the

period of an y two adjacent REFCLK cycles. — — 80 ps —

tREFPJ Phase ji tt er. Deviation in edge location wit h

respect to mean edge location. –40 — 40 ps —

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Serial RapidIO

17.3 Signal Definitions

LP-serial links use differential signaling. This section defines terms used in the des cription and

specification of differential signals. Figure 51 shows how the signals are defined. The figures show

wavefor ms for either a transmitte r output (T D and TD) or a r eceiver input ( RD and RD). Each signal

swings between A volts and B volts where A > B . Using these waveforms, the definitions are as f ollows:

1. The transmitter output signals and the receiver input signals TD, TD, RD, and RD each have a

peak-to-peak swing of A – B volts.

2. The differential output signal of the transmitter, VOD, is defined as VTD –V

TD.

3. The differential input signal of the receiver, VID, is defined as VRD –V

RD.

4. The differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) volts.

5. The peak value of the differential transmitter output signal and the differential receiver input

signal is A – B volts.

6. The peak-to- peak value of the dif ferentia l transm itte r output signal and the diffe rential re c eiver

input signa l is 2 ×(A – B) volts .

Figure 51. Differential Peak–P eak Voltage of Transmitter or Receiver

To illustrate these defini tions using real values, consider the case of a CM L (current mode logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of the signals TD and

TD is 500 mVp-p. The differential output signal ranges between 500 and –500 mV. The peak differential

voltage is 500 mV. The peak-to-peak differential voltage is 1000 mVp-p.

17.4 Equalization

With the use of high speed se rial links, th e interconnec t media will cause degradation of the signal at the

receiver. Effects such as Inter- Symbol Interference (ISI) or data dependent jitter are produced. This loss

can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.

To negate a portion of these effects, equalization can be used. The most common equalization techni ques

that can be used are:

• A passive high pass filter network placed at the receiver. This is of ten referred to as passive

equalization.

• The use of active circuits in the receiver. This is oft en referred to as adapt ive equalization.

Differential Peak-to-Peak = 2 × (A – B)

A Volts TD or RD

TD or RD

B Volts

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Serial RapidIO

17.5 Explanator y Note on Transmitter and Receiver Specifications

AC electrical specifications are given for transmitter and receiver. Long- and short-run interfaces at three

baud rates (a total of six cases) are described.

The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified

in Clause 47 of IEEE 802.3ae-2002.

XAUI has similar application goals to Serial RapidIO, as described in Section 8.1. The goal of this

standard is that electr ical designs for Serial RapidIO can reuse electrical designs for XAUI, suitably

modified for applications at the baud intervals and reaches described herein.

17 .6 Transmi tter Spec ificatio ns

LP-serial transmitter electric al and timing specifications are stated in the text and tables of this section.

The diff ere ntial return loss , S11, of the transmitter in each case shall be better than:

• –10 dB f or (baud frequency)/10 < Fr eq( f) < 625 MHz, a n d

• –10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ Freq( f) ≤ baud frequency

The refere nce impedance for the differential return loss measurements is 100- Ω re s isti v e. Dif fe rentia l

return los s includes contributions f rom on-chip circuitry, chip packaging, and any off-chip components

rel ated to the driver. The output impedance requirement a pplie s to all valid output levels .

It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output,

in each case have a minimum value 60 ps.

It is recommended that the timing skew at the output of an LP-serial trans mitte r betw een the two signals

that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB.

Table 55. Short Run Transmi tter AC Timing S pecifications— 1.25 GB au d

Characteristic Symbol Range Unit Notes

Min Max

Output voltage VO–0.40 2.30 V Voltage relative to COMMON of either signal

com pris ing a dif ferent ial pair

Differenti al output voltage VDIFFPP 500 1000 mV p-p —

De te rm in is ti c jit te r JD—0.17UI p-p —

Total jitter JT—0.35UI p-p —

Mu lt ip le out pu t skew SMO — 1000 ps Skew at the tr ansmitt er out put between lanes of a

multila ne lin k

Unit Interval UI 800 800 ps ±100 ppm

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80 Freescale Semiconductor

Serial RapidIO

Table 56. Short Run Transmitter AC Timing Specifications—2.5 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output voltage V O–0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential output voltage VDIFFPP 500 1000 mV p-p —

Deterministic jitter JD—0.17UI p-p —

Total jitter JT—0.35UI p-p —

Mu l tip le o utp ut skew SMO — 1000 ps Ske w at the t ransm itter out put be twe en lane s of a

multi lane link

Unit interv al UI 400 400 ps ±100 ppm

Table 57. Short Run Transmitter AC Timing Specifications—3.125 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output voltage V O–0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential output voltage VDIFFPP 500 1000 mVp-p —

Deterministic jitter JD—0.17UI p-p —

Total jitter JT—0.35UI p-p —

Mu l tip le o utp ut skew SMO — 1000 ps Ske w at the t ransm itter out put be twe en lane s of a

multi lane link

Unit interv al UI 320 320 ps ±100 ppm

Table 58. Long Run Transmitter AC Timing S pecifications— 1. 25 GBau d

Characteristic Symbol Range Unit Notes

Min Max

Output voltage V O–0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential output voltage VDIFFPP 800 1600 mVp-p —

Deterministic jitter JD—0.17UI p-p —

Total jitter JT—0.35UI p-p —

Mu l tip le o utp ut skew SMO — 1000 ps Ske w at the t ransm itter out put be twe en lane s of a

multi lane link

Unit interv al UI 800 800 ps ±100 ppm

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Serial RapidIO

For each baud rate at which an LP-serial tr ansmitter is specified to operate, the output eye pattern of the

transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown

in Figure 52 with the parameters spe cified in Table 61 when measured at the output pins of the device and

the device is driving a 100-Ω ± 5% differe ntial resistive load. The output eye pattern of an LP-serial

Table 59. Long Run Transmi tter AC T imin g Specification s— 2.5 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output voltage V O–0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential output voltage VDIFFPP 800 1600 mVp-p —

Deterministic jitter JD—0.17UI p-p —

Total jitter JT—0.35UI p-p —

Mu l tip le o utp ut skew SMO — 1000 ps Ske w at the t ransm itter out put be twe en lane s of a

multi lane link

Unit interv al UI 400 400 ps ±100 ppm

Table 60. Long Run Transmitter AC Timing Specifications—3.125 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output voltage V O–0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential output voltage VDIFFPP 800 1600 mVp-p —

Deterministic jitter JD—0.17UI p-p —

Total jitter JT—0.35UI p-p —

Mu l tip le o utp ut skew SMO — 1000 ps Ske w at the t ransm itter out put be twe en lane s of a

multi lane link

Unit interv al UI 320 320 ps ±100 ppm

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82 Freescale Semiconductor

Serial RapidIO

transmitt er that i mplements pre-emphasis ( to equalize the link and re duce inter -symbol inte rference) need

only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized.

Figure 52. Transmitter Output Complianc e Mask

17.7 Receiver Specifications

LP-s erial re c eiver electric al and timing specifi cations are stated in the text and tables of this section.

Receiver input impedance shall result in a diff er ential return loss better tha t 10 dB and a common mode

return los s better than 6 dB from 100 MHz to (0.8) × (baud frequency). This includes contributions from

on-chip circuitry, the chip package, and any off-chip components related to the receiver. AC coupling

Table 61 . Transm itter Differential Output Eye Diagram Pa rameters

Transmit ter Type VDIFFmin (mV) VDIFFmax (mV) A (UI) B (UI)

1.25 GBaud short ra nge 250 500 0. 175 0.39

1.25 GBaud long range 400 800 0.175 0.39

2.5 GBaud short range 250 500 0.175 0.39

2.5 GBaud long range 400 800 0.175 0.39

3.125 GBaud short r ange 250 500 0.175 0.39

3.125 GBaud long range 400 800 0. 175 0.39

VDIFF min

VDIFF ma x

–VDIFF min

–VDIFF max

0B1-B1

Time in UI

Transm it ter Differential Output Voltage

A1-A

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Freescale Semiconductor 83

Serial RapidIO

components are included in this requirement. T he reference impedance for return los s meas urements is

100-Ω resistive for differential return l oss and 25-Ω resistive for common mode.

Table 62. Receiver AC Ti min g Specific ations—1. 25 GBau d

Characteristic Symbol Range Unit Notes

Min Max

Differential input voltage VIN 200 1600 mVp-p Measured at receiver

Deterministic jitter tolerance JD0.37 — UI p-p Measured at receiver

Combined dete rministi c and random

jitter tolerance JDR 0.55 — UI p-p Measured at receiver

Total jitter toler ance1JT0.65 — UI p-p Measured at receiver

Multip le inp ut skew SMI — 24 ns Skew at the receiver input between lanes

of a multilane link

Bit error rate BER — 10–12 ——

Unit interv al UI 800 800 ps ±100 ppm

Note:

1. Total jitter is composed of three components, deterministic jitt er, random jitter, and si ngle frequency sinusoidal jitter. The

sinus oidal jit ter ma y ha v e an y ampl itude and f requency in the unsha ded regi on of Figure 53. Th e sinus oidal jit ter compo nent

is included to ensure margin for low frequency jitter, wander, noise, crosst alk, and other variable system eff ects.

Table 63. Receiver AC Timing Specifications—2.5 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Differential input voltage VIN 200 1600 mVp-p Measured at receiver

Deterministic jitter tolerance JD0.37 — UI p-p Measured at receiver

Combined dete rministi c and random

jitter tolerance JDR 0.55 — UI p-p Measured at receiver

Total jitter toler ance1JT0.65 — UI p-p Measured at receiver

Multip le inp ut skew SMI — 24 ns Skew at the receiver input between lanes

of a multilane link

Bit error rate BER — 10–12 —

Unit interv al UI 400 400 ps ±100 ppm

Note:

1. Total jitter is composed of three components, deterministic jitt er, random jitter, and si ngle frequency sinusoidal jitter. The

sinus oidal jit ter ma y ha v e an y ampl itude and f requency in the unsha ded regi on of Figure 53. Th e sinus oidal jit ter compo nent

is included to ensure margin for low frequency jitter, wander, noise, crosst alk, and other variable system eff ects.

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Serial RapidIO

Figure 53. Single Frequency Sinusoidal Jitter Limits

Table 64. Receiver AC Timing Specifications—3.125 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Differential input voltage VIN 2 00 1600 mVp-p Measured at receiver

Deterministic jitter tol e rance JD0.37 — UI p-p Measured at receiver

Combined deterministic and random

jitter tolerance JDR 0.55 — UI p-p Measured at receiv er

To ta l jit te r to le ra n c e1JT0.65 — UI p-p Measured at receiver

Multiple input skew SMI — 22 ns Skew at the r eceiver input between lanes

of a multilane link

Bit error rate BER — 10-12 —

Unit interv al UI 320 320 ps ±100 ppm

Note:

1. Total ji tter is comp osed of three components, determinis tic jitte r, random jitter and single frequ ency sinusoi dal jitter. The

sinus oidal jit ter ma y ha ve a ny ampli tud e and f requenc y i n the uns haded regi on of Figure 53. The sin usoidal jit te r compone nt

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and ot her variable system effects.

8.5 UI p-p

0.10 UI p-p

Sinusoidal Jit ter Ampli tude

22.1 kHz 1.875 MHz 20 MHz

Frequency

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Freescale Semiconductor 85

Serial RapidIO

17.8 Re ce ive r Eye D iag r ams

For each baud rate at whi ch an LP- serial rece iver is specif ied to operat e, the recei ver sha ll meet the

corresponding bit error rate specification (Table 62, Table 63, Table 64) when the eye pattern of the

receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver

input compliance mask shown in Figure 54 with the parameter s specified in Table 65. The eye pattern of

the receiver test signal is measured at the input pins of the re ceiving device with the device replaced with

a 100-Ω ± 5% differential resistive load.

Figure 54. Receiver Input Compliance Mask

17.9 Measureme nt and Test Requirements

Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in

Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly

guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002

Table 65. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

Receiver T ype VDIFFmin

(mV) VDIFFmax

(mV) A (UI ) B (UI)

1.25 GBaud 100 800 0.275 0.400

2.5 GBaud 100 800 0.275 0.400

3.125 GBaud 100 800 0.275 0.400

VDIFF max

–VDIFF max

VDIFF min

–VDIFF min

Time (UI)

Receiver Differential Input Voltage

AB 1-B1-A

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86 Freescale Semiconductor

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is specifie d as the test pattern for use in eye pattern and jitter measurements . Annex 48B of I EEE S td.

802.3ae-2002 is recommended as a reference for additional information on jitter test methods.

17.9.1 Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point

at (baud frequency)/1667 is applied to the jitte r. The data pattern for template measurements is the

continuous jitter test pat tern (CJPAT) defined in Annex 48A of IE EE 802.3ae. All lanes of the LP-ser ial

link sha ll be active in both the transmit and receive directions, and opposite ends of the links shall use

asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane

implem entation s shall use the CJPAT se quenc e specified in Annex 48A for transmi ssion on lane 0. The

amount of data represented in the eye shall be adequate to ensure that the bit err or r atio is les s than 10–12.

The eye pattern shall be measured with AC coupling and the compliance template centered at 0 V

dif ferential. The left and right edges of the temp late shall be aligned with the m ean zero crossing points of

the measured data eye. The load for this test shall be 100-Ω resistive ± 5% differential to 2.5 GHz.

17.9.2 Jitter Test Measurements

For th e purpose of jitt er measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud

frequency)/1667 is applied to the jitter . The data pattern for jitter measurements is t he Continuo us Jitter test

pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP -serial link shall be

active in both the transmit and receive direc tions, and opposite ends of the links shall use asynchronous

clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations

shall use t he CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured

with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter

toler ance setup) shall be performe d with a test procedure resulting in a BER curve such as that described

in Annex 48B of IEEE 802.3ae.

17.9.3 Trans m it Jit ter

Transmit jitter is measured at the drive r output when terminated into a load of 100 Ω resi st i v e ± 5%

differential to 2.5 GHz.

17.9.4 Jitte r To le ra nce

Jitter tolerance is measured at the receiver using a jit ter tolerance test signal. This signal is obtained by first

producing the sum of deterministic and random jitter defined in Section 17.7, “Receiver Specifications,”

and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening

of the receive template shown in Figure 54 and Table 65. Note that for this to occur, the test signal must

have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)

about the mean zero crossi ng. Eye template measurement requirements are as defined above. Random

jitter is calibrated using a high pass filter with a low fr equency corner at 20 MHz and a 20 dB/decade

roll-off below this . The re quired sinusoida l jitter spec ified in Sect ion 17.7, “Recei ver Specifi cati ons , ” is

then added to the signal and th e test load is replaced by the receiver being tested.

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Freescale Semiconductor 87

Pa ck ag e D es cr iptio n

18 Package Description

This section details package parameters, pin assignments, and dimensions.

1 8. 1 Packag e Par ame ters

The package parameters for both the HiCTE FC-CBGA and FC-PBGA ar e as provided in Table 66.

Table 66. Package Parameters

Parameter CBGA1PBGA2

Package outli ne 29 m m × 29 mm 29 mm × 29 mm

Interconnects 783 783

Ball pit ch 1 mm 1 mm

Ball diameter (typical) 0.6 mm 0.6 mm

Solder ball 62% Sn

36% Pb

2% Ag

62% Sn

36% Pb

2% Ag

Solder ball (l ead-free) 95% Sn

4.5% Ag

0.5% Cu

96.5% Sn

3.5% Ag

Notes:

1. The HiCTE FC-CBGA package is availabl e on only Version 2.0 of the devi ce.

2. The FC-PBGA package is available on only Vers ion 2.1.1 and 2.1.2 of the

device.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

88 Freescale Semiconductor

Package Description

18.2 Mechanical Dimensions of the HiCTE FC-CBGA and FC-PBGA

with Full Lid

Figure 55 shows the mechanical dimensions and bottom surface nomenclature for both the MP C8548E

HiCTE FC-CBGA and FC-PBGA package with full lid.

Figure 55. Mechanical Dimensions and Bottom S urface Nom enclature of the HiCTE

FC-CBGA and FC-PBGA with Full Lid

Notes:

1. All dim e n si o ns ar e in mill im e ters.

2. Dimensioning and tol erancing per ASME Y14.5M -1994.

3. Max imum solder ball di am eter measured par allel to datu m A.

4. Datum A, the seating plane, is determined by the spherical crowns of the sol der balls.

5. Parallelism measurement shal l exclu de any e ffect of mark on top surface of package.

6. All dimensi ons are symmetric across the package center lines unless dimensioned otherwise.

7. Package code summary:

•PBGA 8423

•CBGA 5112

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 89

Pa ck ag e D es cr iptio n

18.3 Pinout Listings

NOTE

The DMA_DACK[0:1] and TEST_SEL/TEST_SEL pins must be set to a

proper state during POR configuration. Please refer to the pinlist table of the

individual device for more details.

For MP C8548/47/45, GPIOs a re still available on

PCI1_AD[63:32]/PC2_AD[31:0] pins if they are not used f or PCI

functionality.

For MPC8545/43, eTSEC does not support 16 bit FIFO mode.

Table 67 provides the pinout listing for the MPC8548E 783 FC-PBGA package.

Table 67. MPC8548E Pinout Listing

Signal Package Pin Number Pin Type Power

Supply Notes

PCI1 and PCI2 (One 64-Bit or Two 32-Bit)

PCI1_AD[63:32]/PCI2_AD[31:0] AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18 , AC17, AD16, AE16,

Y17, AC18, AB18, AA19, AB19, AB21, AA20,

A C20, AB20, AB22, AC2 2, AD21, AB23, AF23,

AD23, AE23, AC23, AC24

I/O OVDD 17

PCI1_AD[31:0] AH6, AE7, AF7, A G7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, A G12, AH12 , AB13, AA12,

A C13, AE13, Y14, W13, AG 13, V14, AH13,

AC14, Y15, AB15

I/O OVDD 17

PCI1_C_BE[7:4]/PCI2_C_BE[3:0] AF15, AD14, AE15, AD15 I/ O OVDD 17

PCI1_C_BE[3:0 ] AF9, AD11, Y12, Y13 I /O OVDD 17

PCI1_PAR64/PCI2_PAR W15 I/O OVDD

PCI1_GNT[4:1 ] AG6, AE6, AF5, AH5 O OVDD 5, 9, 35

PCI1_GNT0 AG5 I/O OVDD —

PCI1_IRDY AF11 I/O OVDD 2

PCI1_PAR AD12 I/O OVDD —

PCI1_PERR AC12 I/O OVDD 2

PCI1_SERR V13 I/O OVDD 2, 4

PCI1_STOP W12 I/O OVDD 2

PCI1_TRDY AG11 I/O OVDD 2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

90 Freescale Semiconductor

Package Description

PCI1_REQ[4:1] AH 2 , AG4, AG3, AH 4 I OVDD —

—

PCI1_REQ0 AH3 I/O OVDD —

PCI1_CLK AH26 I OVDD 39

PCI1_DEVSEL AH11 I/O OVDD 2

PCI1_FRAME AE11 I/O OVDD 2

PCI1_IDSEL AG9 I OVDD —

PCI1_REQ64/PCI2_FRAME AF14 I/O OVDD 2, 5, 1 0

PCI1_ACK64/PCI2_DEVSEL V15 I/O OVDD 2

PCI2_CLK AE28 I OVDD 39

PCI2_IRDY AD26 I/O OVDD 2

PCI2_PERR AD25 I/O OVDD 2

PCI2_GNT[4:1] AE26, AG24, AF25, AE25 O OVDD 5, 9, 35

PCI2_GNT0 AG25 I/O OVDD —

PCI2_SERR AD24 I/O OVDD 2, 4

PCI2_STOP AF24 I/O OVDD 2

PCI2_TRDY AD27 I/O OVDD 2

PCI2_REQ[4:1] AD28 , AE27, W17, AF26 I OVDD —

PCI2_REQ0 AH25 I/O OVDD —

DDR SDRAM Memory Interface

MDQ[0:63] L18, J18, K14, L13, L19, M1 8, L15, L14, A1 7,

B17, A13, B12, C18, B18, B13, A12, H18, F18,

J14, F15, K19, J19, H16, K15, D17, G16, K13,

D14, D18, F17, F14, E14, A7, A6, D5, A4, C8,

D7, B5, B 4, A2, B1 , D1, E4, A3, B2, D2, E3, F3,

G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3,

J2, L1, M6

I/O GVDD —

MECC[0:7] H13, F13, F11, C11, J13 , G13, D12, M12 I/O GVDD —

MDM[0: 8] M17, C16, K17, E16, B6, C4, H4, K1, E13 O GVDD —

MDQS[0:8] M15, A16, G17, G14, A5, D3, H1, L2, C13 I/O GVDD —

MDQS[ 0:8] L17, B16, J16, H14, C6, C2, H3, L4, D13 I/O GVDD —

MA[0:15] A8, F9, D9 , B9, A9, L10, M10, H10, K10, G10,

B8, E10, B10, G6, A10, L11 OGV

DD —

MBA[0:2] F7, J7, M11 O GVDD —

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 91

Pa ck ag e D es cr iptio n

MWE E7 O GVDD —

MCAS H7 O GVDD —

MRAS L8 O GVDD —

MCKE[0:3] F10, C10, J11, H11 O GVDD 11

MCS[0:3] K8, J8, G8, F8 O GVDD —

MCK[0:5] H9, B15, G2, M9, A14, F1 O GVDD —

MCK[0:5 ] J 9, A15, G1 , L9, B14, F2 O GVDD —

MODT[0:3] E6, K6, L7, M7 O GVDD —

MDIC[0:1] A19, B19 I /O G V DD 36

Local Bus Controller Interface

LAD[0:31] E27, B20, H19, F25, A20, C19, E28, J 23, A25,

K 22, B28, D27 , D19, J22, K20, D28, D25, B25,

E22, F22, F21, C25, C22, B23, F20, A23, A22,

E19, A21, D21, F19, B21

I/O BVDD —

LDP[0:3] K21, C28, B26, B22 I/O BVDD —

LA[27] H21 O BVDD 5, 9

LA[28:31] H20, A27, D26, A28 O BVDD 5, 7, 9

LCS[0:4] J25, C20, J24, G26 , A26 O BVDD

LCS5/DMA_DREQ2 D23 I/O BVDD 1

LCS6/DMA_DACK2 G20 O BVDD 1

LCS7/DMA_DDONE2 E21 O BVDD 1

LWE0/LBS0/LSDDQM[0] G25 O BVDD 5, 9

LWE1/LBS1/LSDDQM[1] C23 O BVDD 5, 9

LWE2/LBS2/LSDDQM[2] J21 O BVDD 5, 9

LWE3/LBS3/LSDDQM[3] A24 O BVDD 5, 9

LALE H24 O BVDD 5, 8, 9

LBCTL G27 O BVDD 5, 8, 9

LGPL0/LSDA10 F23 O BVDD 5, 9

LGPL1/LSDWE G22 O BVDD 5, 9

LGPL2/LOE/LSDRAS B27 O BVDD 5, 8, 9

LGPL3/LSDCAS F24 O BVDD 5, 9

LGPL4/LGTA/LUPWAIT/LPBSE H23 I/O BVDD —

LGPL5 E26 O BVDD 5, 9

LCKE E24 O BVDD —

LC LK[0:2] E23, D24, H22 O BVDD —

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

92 Freescale Semiconductor

Package Description

LSYNC_IN F27 I BVDD —

LSYNC_OUT F28 O BVDD —

DMA

DMA_DACK[0:1] A D3, A E 1 O OVDD 5, 9,

102

DMA_DREQ[0:1] AD4, AE2 I OVDD —

DMA_DDONE[0 :1] AD2, AD1 O OVDD —

Programmable Interrupt Controller

UDE AH16 I OVDD —

MCP AG19 I OVDD —

IRQ[0: 7] AG23, AF18, AE18, AF20, A G18, AF17, AH24,

AE20 IOV

DD —

IRQ[8] AF19 I OVDD —

IRQ[9]/DMA_DREQ3 AF21 I OVDD 1

IRQ[10]/DMA_DACK3 AE19 I/O OVDD 1

IRQ[11]/DMA_DDONE3 AD20 I/O OVDD 1

IRQ_OUT AD18 O OVDD 2, 4

Ethernet Management Interf ace

EC_MDC AB9 O OVDD 5, 9

EC_MDIO AC8 I/O OVDD —

Gigabi t Ref erence Clock

EC_GTX_CLK125 V11 I LVDD —

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_RXD[7:0] R5, U1, R3, U2, V3, V1, T3, T2 I LVDD —

TSEC1_TXD[7: 0] T10, V7, U10, U5, U4, V6, T5, T8 O LVDD 5, 9

TSEC1_COL R4 I LVDD —

TSEC1_CRS V5 I/O LVDD 20

TSEC1_GTX_CLK U7 O LVDD —

TSEC1_RX_CLK U3 I LVDD —

TSEC1_RX_DV V2 I LVDD —

TSEC1_RX_ER T1 I LVDD —

TSEC1_TX_CLK T6 I LVDD —

TSEC1_TX_EN U9 O LVDD 30

TSEC1_TX_ER T7 O LVDD —

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 93

Pa ck ag e D es cr iptio n

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

TSEC2_RXD[7:0] P2, R2, N1, N2, P3, M2, M1, N3 I LVDD —

TSEC2_TXD[7: 0] N9, N10, P8, N7, R9, N5, R8, N6 O LVDD 5, 9, 33

TSEC2_COL P1 I LVDD —

TSEC2_CRS R6 I/O LVDD 20

TSEC2_GTX_CLK P6 O LVDD

TSEC2_RX_CLK N4 I LVDD —

TSEC2_RX_DV P5 I LVDD —

TSEC2_RX_ER R1 I LVDD —

TSEC2_TX_CLK P10 I LVDD —

TSEC2_TX_EN P7 O LVDD 30

TSEC2_TX_ER R10 O LVDD 5, 9, 33

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

TSEC3_TXD[3: 0] V8, W10, Y10, W7 O TVDD 5, 9, 29

TSEC3_RXD[3:0] Y1, W3, W5, W4 I TVDD —

TSEC3_GTX_CLK W8 O TVDD —

TSEC3_RX_CLK W2 I TVDD —

TSEC3_RX_DV W1 I TVDD —

TSEC3_RX_ER Y2 I TVDD —

TSEC3_TX_CLK V10 I TVDD —

TSEC3_TX_EN V9 O TVDD 30

Three-Speed Ethernet Controller (Gigabit Ethernet 4)

TSEC4_TXD[3:0] /TSEC3_TXD[7:4] AB8, Y7, AA7, Y8 O TVDD 1, 5, 9,

TSEC4_RXD[3: 0]/ TSEC3_RXD[ 7:4] AA 1, Y3, AA2, AA4 I TVDD 1

TSEC4_GTX_CLK AA5 O TVDD —

TSEC4_RX_CLK/TSEC3_COL Y5 I TVDD 1

TSEC4_RX_DV/TSEC3_CRS AA3 I/O TVDD 1, 31

TSEC4_TX_EN/TSEC3_TX_ER AB6 O TVDD 1, 30

DUART

UART_CTS[0 :1 ] AB3, AC 5 I OVDD —

UART_RTS[ 0 :1 ] AC6 , A D 7 O OVDD —

UART _ S I N [0 :1 ] AB 5 , AC7 I OV DD —

UART_SOUT[0: 1] AB7, AD8 O OVDD —

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

94 Freescale Semiconductor

Package Description

I2C interfa ce

IIC1_SCL AG22 I/O OVDD 4, 27

IIC1_SDA AG21 I/O OVDD 4, 27

IIC2_SCL AG15 I/O OVDD 4, 27

IIC2_SDA AG14 I/O OVDD 4, 27

SerDes

SD_RX[0:7] M28, N26, P28, R26, W26, Y28, AA26, AB28 I XVDD —

SD_RX[0: 7] M27, N25, P27, R25, W25, Y27, AA25, AB27 I XV DD —

SD_TX[0:7] M22, N20 , P22, R20, U20, V22, W20, Y22 O XVDD —

SD_TX[0:7] M23, N21 , P23, R21, U21, V23, W21, Y23 O XVDD —

SD_PLL_TPD U28 O XVDD 24

SD_REF_CLK T28 I XVDD 3

SD_REF_CLK T27 I XVDD 3

Reserv ed AC1, AC3 — — 2

Reserv ed M26, V28 — — 32

Reserv ed M25, V27 — — 34

Reserved M20, M21, T22, T23 — — 38

General-Pur pose Output

GPOUT[2 4:31] K26, K25, H27, G28, H25, J26, K24, K2 3 O BVDD —

System Control

HRESET AG17 I OVDD —

HRESET_REQ AG16 O OVDD 29

SRESET AG20 I OVDD —

CKSTP_IN AA9 I OVDD —

CKSTP_OUT AA8 O OVDD 2, 4

Debug

TRIG_IN AB2 I OVDD —

TRIG_OUT/READY/QUIESCE AB1 O OVDD 6, 9,

19, 29

MSRCID[0:1] AE4, AG2 O OV DD 5, 6, 9

MSRCID[2:4] AF3, AF1, AF2 O OVDD 6, 19,

MDVAL AE5 O OVDD 6

CLK_OUT AE21 O OVDD 11

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 95

Pa ck ag e D es cr iptio n

Clock

RTC AF16 I OVDD —

SYSCLK AH17 I OVDD —

JTAG

TCK AG28 I OVDD —

TDI AH28 I OVDD 12

TDO AF28 O OVDD 11

TMS AH27 I OVDD 12

TRST AH23 I OVDD 12

DFT

L1_TSTCLK AC25 I OVDD 25

L2_TSTCLK AE22 I OVDD 25

LSSD_MODE AH20 I OVDD 25

TEST_SEL AH14 I OVDD 25

Thermal Management

THERM0 AG1 — — 14

THERM1 AH1 — — 14

Power Management

ASLEEP AH18 O OVDD 9, 19,

Power and Ground Signals

GND A11, B7, B24, C1, C3, C5, C12, C15, C26, D8,

D11, D16, D20, D22, E1, E5, E9, E12, E15,

E17, F4, F26, G 12, G15, G18, G21, G24, H2,

H6, H8, H28, J4, J12, J15, J17, J27, K7, K9,

K11, K27, L3, L5, L12, L16, N11, N13, N15,

N17, N19, P4, P9, P12, P14, P16, P18, R11,

R13, R15, R17, R19, T4, T12, T14, T16, T1 8,

U8, U11, U13, U15, U17, U19, V4, V12, V18,

W6, W19, Y4, Y9, Y11, Y19 , AA6, AA1 4, AA17,

AA22, AA23, AB4, A C2, AC11, A C19, AC26,

AD5, AD9, AD22, AE3, AE14, AF6, AF10,

AF13, AG8, AG27, K28, L24, L26, N24, N27,

P25, R28, T24, T26, U24, V2 5, W28, Y24, Y26,

AA24, AA27, AB25, A C28, L21, L23, N22 , P20,

R23, T21, U22, V20, W23, Y21, U27

———

OVDD V16, W11, W14, Y18, AA13, AA21, AB11,

AB17, AB24, AC4, AC9, AC21, AD6, AD13,

AD17, AD19, AE10, AE8, AE24, AF4, AF12,

AF22, AF27, AG 26

Pow er for PCI

and other

standards

(3.3 V)

OVDD —

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

96 Freescale Semiconductor

Package Description

LVDD N8, R7, T9, U6 Power for

TSEC1 and

TSEC2

(2.5 V, 3.3 V)

LVDD —

TVDD W9, Y6 P ower for

TSEC3 and

TSEC4

(2,5 V, 3.3 V)

TVDD —

GVDD B3, B11, C7, C9 , C14, C17, D4, D6, D10, D15,

E2, E8, E11, E18, F5, F12, F16, G3, G7, G9,

G11, H5, H12, H15, H17, J10, K3, K12, K16,

K18, L6, M4, M8, M13

Power for

DDR1 and

DDR2 DRAM

I/O voltage

(1.8 V, 2.5)

GVDD —

BVDD C21, C24, C27, E20, E25, G19, G23 , H26, J20 Power for local

bus (1.8 V,

2.5 V, 3.3 V)

BVDD —

VDD M19, N12, N14, N16, N18, P11, P13, P15, P17,

P19, R12, R14, R16, R18, T11, T13, T15, T17,

T19, U12, U14, U16, U18, V17, V19

P o wer f or c ore

(1.1 V) VDD —

SVDD L25, L27, M24 , N28, P24, P26, R24, R27, T25,

V24, V26, W24, W27, Y25, AA28, AC 27 Core Power for

SerDes

transceivers

(1.1 V )

SVDD —

XVDD L20, L22, N23, P21, R22, T20, U23, V21, W22,

Y20 P ad P ower for

SerDes

transceivers

(1.1 V )

XVDD —

A VDD_LBIU J28 Power for local

bus PLL

(1.1 V )

—26

AVDD_PCI1 AH21 Power for PCI1

PLL

(1.1 V )

—26

AVDD_PCI2 AH22 Power for PCI2

PLL

(1.1 V )

—26

AVDD_CORE AH15 Power for e500

PLL (1.1 V) —26

AVDD_PLA T AH19 Power for CCB

PLL (1.1 V) —26

AVDD_SRDS U25 Power for

SRDSPLL

(1.1 V )

—26

SENSEVDD M14 O VDD 13

SENSEVSS M16 — — 13

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 97

Pa ck ag e D es cr iptio n

Analog Signals

MVREF A18 I

Reference

vo lt age signal

for DDR

MVREF —

SD_IMP_CAL_RX L28 I 200Ω to

GND —

SD_IMP_CAL_TX AB26 I 100Ω to

GND —

SD_PLL_TPA U26 O — 24

Notes:

1. All mul ti plexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is l ist ed only once in th e

local bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.

2. Recommend a weak pull -up resistor (2–10 kΩ) be placed on this pin t o OVDD.

3. A vali d clock must be pro vided at POR if TSEC4_TXD[2] is set = 1.

4. This pin is an open dr ain signal.

5. This pi n is a re set configuration pin. It has a weak internal pull-up P-F ET which is enabled only when the processor is in the

reset stat e. This pull -up i s designed suc h that it ca n be o v erpow ered b y an e xt ernal 4. 7-kΩ p ull- down r esist or . Ho we v er, if t he

signal is i ntended to be high afte r reset, and if there i s any device on the net whi ch might pull down the value of the net at

reset, then a pullup or active driver is needed.

6. Treat these pins as no connects (NC ) unless using debug addr ess functionality.

7. The v al ue of L A[28:31] d uring r eset se ts the CCB cloc k to SYSCLK PLL r ati o . The se p ins r equire 4.7-kΩ pul l-u p or pul l-do wn

resistors. See Section 19.2, “CCB/SYSCLK PLL Ratio.”

8. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins requir e 4.7-kΩ

pull-up or pull-down resistors. See the Secti on 19.3, “e500 Core PLL Rati o.”

9. Functionally, this pin i s an output, but structurall y it is a n I/O because it either samples configuration input during reset or

because it has other man ufact uring test functions . T his pin wi ll therefore be described as an I/O fo r boundary scan.

10.This pin functionally requi res a pull-up resistor, b ut du ring reset it is a configuration inpu t th at controls 32- vs. 64-bit PCI

operation. Therefore, it mus t be act ivel y dri ven low during reset b y reset logic if the device is to be confi gured to be a 64-bit

PCI device. Refer to the

PCI Specification

11.This output is acti vely driven dur ing reset rather than being three-stated during reset.

12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.

13.These pins are connect ed to the VDD/GND plan es internall y and ma y be used b y the cor e pow er suppl y to impro v e tra c king

and regulation.

14.Internal thermally sensitive resistor.

15.No connections should be made to these pins if they are not used.

16.These pins are not connected f or any use.

17.PCI specifi ca tions recommend t hat a weak pull-up r esistor (2– 10 kΩ) be placed on the hig her order pins to O VDD when using

64-bit buff er mod e (pi ns PCI_AD[ 63:32] and PCI1_ C _BE[7:4]).

19.If this pin is conne cted to a dev ic e that pu lls do wn durin g reset, an e xt ern al pul l-up is r equi red to d riv e this p in to a s afe state

during reset.

20.This pin is onl y an output in FIFO mode when used as Rx flo w control.

24.Do not connect.

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

98 Freescale Semiconductor

Package Description

25.These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OV DD for normal machi ne operation.

26.Independent supplies deri ved from board VDD.

27.Recommend a pull-up resistor (~1 kΩ) be pl aced on this pin to OVDD.

29. The f ollowing pi ns m ust NOT be pul led down duri ng power-o n reset: TSEC3 _TXD[3], T SEC4_TXD3/TSEC3_TXD7,

HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.

30.This pin r equires an external 4.7 -kΩ pull-down resi stor to p re vent PHY from seein g a vali d transmi t enabl e before it is a ctive ly

driven.

31.This pin is onl y an output in eTSEC3 FIFO mode when used as Rx flo w control.

32.These pins should be connected to XVDD.

33.TSEC2_TXD1, TSEC2_TX_ER are multiplexed as cfg_dram_type[0:1]. They must be val id at power-up, even before

HRESET assertion.

34.These pins should be pulled to ground through a 300-Ω (±10%) resistor.

35.When a PCI b lock i s dis abled, either the POR config pi n that sel ects b etween internal and external arbiter must be pulle d

down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCI

_AD pins as ‘no

connect’ or terminated throu gh 2–10 kΩ pull-up resistors wit h the default of inter nal arbiter if the PCI

_AD pins are not

connect ed to any other PCI device. The PCI bl ock will dri ve the PCI

_AD pins i f it is configured to be the PCI arbiter—throug h

POR conf ig pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is

any other PCI device connected on the b us.

36.MDIC0 is g rounded t hro ugh an 18.2-Ω pr ecisi on 1% resi st or and MDIC1 i s co nnected t o GVDD t hrough an 18. 2-Ω precisio n

1% resistor. These pins are used for automatic cali bration of the DDR IOs.

38.These pins should be left floating.

39. If PCI1 or PCI2 i s configured as PC I asynchronous mode, a v alid clock m ust be provided on pin PCI1_CLK or PCI2_CLK.

Ot h er wise the p ro c ess o r w ill n o t boot up.

40.These pins should be connected to GND.

101.This pin r equires an e xternal 4. 7-kΩ resistor to GND.

102.F or Rev. 2.x silicon, DMA_D A CK[0:1] m ust be 0b11 during POR co nfiguration; f or re v . 1 .x silicon, the pin v alues during POR

configuration are don’t care.

103.If these pi ns are not used as GPI N

(gener al-pu rpose input), the y shoul d be pulle d low (t o GND) or high ( to LVDD) thro u gh

2–10 kΩ resistors.

104.These should be pulled low to GND throu gh 2–10 kΩ r e sistors if t hey are not used.

105.These should be pulled low or high to LVDD through 2–10 kΩ resistors if they are not used.

106.F or re v. 2.x sil icon, DMA_DA CK[0: 1] m ust be 0b10 du ring POR c onf igur ation; for re v. 1.x si licon, t he pi n v alue s durin g POR

configuration are don’t care.

107.F or re v. 2.x sil icon, DMA_DA CK[0: 1] m ust be 0b01 du ring POR c onf igur ation; for re v. 1.x si licon, t he pi n v alue s durin g POR

configuration are don’t care.

108.F or re v. 2.x sil icon, DMA_DA CK[0: 1] m ust be 0b11 du ring POR c onf igur ation; for re v. 1.x si licon, t he pi n v alue s durin g POR

configuration are don’t care.

109.This is a test signal for factory use only and must be pulled down (100 Ω – 1 kΩ) to GND for normal machine op eration.

110.These pins should be pull ed high to OVDD through 2–10 kΩ resistors.

111.If thes e pins are not use d as GPIN

(gen er al-purpose i nput), the y s hould be pul led l ow (t o GND) or high (t o O VDD) t hrough

2–10 kΩ resistors.

112.This pin must not be pulle d down duri ng PO R configurati on.

113.These should be pulled low or high to OVDD through 2–10 kΩ resistors.

Table 67. MPC8548E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 99

Pa ck ag e D es cr iptio n

Table 68 provides the pin-out listing for the MPC8547E 783 FC-PBGA package.

NOTE

All note references in the following table use the same numbers as those for

Table 67. The re ader should refer to Table 67 for the meanings of these

notes.

Table 68. MPC8547E Pinout Listing

Signal Package Pin Number Pin Type Power

Supply Notes

PCI1 (One 64-Bit or One 32-Bit)

PCI1_AD[63:32] AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18 , AC17, AD16, AE16,

Y17, AC18, AB18, AA19, AB19, AB21, AA20,

A C20, AB20, AB22, AC2 2, AD21, AB23, AF23,

AD23, AE23, AC23, AC24

I/O OVDD 17

PCI1_AD[31:0] AH6, AE7, AF7, A G7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, A G12, AH12 , AB13, AA12,

A C13, AE13, Y14, W13, AG 13, V14, AH13,

AC14, Y15, AB15

I/O OVDD 17

PCI1_C_BE[7:4] AF15, AD14, AE15, AD15 I/O OV DD 17

PCI1_C_BE[3:0 ] AF9, AD11, Y12, Y13 I /O OVDD 17

PCI1_PAR64 W15 I/O OVDD —

PCI1_GNT[4:1 ] AG6, AE6, AF5, AH5 O OVDD 5, 9, 35

PCI1_GNT0 AG5 I/O OVDD —

PCI1_IRDY AF11 I/O OVDD 2

PCI1_PAR AD12 I/O OVDD —

PCI1_PERR AC12 I/O OVDD 2

PCI1_SERR V13 I/O OVDD 2, 4

PCI1_STOP W12 I/O OVDD 2

PCI1_TRDY AG11 I/O OVDD 2

PCI1_REQ[4:1] AH 2 , AG4, AG3, AH 4 I OV DD —

PCI1_REQ0 AH3 I/O OVDD —

PCI1_CLK AH26 I OVDD 39

PCI1_DEVSEL AH11 I/O OVDD 2

PCI1_FRAME AE11 I/O OVDD 2

PCI1_IDSEL AG9 I OVDD —

PCI1_REQ64 AF14 I/O OVDD 2, 5,10

PCI1_ACK64 V15 I/O OVDD 2

Reserved AE28 — — 2

Reserved AD26 — — 2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

100 Freescale Sem iconductor

Package Description

Reserved AD25 — — 2

Reserved AE26 — — 2

cfg_pci1_clk AG24 I OVDD 5

Reserved AF25 — — 101

Reserved AE25 — — 2

Reserved AG25 — — 2

Reserved AD24 — — 2

Reserved AF24 — — 2

Reserved AD27 — — 2

Reserved AD28, AE27, W17, AF26 — — 2

Reserved AH25 — — 2

DDR SDRAM Memory Interface

MDQ[0:63] L18, J18, K14, L13, L19, M1 8, L15, L14, A1 7,

B17, A13, B12, C18, B18, B13, A12, H18, F18,

J14, F15, K19, J19, H16, K15, D17, G16, K13,

D14, D18, F17, F14, E14, A7, A6, D5, A4, C8,

D7, B5, B 4, A2, B1 , D1, E4, A3, B2, D2, E3, F3,

G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3,

J2, L1, M6

I/O GVDD —

MECC[0:7] H13, F13, F11, C11, J13 , G13, D12, M12 I/O GVDD —

MDM[0: 8] M17, C16, K17, E16, B6, C4, H4, K1, E13 O GVDD —

MDQS[0:8] M15, A16, G17, G14, A5, D3, H1, L2, C13 I/O GVDD —

MDQS[ 0:8] L17, B16, J16, H14, C6, C2, H3, L4, D13 I/O GVDD —

MA[0:15] A8, F9, D9 , B9, A9, L10, M10, H10, K10, G10,

B8, E10, B10, G6, A10, L11 OGV

DD —

MBA[0:2] F7, J7, M11 O GVDD —

MWE E7 O GVDD —

MCAS H7 O GVDD —

MRAS L8 O GVDD —

MCKE[0:3] F10, C10, J11, H11 O GVDD 11

MCS[0:3] K8, J8, G8, F8 O GVDD —

MCK[0:5] H9, B15, G2, M9, A14, F1 O GVDD —

MCK[0:5 ] J 9, A15, G1 , L9, B14, F2 O GVDD —

MODT[0:3] E6, K6, L7, M7 O GVDD —

MDIC[0:1] A19, B19 I /O G V DD 36

Table 68. MPC8547E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 101

Pa ck ag e D es cr iptio n

Local Bus Controller Interface

LAD[0:31] E27, B20, H19, F25, A20, C19, E28, J 23, A25,

K 22, B28, D27 , D19, J22, K20, D28, D25, B25,

E22, F22, F21, C25, C22, B23, F20, A23, A22,

E19, A21, D21, F19, B21

I/O BVDD —

LDP[0:3] K21, C28, B26, B22 I/O BVDD —

LA[27] H21 O BVDD 5, 9

LA[28:31] H20, A27, D26, A28 O BVDD 5, 7, 9

LCS[0:4] J25, C20, J24, G26 , A26 O BVDD —

LCS5/DMA_DREQ2 D23 I/O BVDD 1

LCS6/DMA_DACK2 G20 O BVDD 1

LCS7/DMA_DDONE2 E21 O BVDD 1

LWE0/LBS0/LSDDQM[0] G25 O BVDD 5, 9

LWE1/LBS1/LSDDQM[1] C23 O BVDD 5, 9

LWE2/LBS2/LSDDQM[2] J21 O BVDD 5, 9

LWE3/LBS3/LSDDQM[3] A24 O BVDD 5, 9

LALE H24 O BVDD 5, 8, 9

LBCTL G27 O BVDD 5, 8, 9

LGPL0/LSDA10 F23 O BVDD 5, 9

LGPL1/LSDWE G22 O BVDD 5, 9

LGPL2/LOE/LSDRAS B27 O BVDD 5, 8, 9

LGPL3/LSDCAS F24 O BVDD 5, 9

LGPL4/LGTA/LUPWAIT/LPBSE H23 I/O BVDD —

LGPL5 E26 O BVDD 5, 9

LCKE E24 O BVDD —

LC LK[0:2] E23, D24, H22 O BVDD —

LSYNC_IN F27 I BVDD —

LSYNC_OUT F28 O BVDD —

DMA

DMA_DACK[0:1] A D3, A E 1 O OVDD 5, 9,

107

DMA_DREQ[0:1] AD4, AE2 I OVDD —

DMA_DDONE[0 :1] AD2, AD1 O OVDD —

Programmable Interrupt Controller

UDE AH16 I OVDD —

MCP AG19 I OVDD —

Table 68. MPC8547E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

102 Freescale Sem iconductor

Package Description

IRQ[0: 7] AG23, AF18, AE18, AF20, A G18, AF17, AH24,

AE20 IOV

DD —

IRQ[8] AF19 I OVDD —

IRQ[9]/DMA_DREQ3 AF21 I OVDD 1

IRQ[10]/DMA_DACK3 AE19 I/O OVDD 1

IRQ[11]/DMA_DDONE3 AD20 I/O OVDD 1

IRQ_OUT AD18 O OVDD 2, 4

Ethernet Management Interf ace

EC_MDC AB9 O OVDD 5, 9

EC_MDIO AC8 I/O OVDD —

Gigabi t Ref erence Clock

EC_GTX_CLK125 V11 I LVDD —

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_RXD[7:0] R5, U1, R3, U2, V3, V1, T3, T2 I LVDD —

TSEC1_TXD[7: 0] T10, V7, U10, U5, U4, V6, T5, T8 O LVDD 5, 9

TSEC1_COL R4 I LVDD —

TSEC1_CRS V5 I/O LVDD 20

TSEC1_GTX_CLK U7 O LVDD —

TSEC1_RX_CLK U3 I LVDD —

TSEC1_RX_DV V2 I LVDD —

TSEC1_RX_ER T1 I LVDD —

TSEC1_TX_CLK T6 I LVDD —

TSEC1_TX_EN U9 O LVDD 30

TSEC1_TX_ER T7 O LVDD —

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

TSEC2_RXD[7:0] P2, R2, N1, N2, P3, M2, M1, N3 I LVDD —

TSEC2_TXD[7: 0] N9, N10, P8, N7, R9, N5, R8, N6 O LVDD 5, 9, 33

TSEC2_COL P1 I LVDD —

TSEC2_CRS R6 I/O LVDD 20

TSEC2_GTX_CLK P6 O LVDD —

TSEC2_RX_CLK N4 I LVDD —

TSEC2_RX_DV P5 I LVDD —

TSEC2_RX_ER R1 I LVDD —

TSEC2_TX_CLK P10 I LVDD —

TSEC2_TX_EN P7 O LVDD 30

Table 68. MPC8547E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 103

Pa ck ag e D es cr iptio n

TSEC2_TX_ER R10 O LVDD 5, 9, 33

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

TSEC3_TXD[3: 0] V8, W10, Y10, W7 O TVDD 5, 9, 29

TSEC3_RXD[3:0] Y1, W3, W5, W4 I TVDD —

TSEC3_GTX_CLK W8 O TVDD —

TSEC3_RX_CLK W2 I TVDD —

TSEC3_RX_DV W1 I TVDD —

TSEC3_RX_ER Y2 I TVDD —

TSEC3_TX_CLK V10 I TVDD —

TSEC3_TX_EN V9 O TVDD 30

Three-Speed Ethernet Controller (Gigabit Ethernet 4)

TSEC4_TXD[3:0] /TSEC3_TXD[7:4] AB8, Y7, AA7, Y8 O TVDD 1, 5, 9,

TSEC4_RXD[3: 0]/ TSEC3_RXD[ 7:4] AA 1, Y3, AA2, AA4 I TVDD 1

TSEC4_GTX_CLK AA5 O TVDD

TSEC4_RX_CLK/TSEC3_COL Y5 I TVDD 1

TSEC4_RX_DV/TSEC3_CRS AA3 I/O TVDD 1, 31

TSEC4_TX_EN/TSEC3_TX_ER AB6 O TVDD 1, 30

DUART

UART_CTS[0 :1 ] AB3, AC 5 I OVDD —

UART_RTS[ 0 :1 ] AC6 , A D 7 O OVDD —

UART _ S I N [0 :1 ] AB 5 , AC7 I OV DD —

UART_SOUT[0: 1] AB7, AD8 O OVDD —

I2C Interfa ce

IIC1_SCL AG22 I/O OVDD 4, 27

IIC1_SDA AG21 I/O OVDD 4, 27

IIC2_SCL AG15 I/O OVDD 4, 27

IIC2_SDA AG14 I/O OVDD 4, 27

SerDes

SD_RX[0:3] M28, N26, P28, R26 I XVDD —

SD_RX[0:3] M27, N25, P27, R25 I XVDD —

SD_TX[0:3] M22, N20, P22, R20 O XVDD —

SD_TX[0:3] M23, N21, P23, R21 O XVDD —

Reserved W26, Y28, AA26, AB28 — — 40

Reserved W25, Y27, AA25, AB27 — — 40

Table 68. MPC8547E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

104 Freescale Sem iconductor

Package Description

Reserved U20, V22, W20, Y22 — — 15

Reserved U21, V23, W21, Y23 — — 15

SD_PLL_TPD U28 O XVDD 24

SD_REF_CLK T28 I XVDD —

SD_REF_CLK T27 I XVDD —

Reserv ed AC1, AC3 — — 2

Reserv ed M26, V28 — — 32

Reserv ed M25, V27 — — 34

Reserved M20, M21, T22, T23 — — 38

General-Pur pose Output

GPOUT[2 4:31] K26, K25, H27, G28, H25, J26, K24, K2 3 O BVDD —

System Control

HRESET AG17 I OVDD —

HRESET_REQ AG16 O OVDD 29

SRESET AG20 I OVDD —

CKSTP_IN AA9 I OVDD —

CKSTP_OUT AA8 O OVDD 2, 4

Debug

TRIG_IN AB2 I OVDD —

TRIG_OUT/READY/QUIESCE AB1 O OVDD 6, 9,

19, 29

MSRCID[0:1] AE4, AG2 O OV DD 5, 6, 9

MSRCID[2:4] AF3, AF1, AF2 O OVDD 6, 19,

MDVAL AE5 O OVDD 6

CLK_OUT AE21 O OVDD 11

Clock

RTC AF16 I OVDD —

SYSCLK AH17 I OVDD —

JTAG

TCK AG28 I OVDD —

TDI AH28 I OVDD 12

TDO AF28 O OVDD 11

TMS AH27 I OVDD 12

TRST AH23 I OVDD 12

Table 68. MPC8547E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 105

Pa ck ag e D es cr iptio n

DFT

L1_TSTCLK AC25 I OVDD 25

L2_TSTCLK AE22 I OVDD 25

LSSD_MODE AH20 I OVDD 25

TEST_SEL AH14 I OVDD 25

Thermal Management

THERM0 AG1 — — 14

THERM1 AH1 — — 14

Power Management

ASLEEP AH18 O OVDD 9, 19,

Power and Ground Signals

GND A11, B7, B24, C1, C3, C5, C12, C15, C26, D8,

D11, D16, D20, D22, E1, E5, E9, E12, E15,

E17, F4, F26, G 12, G15, G18, G21, G24, H2,

H6, H8, H28, J4, J12, J15, J17, J27, K7, K9,

K11, K27, L3, L5, L12, L16, N11, N13, N15,

N17, N19, P4, P9, P12, P14, P16, P18, R11,

R13, R15, R17, R19, T4, T12, T14, T16, T1 8,

U8, U11, U13, U15, U17, U19, V4, V12, V18,

W6, W19, Y4, Y9, Y11, Y19 , AA6, AA1 4, AA17,

AA22, AA23, AB4, A C2, AC11, A C19, AC26,

AD5, AD9, AD22, AE3, AE14, AF6, AF10,

AF13, AG8, AG27, K28, L24, L26, N24, N27,

P25, R28, T24, T26, U24, V2 5, W28, Y24, Y26,

AA24, AA27, AB25, A C28, L21, L23, N22 , P20,

R23, T21, U22, V20, W23, Y21, U27

———

OVDD V16, W11, W14, Y18, AA13, AA21, AB11,

AB17, AB24, AC4, AC9, AC21, AD6, AD13,

AD17, AD19, AE10, AE8, AE24, AF4, AF12,

AF22, AF27, AG 26

Pow er for PCI

and other

standards

(3.3 V)

OVDD —

LVDD N8, R7, T9, U6 Power for

TSEC1 and

TSEC2

(2.5 V, 3.3 V)

LVDD —

TVDD W9, Y6 P ower for

TSEC3 and

TSEC4

(2,5 V, 3.3 V)

TVDD —

GVDD B3, B11, C7, C9 , C14, C17, D4, D6, D10, D15,

E2, E8, E11, E18, F5, F12, F16, G3, G7, G9,

G11, H5, H12, H15, H17, J10, K3, K12, K16,

K18, L6, M4, M8, M13

Power for

DDR1 and

DDR2 DRAM

I/O voltage

(1.8 V, 2.5 V)

GVDD —

Table 68. MPC8547E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

106 Freescale Sem iconductor

Package Description

BVDD C21, C24, C27, E20, E25, G19, G23 , H26, J20 Power for local

bus (1.8 V,

2.5 V, 3.3 V)

BVDD —

VDD M19, N12, N14, N16, N18, P11, P13, P15, P17,

P19, R12, R14, R16, R18, T11, T13, T15, T17,

T19, U12, U14, U16, U18, V17, V19

P o wer f or c ore

(1.1 V ) VDD —

SVDD L25, L27, M24 , N28, P24, P26, R24, R27, T25,

V24, V26, W24, W27, Y25, AA28, AC 27 Core power for

SerDes

transceivers

(1.1 V )

SVDD —

XVDD L20, L22, N23, P21, R22, T20, U23, V21, W22,

Y20 P ad P ower for

SerDes

transceivers

(1.1 V )

XVDD —

A VDD_LBIU J28 Power for local

bus PLL

(1.1 V )

—26

AVDD_PCI1 AH21 Power for PCI1

PLL

(1.1 V )

—26

AVDD_PCI2 AH22 Power for PCI2

PLL

(1.1 V )

—26

AVDD_CORE AH15 Power for e500

PLL (1.1 V) —26

AVDD_PLA T AH19 Power for CCB

PLL (1.1 V) —26

AVDD_SRDS U25 Power for

SRDSPLL

(1.1 V)

—26

SENSEVDD M14 O VDD 13

SENSEVSS M16 — — 13

Analog Signals

MVREF A18 I

Reference

vo lt age signal

for DDR

MVREF —

SD_IMP_CAL_RX L28 I 200 Ω to

GND —

SD_IMP_CAL_TX AB26 I 100 Ω to

GND —

SD_PLL_TPA U26 O — 24

Note : All note ref er ences in thi s tabl e use the same n umber s as th ose f or Table 67. The reader shou ld refer to Table 67 for the

meanings of these not es.

Table 68. MPC8547E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 107

Pa ck ag e D es cr iptio n

Table 69 provides the pin-out listing for the MPC8545E 783 FC-PBGA package.

NOTE

All note references in the following table use the same numbers as those for

Table 67. The re ader should refer to Table 67 for the meanings of these

notes.

Table 69. MPC8545E Pinout Listing

Signal Package Pin Number Pin Type Power

Supply Notes

PCI1 and PCI2 (One 64-Bit or Two 32-Bit)

PCI1_AD[63:32]/PCI2_AD[31:0] AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18 , AC17, AD16, AE16,

Y17, AC18, AB18, AA19, AB19, AB21, AA20,

A C20, AB20, AB22, AC2 2, AD21, AB23, AF23,

AD23, AE23, AC23, AC24

I/O OVDD 17

PCI1_AD[31:0] AH6, AE7, AF7, A G7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, A G12, AH12 , AB13, AA12,

A C13, AE13, Y14, W13, AG 13, V14, AH13,

AC14, Y15, AB15

I/O OVDD 17

PCI1_C_BE[7:4]/PCI2_C_BE[3:0] AF15, AD14, AE15, AD15 I/ O OVDD 17

PCI1_C_BE[3:0 ] AF9, AD11, Y12, Y13 I /O OVDD 17

PCI1_PAR64/PCI2_PAR W15 I/O OVDD —

PCI1_GNT[4:1 ] AG6, AE6, AF5, AH5 O OVDD 5, 9, 35

PCI1_GNT0 AG5 I/O OVDD —

PCI1_IRDY AF11 I/O OVDD 2

PCI1_PAR AD12 I/O OVDD —

PCI1_PERR AC12 I/O OVDD 2

PCI1_SERR V13 I/O OVDD 2, 4

PCI1_STOP W12 I/O OVDD 2

PCI1_TRDY AG11 I/O OVDD 2

PCI1_REQ[4:1] AH 2 , AG4, AG3, AH 4 I OV DD —

PCI1_REQ0 AH3 I/O OVDD —

PCI1_CLK AH26 I OVDD 39

PCI1_DEVSEL AH11 I/O OVDD 2

PCI1_FRAME AE11 I/O OVDD 2

PCI1_IDSEL AG9 I OVDD —

PCI1_REQ64/PCI2_FRAME AF14 I/O OVDD 2, 5, 1 0

PCI1_ACK64/PCI2_DEVSEL V15 I/O OVDD 2

PCI2_CLK AE28 I OVDD 39

PCI2_IRDY AD26 I/O OVDD 2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

108 Freescale Sem iconductor

Package Description

PCI2_PERR AD25 I/O OVDD 2

PCI2_GNT[4:1] AE26, AG24, AF25, AE25 O O VDD 5, 9, 35

PCI2_GNT0 AG25 I/O OVDD —

PCI2_SERR AD24 I/O OVDD 2,4

PCI2_STOP AF24 I/O OVDD 2

PCI2_TRDY AD27 I/O OVDD 2

PCI2_REQ[4:1] AD28 , AE27, W17, AF26 I OVDD —

PCI2_REQ0 AH25 I/O OVDD —

DDR SDRAM Memory Interface

MDQ[0:63] L18, J18, K14, L13, L19, M1 8, L15, L14, A1 7,

B17, A13, B12, C18, B18, B13, A12, H18, F18,

J14, F15, K19, J19, H16, K15, D17, G16, K13,

D14, D18, F17, F14, E14, A7, A6, D5, A4, C8,

D7, B5, B 4, A2, B1 , D1, E4, A3, B2, D2, E3, F3,

G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3,

J2, L1, M6

I/O GVDD —

MECC[0:7] H13, F13, F11, C11, J13 , G13, D12, M12 I/O GVDD —

MDM[0: 8] M17, C16, K17, E16, B6, C4, H4, K1, E13 O GVDD —

MDQS[0:8] M15, A16, G17, G14, A5, D3, H1, L2, C13 I/O GVDD —

MDQS[ 0:8] L17, B16, J16, H14, C6, C2, H3, L4, D13 I/O GVDD —

MA[0:15] A8, F9, D9 , B9, A9, L10, M10, H10, K10, G10,

B8, E10, B10, G6, A10, L11 OGV

DD —

MBA[0:2] F7, J7, M11 O GVDD —

MWE E7 O GVDD —

MCAS H7 O GVDD —

MRAS L8 O GVDD —

MCKE[0:3] F10, C10, J11, H11 O GVDD 11

MCS[0:3] K8, J8, G8, F8 O GVDD —

MCK[0:5] H9, B15, G2, M9, A14, F1 O GVDD —

MCK[0:5 ] J 9, A15, G1 , L9, B14, F2 O GVDD —

MODT[0:3] E6, K6, L7, M7 O GVDD —

MDIC[0:1] A19, B19 I /O G V DD 36

Local Bus Controller Interface

LAD[0:31] E27, B20, H19, F25, A20, C19, E28, J 23, A25,

K 22, B28, D27 , D19, J22, K20, D28, D25, B25,

E22, F22, F21, C25, C22, B23, F20, A23, A22,

E19, A21, D21, F19, B21

I/O BVDD —

LDP[0:3] K21, C28, B26, B22 I/O BVDD —

Table 69. MPC8545E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 109

Pa ck ag e D es cr iptio n

LA[27] H21 O BVDD 5, 9

LA[28:31] H20, A27, D26, A28 O BVDD 5, 7, 9

LCS[0:4] J25, C20, J24, G26 , A26 O BVDD —

LCS5/DMA_DREQ2 D23 I/O BVDD 1

LCS6/DMA_DACK2 G20 O BVDD 1

LCS7/DMA_DDONE2 E21 O BVDD 1

LWE0/LBS0/LSDDQM[0] G25 O BVDD 5, 9

LWE1/LBS1/LSDDQM[1] C23 O BVDD 5, 9

LWE2/LBS2/LSDDQM[2] J21 O BVDD 5, 9

LWE3/LBS3/LSDDQM[3] A24 O BVDD 5, 9

LALE H24 O BVDD 5, 8, 9

LBCTL G27 O BVDD 5, 8, 9

LGPL0/LSDA10 F23 O BVDD 5, 9

LGPL1/LSDWE G22 O BVDD 5, 9

LGPL2/LOE/LSDRAS B27 O BVDD 5, 8, 9

LGPL3/LSDCAS F24 O BVDD 5, 9

LGPL4/LGTA/LUPWAIT/LPBSE H23 I/O BVDD —

LGPL5 E26 O BVDD 5, 9

LCKE E24 O BVDD —

LC LK[0:2] E23, D24, H22 O BVDD —

LSYNC_IN F27 I BVDD —

LSYNC_OUT F28 O BVDD —

DMA

DMA_DACK[0:1] AD3, AE1 O OVDD 5, 9,

106

DMA_DREQ[0:1] AD4, AE2 I OVDD —

DMA_DDONE[0 :1] AD2, AD1 O OVDD —

Programmable Interrupt Controller

UDE AH16 I OVDD —

MCP AG19 I OVDD —

IRQ[0: 7] AG23, AF18, AE18, AF20, A G18, AF17, AH24,

AE20 IOV

DD —

IRQ[8] AF19 I OVDD —

IRQ[9]/DMA_DREQ3 AF21 I OVDD 1

IRQ[10]/DMA_DACK3 AE19 I/O OVDD 1

Table 69. MPC8545E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

110 Freescale Sem iconductor

Package Description

IRQ[11]/DMA_DDONE3 AD20 I/O OVDD 1

IRQ_OUT AD18 O OVDD 2, 4

Ethernet Management Interf ace

EC_MDC AB9 O OVDD 5, 9

EC_MDIO AC8 I/O OVDD —

Gigabi t Ref erence Clock

EC_GTX_CLK125 V11 I LVDD —

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_RXD[7:0] R5, U1, R3, U2, V3, V1, T3, T2 I LVDD —

TSEC1_TXD[7: 0] T10, V7, U10, U5, U4, V6, T5, T8 O LVDD 5, 9

TSEC1_COL R4 I LVDD —

TSEC1_CRS V5 I/O LVDD 20

TSEC1_GTX_CLK U7 O LVDD —

TSEC1_RX_CLK U3 I LVDD —

TSEC1_RX_DV V2 I LVDD —

TSEC1_RX_ER T1 I LVDD —

TSEC1_TX_CLK T6 I LVDD —

TSEC1_TX_EN U9 O LVDD 30

TSEC1_TX_ER T7 O LVDD —

GPIN[0:7] P2, R2, N1, N2, P3, M2, M1, N3 I LVDD 103

GPOUT[0:5 ] N9, N10, P8, N7, R9, N5 O LVDD —

cfg_dram_type0/GPOUT6 R8 O LVDD 5, 9

GPOUT7 N6 O LVDD —

Reserved P1 — — 104

Reserved R6 — — 104

Reserved P6 — — 15

Reserved N4 — — 105

FIFO1_RXC2 P5 I LVDD 104

Reserved R1 — — 104

Reserved P10 — — 105

FIFO1_TXC2 P7 O LVDD 15

cfg_dram_type1 R10 I LVDD 5

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

TSEC3_TXD[3: 0] V8, W10, Y10, W7 O TVDD 5, 9, 29

Table 69. MPC8545E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 111

Pa ck ag e D es cr iptio n

TSEC3_RXD[3:0] Y1, W3, W5, W4 I TVDD —

TSEC3_GTX_CLK W8 O TVDD —

TSEC3_RX_CLK W2 I TVDD —

TSEC3_RX_DV W1 I TVDD —

TSEC3_RX_ER Y2 I TVDD —

TSEC3_TX_CLK V10 I TVDD —

TSEC3_TX_EN V9 O TVDD 30

TSEC3_TXD[7:4] AB8, Y7, AA7, Y8 O TVDD 5, 9, 29

TSEC3_RXD[7: 4] AA1, Y3, AA2, AA4 I TVDD —

Reserved AA5 — — 15

TSEC3_COL Y5 I TVDD —

TSEC3_CRS AA3 I/O TVDD 31

TSEC3_TX_ER AB6 O TVDD —

DUART

UART_CTS[0 :1 ] AB3, AC 5 I OVDD —

UART_RTS[ 0 :1 ] AC6 , A D 7 O OVDD —

UART _ S I N [0 :1 ] AB 5 , AC7 I OV DD —

UART_SOUT[0: 1] AB7, AD8 O OVDD —

I2C interfa ce

IIC1_SCL AG22 I/O OVDD 4, 27

IIC1_SDA AG21 I/O OVDD 4, 27

IIC2_SCL AG15 I/O OVDD 4, 27

IIC2_SDA AG14 I/O OVDD 4, 27

SerDes

SD_RX[0:3] M28, N26, P28, R26 I XVDD —

SD_RX[0:3] M27, N25, P27, R25 I XVDD —

SD_TX[0:3] M22, N20, P22, R20 O XVDD —

SD_TX[0:3] M23, N21, P23, R21 O XVDD —

Reserved W2 6, Y28, AA26, AB28 — — 40

Reserved W2 5, Y27, AA25, AB27 — — 40

Reserved U20, V22, W20, Y22 — — 15

Reserved U21, V23, W21, Y23 — — 15

SD_PLL_TPD U28 O XVDD 24

SD_REF_CLK T28 I XVDD —

Table 69. MPC8545E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

112 Freescale Sem iconductor

Package Description

SD_REF_CLK T27 I XVDD —

Reserv ed AC1, AC3 — — 2

Reserv ed M26, V28 — — 32

Reserv ed M25, V27 — — 34

Reserved M20, M21, T22, T23 — — 38

General-Pur pose Output

GPOUT[2 4:31] K26, K25, H27, G28, H25, J26, K24, K2 3 O BVDD —

System Control

HRESET AG17 I OVDD —

HRESET_REQ AG16 O OVDD 29

SRESET AG20 I OVDD —

CKSTP_IN AA9 I OVDD —

CKSTP_OUT AA8 O OVDD 2, 4

Debug

TRIG_IN AB2 I OVDD —

TRIG_OUT/READY/QUIESCE AB1 O OVDD 6, 9,

19, 29

MSRCID[0:1] AE4, AG2 O OV DD 5, 6, 9

MSRCID[2:4] AF3, AF1, AF2 O OVDD 6, 19,

MDVAL AE5 O OVDD 6

CLK_OUT AE21 O OVDD 11

Clock

RTC AF16 I OVDD —

SYSCLK AH17 I OVDD —

JTAG

TCK AG28 I OVDD —

TDI AH28 I OVDD 12

TDO AF28 O OVDD 11

TMS AH27 I OVDD 12

TRST AH23 I OVDD 12

DFT

L1_TSTCLK AC25 I OVDD 25

L2_TSTCLK AE22 I OVDD 25

LSSD_MODE AH20 I OVDD 25

Table 69. MPC8545E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 113

Pa ck ag e D es cr iptio n

TEST_SEL AH14 I OVDD 25

Thermal Management

THERM0 AG1 — — 14

THERM1 AH1 — — 14

Power Management

ASLEEP AH18 O OVDD 9, 19,

Power and Ground Signals

GND A11, B7, B24, C1, C3, C5, C12, C15, C26, D8,

D11, D16, D20, D22, E1, E5, E9, E12, E15,

E17, F4, F26, G 12, G15, G18, G21, G24, H2,

H6, H8, H28, J4, J12, J15, J17, J27, K7, K9,

K11, K27, L3, L5, L12, L16, N11, N13, N15,

N17, N19, P4, P9, P12, P14, P16, P18, R11,

R13, R15, R17, R19, T4, T12, T14, T16, T1 8,

U8, U11, U13, U15, U17, U19, V4, V12, V18,

W6, W19, Y4, Y9, Y11, Y19 , AA6, AA1 4, AA17,

AA22, AA23, AB4, A C2, AC11, A C19, AC26,

AD5, AD9, AD22, AE3, AE14, AF6, AF10,

AF13, AG8, AG27, K28, L24, L26, N24, N27,

P25, R28, T24, T26, U24, V2 5, W28, Y24, Y26,

AA24, AA27, AB25, A C28, L21, L23, N22 , P20,

R23, T21, U22, V20, W23, Y21, U27

———

OVDD V16, W11, W14, Y18, AA13, AA21, AB11,

AB17, AB24, AC4, AC9, AC21, AD6, AD13,

AD17, AD19, AE10, AE8, AE24, AF4, AF12,

AF22, AF27, AG 26

Pow er for PCI

and other

standards

(3.3 V)

OVDD —

LVDD N8, R7, T9, U6 Power for

TSEC1 and

TSEC2

(2.5 V, 3.3 V)

LVDD —

TVDD W9, Y6 P ower for

TSEC3 and

TSEC4

(2,5 V, 3.3 V)

TVDD —

GVDD B3, B11, C7, C9 , C14, C17, D4, D6, D10, D15,

E2, E8, E11, E18, F5, F12, F16, G3, G7, G9,

G11, H5, H12, H15, H17, J10, K3, K12, K16,

K18, L6, M4, M8, M13

Power for

DDR1 and

DDR2 DRAM

I/O voltage

(1.8 V, 2.5 V)

GVDD —

BVDD C21, C24, C27, E20, E25, G19, G23 , H26, J20 Power for local

bus (1.8 V,

2.5 V, 3.3 V)

BVDD —

Table 69. MPC8545E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

114 Freescale Sem iconductor

Package Description

VDD M19, N12, N14, N16, N18, P11, P13, P15, P17,

P19, R12, R14, R16, R18, T11, T13, T15, T17,

T19, U12, U14, U16, U18, V17, V19

P o wer f or c ore

(1.1 V ) VDD —

SVDD L25, L27, M24 , N28, P24, P26, R24, R27, T25,

V24, V26, W24, W27, Y25, AA28, AC 27 Core power for

SerDes

transceivers

(1.1 V )

SVDD —

XVDD L20, L22, N23, P21, R22, T20, U23, V21, W22,

Y20 P ad power for

SerDes

transceivers

(1.1 V )

XVDD —

A VDD_LBIU J28 Power for local

bus PLL

(1.1 V )

—26

AVDD_PCI1 AH21 Power for PCI1

PLL

(1.1 V )

—26

AVDD_PCI2 AH22 Power for PCI2

PLL

(1.1 V )

—26

AVDD_CORE AH15 Power for e500

PLL (1.1 V) —26

AVDD_PLA T AH19 Power for CCB

PLL (1.1 V) —26

AVDD_SRDS U25 Power for

SRDSPLL (1.1

—26

SENSEVDD M14 O VDD 13

SENSEVSS M16 — — 13

Analog Signals

MVREF A18 I

Reference

vo lt age signal

for DDR

MVREF —

SD_IMP_CAL_RX L28 I 200 Ω to

GND —

SD_IMP_CAL_TX AB26 I 100 Ω to

GND —

SD_PLL_TPA U26 O — 24

Note : All note ref er ences in thi s tabl e use the same n umber s as th ose f or Table 67. The reader shou ld refer to Table 67 for the

meanings of these not es.

Table 69. MPC8545E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 115

Pa ck ag e D es cr iptio n

Table 70 provides the pin-out listing for the MPC8543E 783 FC-PBGA package.

NOTE

All note references in the following table use the same numbers as those for

Table 67. The re ader should refer to Table 67 for the meanings of these

notes.

Table 70. MPC8543E Pinout Listing

Signal Packag e Pin Number Pin Type Power

Supply Notes

PC I1 (O ne 32-B i t)

Reserved AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18 , AC17, AD16, AE16,

Y17, AC18,

——110

GPOUT[8:15] AB18, AA19, AB19, AB21, AA20, AC20, AB20,

AB22 OOV

DD —

GPIN[8: 15] A C22, AD21 , AB23, AF23, AD23, AE23 , AC23,

AC24 IOV

DD 111

PCI1_AD[31:0] AH6, AE7, AF7, AG7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, A G12, AH12 , AB13, AA12,

A C13, AE13, Y14, W13, AG 13, V14, AH13,

AC14, Y15, AB15

I/O OVDD 17

Reserved AF15, AD14, AE15, AD15 — — 110

PCI1_C_BE[3:0 ] AF9, AD1 1 , Y1 2, Y13 I/O OVDD 17

Reserved W15 — — 110

PCI1_GNT[4:1 ] A G6, AE6, AF5, AH5 O OVDD 5, 9, 35

PCI1_GNT0 AG5 I/O OVDD —

PCI1_IRDY AF11 I/O OVDD 2

PCI1_PAR AD12 I/O OVDD —

PCI1_PERR AC12 I/O OVDD 2

PCI1_SERR V13 I/O OVDD 2, 4

PCI1_STOP W12 I/O OVDD 2

PCI1_TRDY AG11 I/O OVDD 2

PCI1_REQ[4:1] AH2 , AG4, AG3, A H4 I OVDD —

PCI1_REQ0 AH3 I/O OVDD —

PCI1_CLK AH26 I OVDD 39

PCI1_DEVSEL AH11 I/O OVDD 2

PCI1_FRAME AE11 I/O OVDD 2

PCI1_IDSEL AG9 I OVDD —

cfg_pci1_width AF14 I/O OVDD 112

Reserved V15 — — 110

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

116 Freescale Sem iconductor

Package Description

Reserved AE28 — — 2

Reserved AD26 — — 110

Reserved AD25 — — 110

Reserved AE26 — — 110

cfg_pci1_clk AG24 I OVDD 5

Reserved AF25 — — 101

Reserved AE25 — — 110

Reserved AG25 — — 110

Reserved AD24 — — 110

Reserved AF24 — — 110

Reserved AD27 — — 110

Reserved AD28, AE27, W17, AF26 — — 1 10

Reserved AH25 — — 110

DDR SDRAM Memory Interface

MDQ[0:63] L18, J18, K14, L13, L19, M18, L15, L14, A17,

B17, A13, B12, C18, B18, B13, A12, H18, F18,

J14, F15, K1 9, J19, H16, K15, D17, G16, K13,

D14, D18, F17, F14, E14, A7, A6, D5, A4, C8,

D7, B5, B 4, A2, B1 , D1, E4, A3, B2, D2, E3, F3,

G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3,

J2, L1, M6

I/O GVDD —

MECC[0:7] H13, F13 , F11, C11, J13, G13, D12, M1 2 I/O GVDD —

MDM[0: 8] M17, C16, K17, E16, B6, C4, H4, K1, E13 O GVDD —

MDQS[0:8] M15, A16, G17, G14, A5, D3, H1, L2, C13 I/O GVDD —

MDQS[ 0:8] L17, B16, J16, H14, C6, C2, H3, L4, D13 I/O GVDD —

MA[0:15] A8, F9, D9, B9, A9, L1 0, M10, H10, K10, G10,

B8, E10, B10, G6, A10, L11 OGV

DD —

MBA[0:2] F7, J7, M11 O GVDD —

MWE E7 O GVDD —

MCAS H7 O GVDD —

MRAS L8 O GVDD —

MCKE[0:3] F10, C10, J11, H11 O GVDD 11

MCS[0:3] K8, J8, G8, F8 O GVDD —

MCK[0:5] H9, B15, G2, M9, A14, F1 O GVDD —

MCK[0:5 ] J9, A15, G1, L9, B14, F2 O GVDD —

MODT[0:3] E6, K6, L7, M7 O GVDD —

MDIC[0:1] A19, B19 I/O GVDD 36

Table 70. MPC8543E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 117

Pa ck ag e D es cr iptio n

Local Bus Controller Interface

LAD[0:31] E27, B20, H1 9, F25, A20, C19, E28, J23, A25,

K 22, B28, D27 , D19, J22, K20, D28, D25, B25,

E22, F22, F21, C25, C22, B23, F20, A23, A22,

E19, A21, D21, F19, B21

I/O BVDD —

LDP[0:3] K21, C28, B26, B22 I/O BVDD —

LA[27] H21 O BVDD 5, 9

LA[28:31] H20, A27, D26, A28 O BVDD 5, 7, 9

LCS[0:4] J25, C20, J24, G26, A26 O BVDD —

LCS5/DMA_DREQ2 D23 I/O BVDD 1

LCS6/DMA_DACK2 G20 O BVDD 1

LCS7/DMA_DDONE2 E21 O BVDD 1

LWE0/LBS0/LSDDQM[0] G25 O BVDD 5, 9

LWE1/LBS1/LSDDQM[1] C23 O BVDD 5, 9

LWE2/LBS2/LSDDQM[2] J21 O BVDD 5, 9

LWE3/LBS3/LSDDQM[3] A24 O BVDD 5, 9

LALE H24 O BVDD 5, 8, 9

LBCTL G27 O BVDD 5, 8, 9

LGPL0/LSDA10 F23 O BVDD 5, 9

LGPL1/LSDWE G22 O BVDD 5, 9

LGPL2/LOE/LSDRAS B27 O BVDD 5, 8, 9

LGPL3/LSDCAS F24 O BVDD 5, 9

LGPL4/LGTA/LUPWAIT/LPBSE H23 I/O BVDD —

LGPL5 E26 O BVDD 5, 9

LCKE E24 O BVDD —

LC LK[0:2] E23, D24, H22 O BVDD —

LSYNC_IN F27 I BVDD —

LSYNC_OUT F28 O BVDD —

DMA

DMA_DACK[0:1] AD3, AE1 O OVDD 5, 9, 108

DMA_DREQ[0:1] A D 4, AE 2 I OVDD —

DMA_DDONE[0 :1] AD2, AD1 O OVDD —

Programmable Interrupt Controller

UDE AH16 I OVDD —

MCP AG19 I OVDD —

Table 70. MPC8543E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

118 Freescale Sem iconductor

Package Description

IRQ[0: 7] A G23, AF18, AE18, AF20, A G18, AF 17, AH24,

AE20 IOV

DD —

IRQ[8] AF19 I OVDD —

IRQ[9]/DMA_DREQ3 AF21 I OVDD 1

IRQ[10]/DMA_DACK3 AE19 I/O OVDD 1

IRQ[11]/DMA_DDONE3 AD20 I/O OVDD 1

IRQ_OUT AD18 O OVDD 2, 4

Ethernet Management Interf ace

EC_MDC AB9 O OVDD 5, 9

EC_MDIO AC8 I/O OVDD —

Gigabi t Ref erence Clock

EC_GTX_CLK125 V11 I LVDD —

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_RXD[7:0] R5, U1, R3, U2, V3, V1, T3, T2 I LVDD —

TSEC1_TXD[7: 0] T10, V7, U10, U5, U4, V6, T5, T8 O LVDD 5, 9

TSEC1_COL R4 I LVDD —

TSEC1_CRS V5 I/O LVDD 20

TSEC1_GTX_CLK U7 O LVDD —

TSEC1_RX_CLK U3 I LVDD —

TSEC1_RX_DV V2 I LVDD —

TSEC1_RX_ER T1 I LVDD —

TSEC1_TX_CLK T6 I LVDD —

TSEC1_TX_EN U9 O LVDD 30

TSEC1_TX_ER T7 O LVDD —

GPIN[0:7] P2, R2, N1, N2, P3, M2, M1, N3 I LVDD 103

GPOUT[0:5 ] N9, N10, P8, N7, R9, N5 O LVDD —

cfg_dram_type0/GPOUT6 R8 O LVDD 5, 9

GPOUT7 N6 O LVDD —

Reserved P1 — — 104

Reserved R6 — — 104

Reserved P6 — — 15

Reserved N4 — — 105

FIFO1_RXC2 P5 I LVDD 104

Reserved R1 — — 104

Table 70. MPC8543E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 119

Pa ck ag e D es cr iptio n

Reserved P10 — — 105

FIFO1_TXC2 P7 O LVDD 15

cfg_dram_type1 R10 O LVDD 5, 9

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

TSEC3_TXD[3: 0] V8, W10, Y10, W7 O TVDD 5, 9, 29

TSEC3_RXD[3:0] Y1, W3, W5, W4 I TVDD —

TSEC3_GTX_CLK W8 O TVDD —

TSEC3_RX_CLK W2 I TVDD —

TSEC3_RX_DV W1 I TVDD —

TSEC3_RX_ER Y2 I TVDD —

TSEC3_TX_CLK V10 I TVDD —

TSEC3_TX_EN V9 O TVDD 30

TSEC3_TXD[7:4] AB8, Y7, AA7, Y8 O TV DD 5, 9, 29

TSEC3_RXD[7: 4] AA1, Y3, AA2, AA4 I TVDD —

Reserved AA5 — — 15

TSEC3_COL Y5 I TVDD —

TSEC3_CRS AA3 I/O TVDD 31

TSEC3_TX_ER AB6 O TVDD —

DUART

UART_CTS[0 :1 ] A B3 , AC 5 I OVDD —

UART_RTS[ 0 :1 ] AC6 , A D 7 O OVDD —

UART _ S I N [0 :1 ] AB5 , AC7 I OV DD —

UART_SOUT[0: 1] AB7 , AD8 O OVDD —

I2C inter face

IIC1_SCL AG22 I/O OVDD 4, 27

IIC1_SDA AG21 I/O OVDD 4, 27

IIC2_SCL AG15 I/O OVDD 4, 27

IIC2_SDA AG14 I/O OVDD 4, 27

SerDes

SD_RX[0:7] M28, N26, P28, R26, W26, Y28, AA26, AB28 I XVDD —

SD_RX[0: 7] M27, N25, P27, R25, W25, Y27, AA25, AB27 I XVDD —

SD_TX[0:7] M22, N20, P22, R20, U20, V22, W20, Y22 O XVDD —

SD_TX[0:7] M23, N21, P23, R21, U21, V23, W21, Y23 O XVDD —

SD_PLL_TPD U28 O XVDD 24

Table 70. MPC8543E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

120 Freescale Sem iconductor

Package Description

SD_REF_CLK T28 I XVDD —

SD_REF_CLK T27 I XVDD —

Reserv ed AC1 , AC3 — — 2

Reserv ed M26, V28 — — 32

Reserv ed M25, V27 — — 34

Reserved M20, M21, T22, T23 — — 38

General-Pur pose Output

GPOUT[2 4:31] K26, K25, H27, G28, H25, J26, K24, K2 3 O BVDD —

System Control

HRESET AG17 I OVDD —

HRESET_REQ AG16 O OVDD 29

SRESET AG20 I OVDD —

CKSTP_IN AA9 I OVDD —

CKSTP_OUT AA8 O OVDD 2, 4

Debug

TRIG_IN AB2 I OVDD —

TRIG_OUT/READY/QUIESCE AB1 O OVDD 6, 9, 19,

MSRCID[0:1] AE4, AG2 O OVDD 5, 6, 9

MSRCID[2:4] AF3, AF1, AF2 O OVDD 6, 19, 29

MDVAL AE5 O OVDD 6

CLK_OUT AE21 O OVDD 11

Clock

RTC AF16 I OVDD —

SYSCLK AH17 I OVDD —

JTAG

TCK AG28 I OVDD —

TDI AH28 I OVDD 12

TDO AF28 O OVDD 11

TMS AH27 I OVDD 12

TRST AH23 I OVDD 12

DFT

L1_TSTCLK AC25 I OVDD 25

L2_TSTCLK AE22 I OVDD 25

Table 70. MPC8543E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 121

Pa ck ag e D es cr iptio n

LSSD_MODE AH20 I OVDD 25

TEST_SEL AH14 I OVDD 109

Thermal Management

THERM0 AG1 — — 14

THERM1 AH1 — — 14

Power Management

ASLEEP AH18 O OVDD 9, 19, 29

Power and Ground Signals

GND A11, B7 , B24, C1, C3, C5, C12, C15, C26, D8,

D11, D16, D20, D22, E1, E5, E9, E12, E15,

E17, F4, F26, G12, G15, G18, G21, G24, H2,

H6, H8, H28, J4, J12, J15, J17, J27, K7, K9,

K11, K27, L3, L5, L12, L16, N11, N13, N15,

N17, N19, P4, P9, P12, P14, P16, P18, R11,

R13, R15, R17, R19, T4, T12, T14, T16, T1 8,

U8, U11, U13, U15, U17, U19, V4, V12, V18,

W6, W19, Y4, Y9, Y11, Y19 , AA6, AA1 4, AA17,

AA22, AA23, AB4, A C2, AC11, AC 19, AC26,

AD5, AD9, AD22, AE3, AE14, AF6, AF10,

AF13, AG8, AG27, K28, L24, L26, N24, N27,

P25, R28, T24, T26, U24, V2 5, W28, Y24, Y26,

AA24, AA27, AB25, A C28, L21, L23, N22 , P20,

R23, T21, U22, V20, W23, Y21, U27

———

OVDD V16, W11, W14, Y18, AA13, AA21, AB11,

AB17, AB24, AC4, AC9, AC21, AD6, AD13,

AD17, AD19, AE10, AE8, AE24, AF4, AF12,

AF22, AF27, AG 26

Power for

PCI and

other

standards

(3.3 V)

OVDD —

LVDD N8, R7, T9, U6 Power for

TSEC1 and

TSEC2

(2. 5 V, 3.3 V)

LVDD —

TVDD W9, Y6 Power for

TSEC3 and

TSEC4

(2, 5 V, 3.3 V)

TVDD —

GVDD B3, B11, C7, C9 , C14, C17, D4, D6, D10, D15,

E2, E8, E11, E18, F5, F12, F16, G3, G7, G9,

G11, H5, H12, H15, H17, J10, K3, K12, K16,

K18, L6, M4, M8, M13

Power for

DDR1 and

DDR2

DRAM I/O

voltage

(1.8 V,2.5 V)

GVDD —

Table 70. MPC8543E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

122 Freescale Sem iconductor

Package Description

BVDD C21, C24, C27, E20, E 25, G19, G23, H26, J20 P ower for

local bus

(1.8 V, 2.5 V,

3.3 V)

BVDD —

VDD M19, N12, N14, N16, N18, P11, P13, P15, P17,

P19, R12, R14, R16, R18, T11, T13, T15, T17,

T19, U12, U14, U16, U18, V17, V19

Power for

core (1.1 V) VDD —

SVDD L25, L27, M24 , N28, P24, P26, R24, R27, T25,

V24, V26, W24, W27, Y25, AA28, AC 27 Core power

for Se rDes

transceivers

(1.1 V )

SVDD —

XVDD L20, L22, N23, P21, R22, T20, U23, V21, W22,

Y20 Pad power

for Se rDes

transceivers

(1.1 V )

XVDD —

AVDD_LBIU J28 Power for

local bus

PLL

(1.1 V )

—26

AVDD_PCI1 AH21 Po wer for

PCI1 PLL

(1.1 V )

—26

AVDD_PCI2 AH22 Po wer for

PCI2 PLL

(1.1 V )

—26

AVDD_CORE AH15 Power for

e500 PLL

(1.1 V )

—26

AVDD_PLAT AH19 Power f or

CCB PLL

(1.1 V )

—26

AVDD_SRDS U25 Power for

SRDSPLL

(1.1 V )

—26

SENSEVDD M14 O VDD 13

SENSEVSS M16 — — 13

Analog Signals

MVREF A18 I

Reference

voltage

signal for

DDR

MVREF —

SD_IMP_CAL_RX L28 I 200 Ω (±1%)

to GN D —

Table 70. MPC8543E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 123

Clocking

19 Clocking

This section describes the PLL configuration of the MPC8548E. Note that the platform clock is identical

to the core complex bus (CCB) clock.

19.1 Clo ck Ranges

Table 71 through Table 73 provide the clocking specifications for the processor cores and Table 74,

through Table 76 provide the clocking specifications for the memor y bus.

SD_IMP_CAL_TX AB26 I 100 Ω (±1%)

to GN D —

SD_PLL_TPA U26 O AVDD_SRDS 24

Note : Al l not e referen ces in t his t abl e use the sam e num bers as those for Table 67. The read er shoul d ref er to Table 67 for the

meanings of these not es.

Table 71. Pro cessor Core Clocking Specifications (MPC8548E and MPC8547E)

Characteristic

Maxim u m Processor Core Frequency

Unit Notes1000 MHz 1200 MHz 13 33 MHz

Min Max Min Max Min Max

e500 core processor frequency 800 1000 8 00 1200 800 1333 MHz 1 , 2

Notes:

1. Caution: The CCB to SYSCLK rati o and e500 core to CCB ratio settings must be chosen such that the re sulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operat ing

frequencies. Refer to Section 19.2, “CCB/ SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core fr equency is based on the minimum platfor m frequency of 333 MHz.

Table 72. Pr o cessor Core Clocking Specifications (MPC8545E)

Characteristic

Maxim u m Processor Core Frequency

Unit Notes800 MHz 1000 MHz 1200 M Hz

Min Max Min Max Min Max

e500 core processor frequency 800 800 800 1000 800 1200 MHz 1, 2

Notes:

1. Caution: The CCB to SYSCLK rati o and e500 core to CCB ratio settings must be chosen such that the re sulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operat ing

frequencies. Refer to Section 19.2, “CCB/ SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core fr equency is based on the minimum platfor m frequency of 333 MHz.

Table 70. MPC8543E Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

124 Freescale Sem iconductor

Clocking

Table 73. Pr o cessor Core Clocking Specifications (MPC8543E)

Characteristic

Maxim u m Processor Core Frequency

Unit Notes800 MHz 1000 MHz

Min Max Min Max

e500 core processor frequency 800 800 800 1000 MHz 1, 2

Notes:

1. Caution: The CCB to SYSCLK rati o and e500 core to CCB ratio settings must be chosen such that the re sulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operat ing

frequencies. Refer to Section 19.2, “CCB/ SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core fr equency is based on the minimum platfor m frequency of 333 MHz.

Table 74. Memory Bus Clocking Specifications (MPC854 8E an d MPC85 47E)

Characteristic

Maxim u m Processor Core Frequency

Unit Notes1000, 1200, 1333 M Hz

Min Max

Memory bus cl ock speed 166 266 MHz 1, 2

Notes:

1. Caution: The CCB cloc k to SYSCLK rat io and e500 core to CCB cloc k rati o settings must be cho sen such that the resulti ng

SYSCLK frequency, e500 (core) f requency, and CCB clock frequency do not exceed their respective m aximum or minimum

operating frequencies. Refer to Sect ion 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ra tio

settings.

2. The memory b us speed is half of the DDR/DDR2 data rate, hence, h alf of the platform cloc k frequency.

Table 75. Memo ry Bus Clocking Specifications (MPC8545E )

Characteristic

Maxim u m Processor Core Frequency

Unit Notes800, 1000, 1200 MHz

Min Max

Memory bus cl ock speed 166 200 MHz 1, 2

Notes:

1. Caution: The CCB cloc k to SYSCLK rat io and e500 core to CCB cloc k rati o settings must be cho sen such that the resulti ng

SYSCLK frequency, e500 (core) f requency, and CCB clock frequency do not exceed their respective m aximum or minimum

operating frequencies. Refer to Sect ion 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ra tio

settings.

2. The memory b us speed is half of the DDR/DDR2 data rate, hence, h alf of the platform cloc k frequency.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 125

Clocking

19.2 CCB/SYSCLK PLL Ratio

The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform

clock. The frequency of th e CCB is set using the following reset signals, as shown in Table 77:

• SYSCLK input s ignal

• Binary value on LA[28:31] at power up

Note that there is no default for t his PLL ratio; t hese signals must be pulled to the desired values. Als o note

that the DDR data rate is the dete rmining factor in selec ting the C CB bus frequenc y, since the CC B

frequency must equal the DDR data rate.

For specifications on the PCI_CL K, refer to the PCI 2.2 Specification.

Table 76. Memo ry Bus Clocking Specifications (MPC8543E )

Characteristic

Maxim u m Processor Core Frequency

Unit Notes800, 1000 MHz

Min Max

Memory bus cl ock speed 166 200 MHz 1, 2

Notes:

1. Caution: The CCB cloc k to SYSCLK rat io and e500 core to CCB cloc k rati o settings must be cho sen such that the resulti ng

SYSCLK frequency, e500 (core) f requency, and CCB clock frequency do not exceed their respective m aximum or minimum

operating frequencies. Refer to Sect ion 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ra tio

settings.

2. The memory b us speed is half of the DDR/DDR2 data rate, hence, h alf of the platform cloc k frequency.

Table 7 7. CCB Clock Ratio

Binary Value of LA[28:31] Signals CCB:SYSCLK Ratio Binary Value of LA[2 8:31] Sign als CCB:SYSCLK Ratio

0000 16:1 1000 8:1

0001 Reserved 1001 9:1

0010 2:1 1010 10:1

0011 3:1 1011 Reserved

0100 4:1 1100 12:1

0101 5:1 1101 20:1

0110 6:1 1110 Reserved

0111 Reserved 1111 Reserved

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

126 Freescale Sem iconductor

Clocking

19.3 e500 Core PLL Ratio

Table 78 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This

ratio is determined by the binary value of LBCTL, LALE, and L GPL2 at power up, as s hown in Table 78.

19.4 Freque ncy Options

Table 79 shows the expected frequency values for the platform frequency when using a CCB clock to

SYSCLK ra tio in c omparison to the memory bus clock speed.

Table 78. e500 Core to CCB Clock Ratio

Binary Value of

LBCTL, LALE, LGPL2

Signals e5 00 core:CCB Clock Ratio Binary Val ue of

LBCTL, LALE, LGPL2

Signals e500 core:CCB Clock Rat io

000 4:1 100 2:1

001 9:2 101 5:2

010 Reserved 110 3:1

011 3:2 111 7:2

Table 79. Frequency Options of SYSCL K with Respect to Memo ry Bus Speeds

CCB to

SYSCLK Ratio SYSCLK (MHz)

16.66 25 33.33 41.66 66.66 83 100 111 133.33

Platform/CCB Frequency (MHz)

3333 400

4333 400 445 533

5333 415 500

6400 500

8333 533

9375

10 333 417

12 400 500

16 400 533

20 333 500

Note : Due to err ata Gen 13 the max sys clk frequenc y should not e xceed 100 MHz if th e core clk frequenc y is below

1200 MHz.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 127

Thermal

20 Thermal

This section describes the thermal specifications of the MPC8548.

20.1 Therm a l for Version 2.0 Silicon HiCTE FC-CBGA with Full Lid

This section describes the thermal specifications for the HiCTE FC-CBGA package for revision 2.0

silicon.

Table 80 shows the package thermal characteristics.

20.2 Thermal for V ersion 2.1.1 and 2.1.2 Silicon FC-PBGA with Full Lid

This section describes the thermal specific ations for the FC-PBGA package for re vision 2.1.1 silicon.

Table 81 shows the package thermal characteristics.

Table 80. Package Therm al Character istics for HiCTE F C -CBGA

Characteristic JEDEC Board Symbol Value Unit Notes

Die junction-to-ambient (natural convection) Si ngle-layer board (1s) RθJA 17 °C/W 1, 2

Die junction-to-ambient (natural convection) Four-layer board (2s2p) RθJA 12 °C/W 1, 2

Die junction-to-ambient (200 ft/min) Single-layer board (1s) RθJA 11 °C/W 1, 2

Die junction-to-ambient (200 ft/min) Four -layer board (2s2p) RθJA 8°C/W1, 2

Die junction-to-board N/A RθJB 3°C/W3

Die junction-to -case N/A RθJC 0.8 °C/W 4

Notes:

1. Junction tem peratur e is a fun ction of die siz e, on-chip power dissipation, package thermal resistance , mountin g site ( board)

temperature , ambient temper ature, airflow, pow er di ssipati on of ot her co mp onents on the board, and board thermal

resistance.

2. Per JEDEC JESD51-6 with the board ( JESD51-7) horizontal .

3. Thermal res istanc e betwe en the di e an d the pri nted-c ircuit board pe r JE DEC JESD51- 8. Boar d temp eratu re is measured on

the top sur face of the board n ear the package.

4. Thermal resistance betw een the die and the case top surfac e as measured by the cold plate method (MIL SPEC-883 Method

1012.1) . The col d plate temper atu re is used for the case tem perat ure, meas ured v a lue incl udes t he thermal r esist ance of t he

inter face layer.

Table 81. Package Thermal Characteristics for FC-PBGA

Characteristic J EDEC Board Symbol Value Unit Notes

Die junction-to-ambient (natural convection) Single- layer board (1s) RθJA 18 °C/W 1, 2

Die junction-to-ambient (natural convection) Four-layer board (2s2p) RθJA 13 °C/W 1, 2

Die junction-to-ambient (200 ft/min) Single-layer board (1s) RθJA 13 °C/W 1, 2

Die junction-to-ambient (200 ft/min) Four-layer board (2s2p) RθJA 9°C/W1, 2

Die junction-to-board N/A RθJB 5°C/W3

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

128 Freescale Sem iconductor

Syste m Des ign Infor m atio n

20.3 Heat Sink Solution

Every system application has different c onditions that the thermal management solution must solve. As

such, providing a recommended heat sink has not been found to be very useful. When a heat sink is chosen,

give special consideration to the mounting technique. Mounting the heat sink to the printed-circuit board

is the recommended procedure using a ma ximum of 10 lbs force (45 Newtons) perpendicular to the

package and board. Clipping the heat sink to the package is not recomm ended.

21 System Design Information

This section provides electrical design recommendat ions for successful application of the MPC8548E.

21 .1 System Clocking

This device includes five PLLs, as follows:

1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The

frequency ratio between the platform and SYSCLK is sel ected using the platform PLL ratio

configuration bits as described in Section 19.2, “CCB /SYSCLK PLL Ra tio. ”

2. The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio

between the e500 core clock and the platform clock is selected using the e500 PLL ratio

configuration bits as described in Section 19.3, “e500 Core PLL Ratio.”

3. The PCI PLL generates the clocking f or the PCI bus.

4. The local bus PLL generates the clock f or the local bus .

5. There is a PLL for the SerDes block.

21.2 PLL Power Sup ply Fil tering

Each of the PLLs listed above is provided with power through independent power supply pins

(AVDD_PLAT, AVDD_CORE, AVDD_PCI, AVDD_LBIU, and AVDD_SRDS, respectively) . The AVDD

level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD

through a low frequency filter scheme such as the following.

Die junction-to -case N/A RθJC 0.8 °C/W 4

Notes:

1. Junction tem peratur e is a fun ction of die siz e, on-chip power dissipation, package thermal resistance , mountin g site ( board)

temperature , ambient temper ature, airflow, pow er di ssipati on of ot her co mp onents on the board, and board thermal

resistance.

2. Per JEDEC JESD51-6 with the board ( JESD51-7) horizontal .

3. Thermal resist anc e between t he die an d the printed cir cuit board per JEDEC JESD51-8. Boar d tempera ture i s measu red on

the top sur face of the board n ear the package.

4. Thermal resistance betw een the die and the case top surfac e as measured by the cold plate method (MIL SPEC-883 Method

1012.1) . The col d plate temper atu re is used for the case tem perat ure, meas ured v a lue incl udes t he thermal r esist ance of t he

inter face layer.

Table 81. Package Thermal Characteristics f or FC-PBGA (contin ued)

Characteristic J EDEC Board Symbol Value Unit Notes

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 129

System Design Information

There are a number of ways to reliably provide power to the PLLs, but the recommended solut ion is to

provide independent filter circuits per PLL power supply as illustrated in Figure 56, one to each of the

AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injec tion from

one PLL to the other is reduced.

This circuit is intende d to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacit ors with minim um E ffective Series Inductance (ESL ).

Consistent with the recommendations of Dr . Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize

noise coupled from nearby circuits. It should be pos sible to r oute directly from the capacitors to the AVDD

pin, which is on the periphery of the footprint, without the inductance of vi as.

Figure 56 through Figure 58 shows the PLL power supply filter circuits.

Figure 56. PLL Power Supply Filter Circuit with PLAT Pins

Figure 57. PLL Power Supply Filter Circuit with CORE Pins

Figure 58. PLL Power Supply Filter Circuit with PCI/LBIU Pins

The AVDD_SRDS signal pr ovides power for the analog por tions of the S er Des PLL. To ensure stability of

the internal clock, the power supplie d to the PLL is filtered using a circuit similar to the one shown in

following figure. For maximum ef fec tiven ess, the filter circuit is plac ed as closely as possible to the

AVDD_SRDS ball t o ensure it filters out as much noise as possible. The groun d connection should be near

the AVDD_SRDS ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF capacitors,

and finally the 1 Ω resistor to the board supply plane. The capacitors are connected from AVDD_SRDS to

the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency . All t races

should be kept short, wide and dir ect.

VDD AVDD_PLAT

2.2 µF 2.2 µF

GND Low ESL Surface Moun t Capacitors

150 Ω

VDD AVDD_CORE

2.2 µF 2.2 µF

GND Low ESL Surface Moun t Capacitors

180 Ω

VDD AVDD_PCI/AVDD_LBIU

2.2 µF 2.2 µF

GND Low ESL Surface Moun t Capacitors

10 Ω

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

130 Freescale Sem iconductor

Syste m Des ign Infor m atio n

Fig ure 59. S erDes PLL Power Supply Filter

Note the following:

•AV

DD_SR D S should be a filtered version of SVDD.

• Signals on the SerDes interface are fed from the XVDD power plane.

21.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply , especially while driving large capacitive loads.

This noise must be prevented fr om reaching other component s in the MPC8548E system, and the device

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each VDD, TVDD, BV DD, OVDD, GVDD, and LVDD pin

of the device. T hese decoupling capacitors should receive their power from separate VDD, TVDD, BVDD,

OVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing short low impedance traces to

minimize inductance. Capacitors must be placed directly under the device using a standard escape pattern

as much as pos sible. If some caps are to b e placed surrounding the part i t should be routed with lar ge trace

to minimize the inductance.

These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors

should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be severa l bulk s torage capacitors distr ibuted around the PCB ,

feeding the VDD, TVDD, BV DD, OVDD, GVDD, and LVDD, planes, to enable quick recharging of the

smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating

to ensure the quick response time necessary. They should also be connected to the power and ground

planes through two vias to minimize inductance. Suggested bulk capacitor s—100–330 µF (AVX TPS

tantalum or Sanyo OS CON). However , customers should wor k directly with their power regulator vendor

for best values, types and quantity of bulk cap ac itors .

21.4 Ser Des Block Power Supply Decoupling Reco mm enda tions

The SerDes block requir es a clean, tightly r egulated source of power (SVDD and XV DD) to ensure low

jitter on transmit and reliable recovery of data in the rec eiver. An appr opr iate decoupling scheme is

outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize induc tance. Connections

from all capacitors to powe r and ground s hould be done with multiple vias to f ur ther reduce inductance.

• First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible

to the s upply balls of the d evice. Where the board has blind vias, these capacitors should be placed

2.2 µF 10.003 µF

1.0 Ω AVDD_SRDS

Note:

1. An 0805 sized capacitor is recommended for syst em ini ti al b rin g-up.

SVDD 2.2 µF 1

GND

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 131

System Design Information

directly below th e chip supply and ground connections. Where the board does not have blind vias,

these capacitors should be placed in a ring around the device as close to the supply and ground

connections as possible.

• Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SVDD and

XVDD) to the board ground plane on each side of the device. T his should be done for all SerDes

supplies.

• Third, between the device and any SerDes voltage regulator there should be a 10-µF, low

equivalent series resistance (ESR) SM T tantalum chip capacitor and a 100-µF, low ESR SM T

tantalum chip capacitor. This should be done for all SerDes supplies.

21.5 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an a ppropriate signal

level. All unused active low in puts should be tied to VDD, TV DD, BVDD, OVDD, GV DD, and LVDD, as

required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must

remain unconnect ed. Power and ground connections must be made to all external VDD, TV DD, BV DD,

OVDD, GVDD, LVDD,

and GND pins of the device.

21.6 Pull-Up and Pull-Down Resistor Requirements

The MPC8548E requires weak pull-up re sistors (2–10 kΩ is recommended) on open drain type pins

including I2C pins and PIC (interrupt) pins.

Correct operation of the JTAG interface requires configuration of a group of system control pin s as

demonstrated in Figure 62. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating condit ions as most have asynchronous behavior and spurious assertion will

give unpredictable results.

The following pins must not be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,

TRIG_OUT/READY/QUIESCE, MSRCID [2:4], ASLEEP. The DMA_DACK [0:1], and TEST _SEL/

TEST_SEL pins must be set to a proper state during POR configuration. Refer to the pinlist table of the

individual device for more details

Refer to the PCI 2.2 specification for all pull ups required for PCI.

21.7 Output Buffer DC Impedance

The MPC8548E drivers are characterized over process, voltage, and temperature. For all buses, the driver

is a push-pull single-ended driver type (open drain for I2C).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD

or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (s ee Figure 60). The

output impedance is the average of two components, the resistances of the pull-up and pull -down devices.

When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals

OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each

other in va lue. Then, Z0 = (RP + RN)/2.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

132 Freescale Sem iconductor

Syste m Des ign Infor m atio n

Figure 60. Driver Impedance Measurement

Table 82 summa rizes the signa l impedance tar gets. The driver impedances are targeted at minimum VDD,

nominal OVDD, 105°C.

21.8 Configura tion Pin Muxing

The MPC8548E provides t he user with power-on configuration options which can b e set through the use

of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible

configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are tr eated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal funct ion. Most of these sampled configuration pins are equipped

with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull

the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and

for platform/system clocks after HRESET deassertion to ensure capture of t he reset value). When the input

receiver is disab led the pull-up is also, thus allowing functional operation of the pin as an output wi th

minima l signal quality or delay disrupti on. The def aul t value for all configuration bits treated this way has

been encoded such that a high voltage level puts the device into the default state and external resistors are

needed only when non-de fault settings are requir ed by the us er.

Careful board layout with stubless connections to these pull-down re sistors coupled with the large value

of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus

configured.

Table 82. Impeda nce Cha racteristics

Impedance Loca l Bu s, Ethe rnet, DUAR T, Cont rol ,

Configuration, P ower Manageme nt PCI DDR DRAM Symbol Unit

RN43 Target 25 Target 20 Target Z0W

RP43 Target 25 Target 20 Target Z0W

Note: Nominal supply voltages. See Table 1, Tj = 105°C.

OVDD

OGND

Pad

Data

SW1

SW2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 133

System Design Information

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up

devices.

21.9 JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pin s as

demonstrated in Figure 62. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating condit ions as most have asynchronous behavior and spurious assertion will

give unpredictable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but it is provided on all processors built on Power Architecture technology . The

device requires TRST to be asserted during power-on reset flow to ensure that the JTAG boundary logic

does not interfere with normal chip operation. While the TAP contr olle r can be forced to the reset state

using only the TCK and TMS signals , generally sys t ems assert TRST during the power -on reset flow.

Simply tying TRST to HR ES ET is not pr actical because the JTAG interface is also used for accessing the

common on-chip processor (COP), which implements the debug interface to the chip.

The COP function of these process or s allow a remote computer system (typicall y, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor . The COP

interface connects primarily through the JTAG port of the processor, with some additional status

monitoring s igna ls. T he COP port r e quires the ability to independently assert HR ESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, pow er supply failures, or push-button switches, then the COP re set signals must be

merge d into these signals with logic.

The arrangement shown in Figure 62 allows the COP port to independently a ssert HRESET or TRST,

while ensuring that the target can drive HRESET as well.

The COP interface has a standard header, shown i n Figure 61, for connection to the target system, and is

based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The

connector typically has pin 14 removed as a connector key.

The COP header a dds many benefits such as br eakpoints, watchpoints, register and me mory

examination/modification, and other standard debugger features. An inexpensiv e option can be to leave

the COP header unpopulated until needed.

There is no standardized way to number the COP header; so emulator v endors have issued many dif ferent

pin numbering schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others

use left-to-right then top-to- bottom. S till others number the pins counter- clockwise from pin 1 (as with an

IC). Regardless of the numbering scheme, the signal placement recommended in Figure 61 is common to

all known emulators.

21.9.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

•TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ens uring tha t the JTAG scan chain is initia lize d during

the power-on reset flow. Freescale recommends that the COP header be designed into the syste m

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

134 Freescale Sem iconductor

Syste m Des ign Infor m atio n

as shown in Figure 62. If this is not possible, the isolation resistor will allow future access to TRST

in case a JTAG interface may need to be wire d onto the syst em in futur e debug situations.

• No pull-up/pull-down is required for TDI, TMS, TDO, or TCK.

Figure 61. COP Connector Physical Pinout

KEY

No pin

COP_TDO

COP_TDI

COP_RUN/STOP

COP_TRST

COP_VDD_SENSE

COP_CHKSTP_IN

GND

COP_TCK

COP_TMS

COP_SRESET

COP_HRESET

COP_CHKSTP_OUT

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 135

System Design Information

Figure 62. JTAG Interface Connection

HRESET

From Target

Board Sources

COP_HRESET

13 COP_SRESET

SRESET

COP_VDD_SENSE2

10 Ω

10 kΩ

COP_CHKSTP_IN CKSTP_IN

8COP_TMS

COP_TDO

COP_TDI

COP_TCK

TMS

TDO

TDI

4COP_TRST

(if any)

COP Header

14 3

Notes:

3. The KEY locati on ( pin 14) is not ph ysically presen t on th e COP heade r.

10 kΩ

TRST1

10 kΩ

CKSTP_OUT

COP_CHKSTP_OUT

KEY

No pin

COP Connector

Physical Pinout

SRESET

2. Populate this with a 10−Ω resistor for shor t-circuit/current-li miti ng protection.

OVDD

10 kΩHRESET1

in order to fully control the processor as shown here.

4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an addi tional GND pin for

1. The COP port and target board should be able to independentl y assert HRESET and TRST to the processor

improved si gnal integrity.

TCK

This switch is included as a precaution for BSDL testing. The switch sho uld be closed to posi tion A during BSDL

testing to avoid accidentally asserting the TRST line. If BSDL testing i s not bei ng performed, this swit ch should be

10 kΩ

Asserting SRESET causes a machine check interrupt to t he e500 core.

closed to position B .

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

136 Freescale Sem iconductor

Syste m Des ign Infor m atio n

21.10 Guideli nes for High-Speed Interface Te rm ination

This section provides the guidelines for high-spe ed interface termination whe n the SerDes interf ace is

entirely unused and when it is partly unused.

21.10.1 SerDes Interface Entirely Unused

If the high-speed SerDes interface is not used at all, the unus ed pin should be terminated as described in

this section.

The following pins must be left unconnected (float):

•SD_TX[7:0]

•SD_TX

[7:0]

• Reserved pins T22, T23, M20, M21

The following pins must be connected to GND:

•SD_RX[7:0]

•SD_REF_CLK

NOTE

It is recommended to power down the unused lane through SRDSCR1[0:7]

receiver output in a fixed state.) that maps to S ERDES lane 0 to lane 7

accordingly.

Pins V28 and M26 must be tied to XVDD. Pins V27 and M25 must be tied to GND through a 300-Ω

resistor.

In Rev 2.0 silicon, POR configuration pin cfg_srds_en on TSEC4_TXD[2]/TSEC3_TXD[6] can be used

to power down SerDes block.

21.10.2 SerDes Interface Partly Unused

If only part of the high-speed SerDes interface pi ns are used, the remaining high-speed serial I/O pins

should be terminated as described in this section.

The following pins must be left unconnected (float) if not used:

•SD_TX[7:0]

• Reserved pins: T22, T23, M20, M21

The following pins must be connected to GND if not used:

•SD_RX[7:0]

•SD_REF_CLK

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 137

Ordering Info r mat ion

•SD_REF_CLK

NOTE

It is recommended to power down the unused lane through SRDSCR1[0:7]

receiver output in a fixed state) that maps to SERDES lane 0 to lane 7

accordingly.

Pins V28 and M26 must be tied to XVDD. Pins V27 and M25 must be tied to GND through a 300-Ω

resistor.

21.11 Guideline for PCI Interface Termination

PCI ter mination if PCI 1 or PCI 2 is not used at all.

Option 1

If PCI arbiter is enabled during POR:

• All AD pins will be dr i ven to the stable states after POR. Theref ore, al l ADs pins can be f l oati ng.

• All PCI control pins can be gr ouped together and tied to OVDD through a single 10-kΩ resistor.

• It is optional to dis able PCI block through DEVDI SR register after POR reset.

Option 2

If PCI arbiter is disabled during POR:

• All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied

to OVDD through a si ngle (or multiple) 10-kΩ res i stor(s).

• All PCI control pins can be gr ouped together and tied to OVDD through a single 10-kΩ resistor.

• It is optional to dis able PCI block through DEVDI SR register after POR reset.

21.12 Guideline for LBIU Termination

If the LBIU parity pins are not used, t he following is the termination recommendation:

• For LDP[ 0:3]—tie them to ground or the power supply rail via a 4.7-kΩ resisto r.

• For LPBSE—tie it to the power supply rail via a 4.7-kΩ re sistor (pull-up r esistor).

22 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in

Section 22.1, “Part Number s Fully Addressed by this Document.”

22.1 Part Numbers Fully Ad dressed by t hi s Do cument

Table 83 provides the Freescale part numbering nomenclature for the MPC8548E. Note that the individual

part numbers correspond to a maximum processor core frequency. For available frequencies, contact your

local Freescale sales office. In addition to the processor frequency, the part num bering scheme also

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

138 Freescale Sem iconductor

Orde ri ng Info rma tion

includes an appli cation modifier which may specify special application conditions. Each part num ber also

contains a revis i on code which r efer s to the die mask revision number.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 139

Ordering Info r mat ion

Table 83. Par t Numb ering Nomenclature

MPC

nnnnn t pp ff c r

Product

Code Part

Identifier Temperature Package1, 2, 3 Processor

Frequency4Core

Frequency Si l ic o n Ver sio n

MPC 8548 E Bla nk = 0 to 105°C

C = –40° to 105°CHX = CBGA

VU = Pb-free CBGA

PX = PBGA

VT = Pb-free PBGA

AV = 15003

AU = 1333

AT = 1200

A Q = 1000

J = 533

H = 5005

G = 40 0

Blank = Ver. 2.0

(SVR = 0x80390020)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80390021)

8548 Blank = Ver. 2.0

(SVR = 0x80310020)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80310021)

8547E AU = 1333

AT = 1200

A Q = 1000

J = 533

G = 40 0 Blank = Ver. 2.0

(SVR = 0x80390120)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80390121)

8547 Blank = Ver. 2.0

(SVR = 0x80390120)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80310121)

8545E AT = 1200

A Q = 1000

AN = 800

G = 400 Bl ank = Ver. 2.0

(SVR = 0x80390220)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80390221)

8545 Blank = Ver. 2.0

(SVR = 0x80310220)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80310221)

8543E A Q = 1000

AN = 800 Blank = Ver. 2.0

(SVR = 0x803A0020)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x803A0021)

8543 Blank = Ver. 2.0

(SVR = 0x80320020)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80320021)

Notes:

1. See Section 18, “Package Descript ion,” for more infor mation on available package types.

2. The HiCTE FC-CBGA package is availab le on only Version 2.0 of the device .

3. The FC-PBGA package is av ailab le on only Version 2.1.1 and 2.1.2 of the device.

4. Processor core frequencies suppo rted by parts addressed by this specification only. Not all parts describe d in this

specificatio n support all core frequencies. Additionally, parts addressed by part number specifications ma y support other

maximum core frequencies.

5. This speed available only for silicon Version 2.1.1.and 2.1.2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

140 Freescale Sem iconductor

Orde ri ng Info rma tion

22.2 Part Marking

Parts are marke d as the example shown in Figure 63.

Figure 63. Part Markin g for CBG A and PBGA Device

MMMMM CCCCC

Notes:

CCCCC is the country of assembly. This spa ce is lef t blank if parts are assembl ed in the United Stat es.

TWLYYWW is final test traceability code.

MMMMM is 5 digit mask number .

MPC8548xxxxxx

TWLYWW

YWWLAZ

YWWLAZ is ass em bly traceability code.

(F)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 141

Document Revision History

23 Document Revision H istory

Table 84 pr ovides a revision histor y for the MPC8548E hardware specification.

Table 84. Documen t Revision History

Revision Date Substantive Change(s)

6 12/2009 • In Se ction 5.1, “Power-On Ramp R a te ” added explanation that Power-On Ramp Rate i s required to

avoi d falsely triggeri ng ESD circuitry.

•In Table 10 changed re quired ramp rate from 545 V/ s for MVREF and VDD/XVDD/SVDD to 3500 V/s

for MVREF and 4000 V/s for VDD.

•In Table 10 deleted ramp rate requirement for XVDD/SVDD.

•In Table 10 f ootnote 1 changed v oltage r ange of concern from 0–400 mV to 20–500mV.

•In Table 10 added f ootnot e 2 explai ning that VDD volta ge ramp rat e is intended to control ramp rat e of

AVDD pin s.

5 10/2009 • In Table 27, ”GMII Receive AC Timing Specifications,” changed duty cycle specification from 40/60 to

35/75 for RX_CLK duty cycle.

• Updated tMDKHDX in Table 37, “MII Managem ent AC Timi ng Specificati ons.”

• Ad ded a reference to Revision 2.1.2.

• Up dated Table 55, “M II Management AC Timing Specifications.”

• Ad ded S e ctio n 5.1, “Po wer-O n R a mp Rate.”

4 04/2009 • In Table 1, “Absolute Maximum Ratings 1,” and in Table 2, “Recommended Operating Conditi ons,”

moved text, “M II management voltage” from LV DD/TVDD to OVDD, added “Ethernet management ” to

OVDD row of i nput v oltage se cti on.

•In Table 5, “SYSCLK AC Ti ming Speci fica tions,” added notes 7 and 8 t o SYSCLK frequen cy and cy cle

time.

•In Table 36, “MII Managem ent DC Elect rical Characteristics,” changed all instances of LVDD/OVDD to

OVDD.

• Mod if ied Section 15, “High-Speed Serial Interfaces (HSSI),” to reflect that th ere is only one SerDes.

• Modified DDR clk rate min from 133 to 166 MHz.

• Modified note in Table 71, “Processor Core Clocking Specifications (MPC8548E and MPC8547E), “ .”

•In Table 52, “Differential Transmitter (TX) Output Specif ications,” modified equations in Comments

column, and changed al l instances of “LO” to “L 0.” In addi ti on, added note 8.

•In Table 53, “Differential Receiver (RX) Input Specificati ons,” modified equat ions in Comments col umn,

and in not e 3, changed “TRX-EYE-MEDIAN- to-MAX-JITTER,” to “TRX-EYE-MEDIAN-to-MAX-JITTER.”

• Mod if ied Table 79, “Frequency Optio ns of SYSCLK with Respect to Memory Bus Speeds.”

• Ad ded a note on Secti on 4.1, “System Clock Timing,” to li m it the SYSCLK to 100 MHz if the core

frequency is less than 1200 MHz

•In Table 67, “MPC8548E Pinout ListingTable 68, “MPC8 547E Pinout Listi ngTable 69, “MPC8545E

Pinout ListingTable 70, “MPC8543E Pinout Listing,” added note 5 to LA[28:31] .

• Ad ded note to Table 79, “ Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

142 Freescale Sem iconductor

Docume nt Revision Hist ory

3 01/2009 • [Section 4.6, “Platform Frequency Requ irements for PCI-Express and Serial RapidIO.” Changed

minimum frequency equation to be 527 MHz for PCI x8.

•In Table 5, added note 7.

• S ec t io n 4.5 , “P l at for m to FI F O Re s tr ict io n s .” Changed platform clock frequency to 4.2.

• Section 8.1, “Enhanced Three-Speed Ethernet Control ler (eTSEC)

(10/ 100/1G b Mbps)—GMI I/MII /TBI/ RGMII/R TBI /RMII Elec trical Char ac teristi cs.” Added M II after GMII

and add ‘or 2.5 V’ a ft er 3.3 V.

•In Table 23, modified table ti tle to include GMII, MII, RMII, and TBI.

•In Table 24 and Table 25, changed clock period minim um to 5.3.

•In Table 25, added a note.

•In Table 26, Table 27, Table 28, Table 29, and Table 30, r em oved subtitle from table titl e.

•In Table 30 and Figure 15, changed al l i nstances of PMA to TSEC

•In Section 8.2.5, “TBI Single-Clock Mode AC Specifications.” Replaced first paragraph.

•In Table 34, Table 35, Figure 18, and Figure 20, changed all instances of REF_CLK to

TSEC

_TX_CLK.

•In Table 36, changed al l i nstances of OVDD to LV DD/TVDD.

•In Table 37, “MI I M anagement AC Timing Specifications,” changed MDC minimum clock pulse width

high from 32 to 48 ns.

• Ad ded new s ection, Secti on 15, “High-Speed Serial In ter faces (HSSI) .”

• Section 16.1, “DC Requir ements for PCI Expr ess SD_REF_CLK and SD_REF_CLK.” Added new

paragraph.

• Section 17.1, “DC Requi rements f or Serial RapidIO SD_R EF_CLK and SD_REF_CLK.” Added new

paragraph.

• Ad ded information to Figure 63, both in figure and in no te.

• Section 21.3, “Decoupling Recomm endati ons.” Modified the recommendation.

• Table 83, “Part Numbering Nomenclature.” In Silicon Ver sion column added Ver. 2.1.2.

2 04/2008 • Re mo ved 1:1 support on Table 78, “e500 Core to CCB Clo ck Rati o .”

• Removed M DM from Table 18, “DDR SDRAM Input AC Timing Specifications.” MDM is an Output.

• Figure 56, “PLL Power Supply Filter Circuit with PLAT Pins” (AVDD_P L AT).

• Figure 57, “PLL Power Supply Filter Circuit with CORE Pi ns” (AVDD_CORE).

•Split Figure 58, “PLL Po wer Supply Filter Ci rcu it with PCI/LBI U Pins,” (formerly cal led just “PLL Power

Suppl y Fil ter Ci rcui t”) into three fi gur es: t he original (no w spe cifi c f or AVDD_PCI/AVDD_LBIU) and t wo

new ones.

Table 84. Document Revision History (continued)

Revision Date Substantive Change(s)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Speci fications, Rev. 6

Freescale Semiconductor 143

Document Revision History

1 10/2007 • Adjusted maximu m SYSCLK frequency down in Table 5, “SYSCLK AC Timing Specif ic ations” per

device erratum GEN-13.

• Clarified notes to Table 6, “EC_GTX_CLK125 AC Ti ming Specif ications.”

• Ad ded Section 4.4, “PCI/PCI-X Reference Clock Timing.”

• Clarified descriptions and added PCI/PCI-X to Table 9, “ PLL Lock Times.”

• Remov ed supp ort for 266 and 20 0 Mbps data ra tes per de vice err atum GEN- 13 in Section 6, “DDR and

DDR2 SDRAM.”

• Clarified Note 4 of Table 19, “DDR SDRAM Outp ut AC Timing Specifications.”

• Clarified the reference clock used i n Sec ti on 7.2, “DUART AC Electrical Speci fi cations.”

• Co rrected VIH(m in) in Tab le 22, “GMII , MII , RMII , and TBI DC Electrical Char acteristics.”

• Co rrected VIL(m a x ) in Table 23, “GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical

Characteristics.”

• Remo ved DC parameters from Table 24, Table 25, Table 26, Table 27, Table 28, Table 29, Table 32,

Table 34, and Table 35.

• Co rrected VIH(min) in Table 36, “MII Management DC Electr ical Characteristics.”

• Co rrected tMDC(m in ) in Table 37, “MII Ma nagem ent AC Timi ng Specificati ons.”

• Up dated parameter descript ions f or tLBIVKH1, tLBIVKH2, tLBIXKH1, and tLBIXKH2 in Table 40, “Local Bus

Timing Par ameter s (BVDD = 3. 3 V)—PLL Enabled” and Table 40, “Local Bus Timing Param eters

(BVDD = 2.5 V)—PLL Enab led.”

• Up dated parameter descript ions f or tLBIVKH1, tLBIVKL2, tLBIXKH1, and tLBIXKL2 in Table 42, “Local Bus

Timing Parameters—PLL Bypassed.” Note that tLBIVKL2 and tLBIXKL2 were previously la beled tLBIVKH2

and tLBIXKH2.

• Added LUPWAIT signal to Figur e 23, “Local B us Signals ( PLL Enabled) ” and Figure 24, “Local Bus

Signals (PLL Bypass Mod e).”

• Ad ded LG TA signal to Figure 25, Figure 26, Figure 27 and Figure 28.

• Co rr ected LUPWAIT assertion in Figure 26 and Figure 28.

• Clari fi ed the PCI reference c lock in Section 14.2, “PCI/PCI-X AC Electric al Specificat ions”

• Ad ded Section 17.1 , “Package Paramet ers.”

• Added PBG A thermal information in Secti on 20.2, “Thermal for Version 2.1 .1 and 2.1.2 Silicon

FC-PBGA with Full Lid.”

• Up dated.”

• Up dated Table 83, “Part Numbering Nomenclature.”

0 07/2007 • Initial Release

Table 84. Document Revision History (continued)

Revision Date Substantive Change(s)

Document Number: MPC8548EEC

Rev. 6

12/2009

Information in this document is provided solely to enable system and software

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