ISL6208BCRZ-T - Intersil Corporation

High Voltage Synchronous Rectified Buck MOSFET

Drivers

ISL6208, ISL6208B

The ISL6208 and ISL6208B are high frequency, dual MOSFET

drivers, optimized to drive two N-Channel power MOSFETs in a

synchronous-rectified buck converter topology. They are

especially suited for mobile computing applications that

require high efficiency and excellent thermal performance.

These drivers, combined with an Intersil multiphase Buck

PWM controller, form a complete single-stage core-voltage

regulator solution for advanced mobile microprocessors.

ISL6208 and ISL6208B have the same function but different

packages. The descriptions in this datasheet are based on

ISL6208 and also apply to ISL6208B.

The ISL6208 features 4A typical sinking current for the lower

gate driver. This current is capable of holding the lower

MOSFET gate off during the rising edge of the Phase node. This

prevents shoot-through power loss caused by the high dv/dt of

phase voltages. The operating voltage matches the 30V

breakdown voltage of the MOSFETs commonly used in mobile

computer power supplies.

The ISL6208 also features a three-state PWM input that,

working together with Intersil’s multiphase PWM controllers,

will prevent negative voltage output during CPU shutdown. This

feature eliminates a protective Schottky diode usually seen in

a microprocessor power systems.

MOSFET gates can be efficiently switched up to 2MHz using

the ISL6208. Each driver is capable of driving a 3000pF load

with propagation delays of 8ns and transition times under

10ns. Bootstrapping is implemented with an internal Schottky

diode. This reduces system cost and complexity, while allowing

the use of higher performance MOSFETs. Adaptive shoot-

through protection is integrated to prevent both MOSFETs from

conducting simultaneously.

A diode emulation feature is integrated in the ISL6208 to

enhance converter efficiency at light load conditions. This

feature also allows for monotonic start-up into pre-biased

outputs. When diode emulation is enabled, the driver will allow

discontinuous conduction mode by detecting when the

inductor current reaches zero and subsequently turning off the

low side MOSFET gate.

Features

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Adaptive Shoot-Through Protection

•0.5Ω On-Resistance and 4A Sink Current Capability

• Supports High Switching Frequency up to 2MHz

- Fast Output Rise And Fall Time

- Low Propagation Delay

• Three-State PWM Input for Power Stage Shutdown

• Internal Bootstrap Schottky Diode

• Low Bias Supply Current (5V, 80µA)

• Diode Emulation for Enhanced Light Load Efficiency and

Pre-Biased Start-Up Applications

• VCC POR (Power-On-Reset) Feature Integrated

• Low Three-State Shutdown Holdoff Time (Typical 160ns)

• Pin-to-Pin Compatible with ISL6207

• QFN and DFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

DFN - Dual Flat No Leads - Package Outline

- Near Chip Scale Package Footprint, which Improves PCB

Efficiency and has a Thinner Profile

• Pb-Free (RoHS Compliant)

Applications

• Core Voltage Supplies for Intel® and AMD® Mobile

Microprocessors

• High Frequency Low Profile DC/DC Converters

• High Current Low Output Voltage DC/DC Converters

• High Input Voltage DC/DC Converters

Related Literature

•Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

•Technical Brief TB389 “PCB Land Pattern Design and

Surface Mount Guidelines for MLFP Packages”

•Technical Brief TB447 “Guidelines for Preventing

Boot-to-Phase Stress on Half-Bridge MOSFET Driver ICs”

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

January 31, 2012

FN9115.6

ISL6208, ISL6208B

2FN9115.6

January 31, 2012

Pin Configurations

Block Diagram

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL6208CBZ ISL62 08CBZ -10 to +100 8 Ld SOIC M8.15

ISL6208CRZ 208Z -10 to +100 8 Ld 3x3 QFN L8.3x3

ISL6208BCRZ 8BC -10 to +100 8 Ld 2x2 DFN L8.2x2D

ISL6208IBZ ISL62 08IBZ -40 to +100 8 Ld SOIC M8.15

ISL6208IRZ 8IRZ -40 to +100 8 Ld 3x3 QFN L8.3x3

ISL6208BIRZ 8BI -40 to +100 8 Ld 2x2 DFN L8.2x2D

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin

plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6208, ISL6208B. For more information on MSL please see techbrief

TB363.

ISL6208CBZ, ISL6208IBZ

(8 LD SOIC)

TOP VIEW

ISL6208CRZ, ISL6208IRZ

(8 LD 3x3 QFN)

TOP VIEW

ISL6208BCRZ, ISL6208BIRZ

(8 LD 2x2 DFN)

TOP VIEW

UGATE

BOOT

PWM

GND

PHASE

FCCM

VCC

LGATE

UGATE

PHASE

GND

LGATE

FCCM

VCC

BOOT

PWM 5

6VCC

LGATE

PWM

GND 5

6PHASE

FCCM

UGATE

BOOT 2

VCC

PWM 10K

CONTROL

LOGIC

SHOOT-

THROUGH

PROTECTION

BOOT

UGATE

PHASE

LGATE

GND

VCC

FCCM

THERMAL PAD (FOR QFN AND DFN PACKAGE ONLY)

FIGURE 1. BLOCK DIAGRAM

ISL6208, ISL6208B

3FN9115.6

January 31, 2012

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

Input Voltage (VFCCM, VPWM) . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V

BOOT Voltage (VBOOT-GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V

BOOT To PHASE Voltage (VBOOT-PHASE). . . . . . . . . . . . . . . . -0.3V to 7V (DC)

-0.3V to 9V (<10ns)

PHASE Voltage (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V

GND - 8V (<20ns Pulse Width, 10µJ)

UGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT

VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT

LGATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V (DC) to VCC + 0.3V

GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

8 Ld SOIC Package (Notes 5, 8) . . . . . . . . . 110 67

8 Ld 3x3 QFN Package (Notes 6, 7) . . . . . . 80 15

8 Ld 2x2 DFN Package (Notes 6, 7) . . . . . . 89 24

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C

Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.

5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

8. For θJC, the “case temp” location is taken at the package top center.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating

temperature range.

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 10) TYP

MAX

(Note 10) UNITS

VCC SUPPLY CURRENT

Bias Supply Current IVCC PWM pin floating, VFCCM = 5V - 80 - µA

POR

VCC Rising -3.403.90 V

VCC Falling 2.40 2.90 - V

Hysteresis - 500 - mV

BOOTSTRAP DIODE

Forward Voltage VFVVCC = 5V, forward bias current = 2mA 0.50 0.55 0.65 V

PWM INPUT

Input Current IPWM VPWM = 5V - 250 - µA

VPWM = 0V - -250 - µA

PWM Three-State Rising Threshold VVCC = 5V 0.70 1.00 1.30 V

PWM Three-State Falling Threshold VVCC = 5V 3.5 3.8 4.1 V

Three-State Shutdown Hold-off Time tTSSHD VVCC = 5V, temperature = +25°C 100 175 250 ns

FCCM INPUT

FCCM LOW Threshold 0.50 --V

FCCM HIGH Threshold --2.0 V

SWITCHING TIME

UGATE Rise Time (Note 9) tRU VVCC = 5V, 3nF load - 8.0 - ns

LGATE Rise Time (Note 9) tRL VVCC = 5V, 3nF load - 8.0 - ns

ISL6208, ISL6208B

4FN9115.6

January 31, 2012

UGATE Fall Time (Note 9) tFU VVCC = 5V, 3nF load - 8.0 - ns

LGATE Fall Time (Note 9) tFL VVCC = 5V, 3nF load - 4.0 - ns

UGATE Turn-Off Propagation Delay tPDLU VVCC = 5V, outputs unloaded - 18 - ns

LGATE Turn-Off Propagation Delay tPDLL VVCC = 5V, outputs unloaded - 25 - ns

UGATE Turn-On Propagation Delay tPDHU VVCC = 5V, outputs unloaded 10 20 30 ns

LGATE Turn-On Propagation Delay tPDHL VVCC = 5V, outputs unloaded 10 20 30 ns

UG/LG Three-State Propagation Delay tPTS VVCC = 5V, outputs unloaded - 35 - ns

Minimum LG ON-TIME in DCM (Note9) tLGMIN - 400 - ns

OUTPUT

Upper Drive Source Resistance RU 500mA source current - 1 2.5 Ω

Upper Driver Source Current (Note 9) IU VUGATE-PHASE = 2.5V - 2.00 - A

Upper Drive Sink Resistance RU 500mA sink current - 1 2.5 Ω

Upper Driver Sink Current (Note 9) IU VUGATE-PHASE = 2.5V - 2.00 - A

Lower Drive Source Resistance RL 500mA source current - 1 2.5 Ω

Lower Driver Source Current (Note 9) IL VLGATE = 2.5V - 2.00 - A

Lower Drive Sink Resistance RL 500mA sink current - 0.5 1.0 Ω

Lower Driver Sink Current (Note 9) IL VLGATE = 2.5V - 4.00 - A

NOTES:

9. Limits established by characterization and are not production tested.

10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating

temperature range.

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 10) TYP

MAX

(Note 10) UNITS

ISL6208, ISL6208B

5FN9115.6

January 31, 2012

Typical Application with 2-Phase Converter

+5V

BOOT

UGATE

PHASE

LGATE

PWM

FCCM

VCC

DRIVE

VBAT

+5V

BOOT

UGATE

PHASE

LGATE

PWM

VBAT

+VCORE

PGOOD

VID

FS GND

ISEN2

ISEN1

PWM2

PWM1

VSEN

MAIN

VCC

+5V

COMP

ISL6208

CONTROL

VCC

DRIVE

ISL6208

+5V

DACOUT FCCM

FCCM THERMAL

PAD

THERMAL

PAD

ISL6208, ISL6208B

6FN9115.6

January 31, 2012

Timing Diagram

Functional Pin Description

UGATE

The UGATE pin is the upper gate drive output. Connect to the

gate of high-side power N-Channel MOSFET.

BOOT

BOOT is the floating bootstrap supply pin for the upper gate

drive. Connect the bootstrap capacitor between this pin and

the PHASE pin. The bootstrap capacitor provides the charge to

turn on the upper MOSFET. See “Internal Bootstrap Diode” on

page 8 for guidance in choosing the appropriate capacitor

value.

PWM

The PWM signal is the control input for the driver. The PWM signal

can enter three distinct states during operation. See “Three-State

PWM Input” on page 8 for further details. Connect this pin to the

PWM output of the controller.

GND

GND is the ground pin for the IC.

LGATE

LGATE is the lower gate drive output. Connect to gate of the

low-side power N-Channel MOSFET.

VCC

Connect the VCC pin to a +5V bias supply. Place a high quality

bypass capacitor from this pin to GND.

FCCM

The FCCM pin enables or disables Diode Emulation. When

FCCM is LOW, diode emulation is allowed. Otherwise,

continuous conduction mode is forced. See “Diode Emulation”

on page 8 for more detail.

PHASE

Connect the PHASE pin to the source of the upper MOSFET and

the drain of the lower MOSFET. This pin provides a return path

for the upper gate driver.

Description

Theory of Operation

Designed for speed, the ISL6208 dual MOSFET driver controls

both high-side and low-side N-Channel FETs from one

externally provided PWM signal.

A rising edge on PWM initiates the turn-off of the lower MOSFET

(see “Timing Diagram” above). After a short propagation delay

[tPDLL], the lower gate begins to fall. Typical fall times [tFL] are

provided in the “Electrical Specifications” section. Adaptive shoot-

through circuitry monitors the LGATE voltage. When LGATE has

fallen below 1V, UGATE is allowed to turn ON. This prevents both

the lower and upper MOSFETs from conducting simultaneously, or

shoot-through.

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [tPDLU] is encountered before the upper gate

begins to fall [tFU]. The upper MOSFET gate-to-source voltage is

monitored, and the lower gate is allowed to rise after the upper

MOSFET gate-to-source voltage drops below 1V. The lower gate

then rises [tRL], turning on the lower MOSFET.

This driver is optimized for converters with large step-down

compared to the upper MOSFET because the lower MOSFET

conducts for a much longer time in a switching period. The

lower gate driver is therefore sized much larger to meet this

application requirement.

The 0.5Ω ON-resistance and 4A sink current capability enable

the lower gate driver to absorb the current injected to the lower

gate through the drain-to-gate capacitor of the lower MOSFET

and prevent a shoot-through caused by the high dv/dt of the

phase node.

PWM

UGATE

LGATE

tPDLL

tFL

tPDHU

tRU

tPDLU

tFU

tPDHL

tRL

2.5V

tRU tFU

tFL

tPTS

tTSSHD

tPTS

ISL6208, ISL6208B

7FN9115.6

January 31, 2012

Typical Performance Waveforms

FIGURE 2. LOAD TRANSIENT (0 - 30A, 3-PHASE) FIGURE 3. LOAD TRANSIENT (30 - 0A, 3-PHASE)

FIGURE 4. DCM TO CCM TRANSITION AT NO LOAD FIGURE 5. CCM TO DCM TRANSITION AT NO LOAD

FIGURE 6. PRE-BIASED START-UP IN CCM MODE FIGURE 7. PRE-BIASED START-UP IN DCM MODE

ISL6208, ISL6208B

8FN9115.6

January 31, 2012

Diode Emulation

Diode emulation allows for higher converter efficiency under

light load situations. With diode emulation active, the ISL6208

will detect the zero current crossing of the output inductor and

turn off LGATE. This ensures that discontinuous conduction

mode (DCM) is achieved. Diode emulation is asynchronous to

the PWM signal. Therefore, the ISL6208 will respond to the

FCCM input immediately after it changes state. Refer

to“Typical Performance Waveforms” on page 7. NOTE: Intersil

does not recommend Diode Emulation use with rDS(ON)

current sensing topologies. The turn-OFF of the low side

MOSFET can cause gross current measurement inaccuracies.

Three-State PWM Input

A unique feature of the ISL6208 and other Intersil drivers is the

addition of a shutdown window to the PWM input. If the PWM

signal enters and remains within the shutdown window for a set

holdoff time, the output drivers are disabled and both MOSFET

gates are pulled and held low. The shutdown state is removed

when the PWM signal moves outside the shutdown window.

Otherwise, the PWM rising and falling thresholds outlined in the

“Electrical Specifications” table on page 3 determine when the

lower and upper gates are enabled.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection to

prevent upper and lower MOSFETs from conducting

simultaneously and shorting the input supply. This is

accomplished by ensuring the falling gate has turned off one

MOSFET before the other is allowed to turn on.

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a 1V threshold, at which time the

UGATE is released to rise. Adaptive shoot-through circuitry

monitors the upper MOSFET gate-to-source voltage during UGATE

turn-off. Once the upper MOSFET gate-to-source voltage has

dropped below a threshold of 1V, the LGATE is allowed to rise.

Internal Bootstrap Diode

This driver features an internal bootstrap Schottky diode.

Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit.

The bootstrap capacitor must have a maximum voltage rating

above the maximum battery voltage plus 5V. The bootstrap

capacitor can be chosen from Equation 1:

where QGATE is the amount of gate charge required to fully

charge the gate of the upper MOSFET. The ΔVBOOT term is

defined as the allowable droop in the rail of the upper drive.

As an example, suppose an upper MOSFET has a gate charge,

QGATE, of 25nC at 5V and also assume the droop in the drive

voltage over a PWM cycle is 200mV. One will find that a

bootstrap capacitance of at least 0.125µF is required. The next

larger standard value capacitance is 0.15µF. A good quality

ceramic capacitor is recommended.

Power Dissipation

Package power dissipation is mainly a function of the

switching frequency and total gate charge of the selected

MOSFETs. Calculating the power dissipation in the driver for a

desired application is critical to ensuring safe operation.

Exceeding the maximum allowable power dissipation level will

push the IC beyond the maximum recommended operating

junction temperature of +125°C. The maximum allowable IC

power dissipation for the SO-8 package is approximately

800mW. When designing the driver into an application, it is

recommended that the following calculation be performed to

ensure safe operation at the desired frequency for the selected

MOSFETs. The power dissipated by the driver is approximated

as shown in Equation 2:

where fsw is the switching frequency of the PWM signal. VU

and VL represent the upper and lower gate rail voltage. QU and

QL is the upper and lower gate charge determined by MOSFET

selection and any external capacitance added to the gate pins.

The lVCC VCC product is the quiescent power of the driver and

is typically negligible.

CBOOT

QGATE

ΔVBOOT

---------------------

≥(EQ. 1)

FIGURE 8. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

20nC

ΔVBOOT_CAP (V)

CBOOT_CAP (µF)

2.0

1.6

1.4

1.0

0.8

0.6

0.4

0.2

0.0 0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0

QGATE = 100nC

1.2

1.8

50nC

sw 1.5VUQUVLQL

+()IVCCVCC

+= (EQ. 2)

FIGURE 9. POWER DISSIPATION vs FREQUENCY

FREQUENCY (kHz)

100

200

300

400

500

600

700

800

900

1000

0 200 400 600 800 1000 1200 1400 1600 1800 2000

POWER (mW)

QU = 50nC

QL = 50nC

QU = 50nC

QL = 100nC

QU =100nC

QL = 200nC

QU = 20nC

QL =50nC

ISL6208, ISL6208B

9FN9115.6

January 31, 2012

Layout Considerations

Reducing Phase Ring

The parasitic inductances of the PCB and power devices (both upper

and lower FETs) could cause increased PHASE ringing, which may

lead to voltages that exceed the absolute maximum rating of the

devices. When PHASE rings below ground, the negative voltage

could add charge to the bootstrap capacitor through the internal

bootstrap diode. Under worst-case conditions, the added charge

could overstress the BOOT and/or PHASE pins. To prevent this from

happening, the user should perform a careful layout inspection to

reduce trace inductances, and select low lead inductance MOSFETs

and drivers. D2PAK and DPAK packaged MOSFETs have high

parasitic lead inductances, as opposed to SOIC-8. If higher

inductance MOSFETs must be used, a Schottky diode is

recommended across the lower MOSFET to clamp negative PHASE

ring.

A good layout would help reduce the ringing on the phase and

gate nodes significantly:

• Avoid using vias for decoupling components where possible,

especially in the BOOT-to-PHASE path. Little or no use of vias

for VCC and GND is also recommended. Decoupling loops

should be short.

• All power traces (UGATE, PHASE, LGATE, GND, VCC) should be

short and wide, and avoid using vias. If vias must be used, two

or more vias per layer transition is recommended.

• Keep the SOURCE of the upper FET as close as thermally

possible to the DRAIN of the lower FET.

• Keep the connection in between the SOURCE of lower FET and

power ground wide and short.

• Input capacitors should be placed as close to the DRAIN of the

upper FET and the SOURCE of the lower FET as thermally

possible.

Note: Refer to Intersil Tech Brief TB447 for more information.

Thermal Management

For maximum thermal performance in high current, high

switching frequency applications, connecting the thermal pad of

the QFN and DFN parts to the power ground with multiple vias, or

placing a low noise copper plane underneath the SOIC part is

recommended. This heat spreading allows the part to achieve its

full thermal potential.

ISL6208, ISL6208B

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9115.6

January 31, 2012

For additional products, see www.intersil.com/product_tree

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL6208, ISL6208B

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest revision.

DATE REVISION CHANGE

January 17, 2012 FN9115.6 Added limits for “UGATE Turn-On Propagation Delay” and “LGATE Turn-On Propagation Delay” on page 4.

October 26, 2011 FN9115.5 Removed limits for “UGATE Turn-On Propagation Delay” and “LGATE Turn-On Propagation Delay” on page 4.

July 12, 2011 FN9115.4 Added “Revision History” on page 10 and “Products” on page 10.

Added ISL6208BCRZ and ISL6208BIRZ parts to “Ordering Information” on page 2. Removed leaded, obsolete

devices (ISL6208CB, ISL6208CR, ISL6208IB, ISL6208IR).

Updated Tape & Reel note in “Ordering Information” on page 2 from "Add "-T" suffix for tape and reel." to new

standard "Add "-T*" suffix for tape and reel." The "*" covers all possible tape and reel options

Added MSL note to “Ordering Information” on page 2

Added Pinout for ISL6208BIRZ and ISL6208BCRZ on page 2

Added “Thermal Information” on page 3 for new ISL6802B package, 8 Ld 2x2 DFN. Added Theta JC for SOIC

package and Note 8.

Removed "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.

Temperature limits established by characterization and are not production tested." from common conditions of

spec table. Added as Note in MIN MAX columns of “Electrical Specifications” table.

Added standard text "Boldface limits apply over the operating temp range" to common conditions of spec table.

Bolded applicable specs.

Updated “Package Outline Drawing” on page 13 (M8.15) as follows:

Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern

ISL6208, ISL6208B

11 FN9115.6

January 31, 2012

Package Outline Drawing

L8.3x3

8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 3/07

located within the zone indicated. Th e pin #1 indentifier may be

Unless otherwise specified, tol erance : Decim al ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optio nal, but must be

between 0.15mm an d 0.3 0m m from the te rminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL " X "

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

BOTTOM VIEW

SIDE VIEW

(4X) 0.15

INDEX AREA

PIN 1

3.00

8X 0.60 ± 0.15

8X 0.28 ± 0.05

0.10 BA

0.65

PIN #1 INDEX AR EA

1 .10 ± 0 . 15

0 . 90 ± 0.1

SEE DETAIL "X "

BASE PLANE

SEATING PLANE

0.10

0.08

0 . 05 MAX.

0 . 2 REF

0 . 00 MIN.

( 2. 60 TYP )

( 1. 10 )

( 8X 0 . 80 )

( 8X 0 . 28 )

( 4X 0 . 65 )

ISL6208, ISL6208B

12 FN9115.6

January 31, 2012

Package Outline Drawing

L8.2x2D

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD

Rev 0, 3/11

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

PIN #1

B0.10MA

SEATING PLANE

BASE PLANE

0.08

0.10

SEE DETAIL "X"

0 . 00 MIN.

0 . 05 MAX.

0 . 2 REF

INDEX AREA

PIN 1

(4X) 0.15

PACKAGE

2.00

1.55±0.10

0.90±0.10

0.22

( 6x0.50 )

( 8x0.22 )

2.00

( 8x0.30 )

( 8x0.20 )

( 8x0.30 )

0.50

0.90

1.55

0.90±0.10

INDEX AREA

OUTLINE

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance: Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the termi nal tip.

Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1 994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

ISL6208, ISL6208B

13 FN9115.6

January 31, 2012

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 3, 3/11

DETAIL "A"

TOP VIEW

INDEX

AREA

123

-C-

SEATING PLANE

x 45°

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1982.

2. Package length does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

3. Package width does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatche d area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above the

seating plane, shall not exceed a maximum value of 0.61mm (0. 024 inch) .

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not

necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

SIDE VIEW “A

SIDE VIEW “B”

1.27 (0.050)

6.20 (0.244)

5.80 (0.228)

4.00 (0.157)

3.80 (0.150)

0.50 (0.20)

0.25 (0.01)

5.00 (0.197)

4.80 (0.189) 1.75 (0.069)

1.35 (0.053)

0.25(0.010)

0.10(0.004)

0.51(0.020)

0.33(0.013)

8°

0°

0.25 (0.010)

0.19 (0.008)

1.27 (0.050)

0.40 (0.016)

1.27 (0.050)

5.20(0.205)

TYPICAL RECOMMENDED LAND PATTERN

2.20 (0.087)

0.60 (0. 023)