128M DDR SDRAM K4D263238M 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Revision 1.3 August 2001 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M Revision History Revision 1.3 (August 2, 2001) * Removed K4D263238M-QC40 with VDD&VDDQ=2.8V * Changed VDD&VDDQ of K4D263238M-QC45 from 2.8V to 2.5V. * Changed tCK(max) from 7ns to 10ns. Revision 1.2 (July 12, 2001) * Corrected CAS latency of K4D263238M-QC45 from CL3 to CL4 * The specification for the 222MHz/250MHz is preliminary one. Revision 1.1 (March 5, 2000) * Added K4D263238M-QC40 with VDD&VDDQ=2.8V * Changed VDD/VDDQ of K4D263238M-QC45 from 2.5V to 2.8V. Accordingly, DC current characteristics values have been changed. - Changed CAS latency of K4D263238M-QC45 from CL4 to CL3. * Changed tWPREH of K4D263238M-QC50 from 0.3tCK to 0.25tCK - 2 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M Revision 1.0 (December 13, 2000) * Defined capacitance values * Chagned tRCDWR of K4D263238M-QC60 from 1tCK to 2tCK Revision 0.5 (December 8, 2000) * Changed AC input level from Vref + 0.31V to Vref + 0.35V * Changed tRC/tRFC/tRAS/tRP/tRCDRD/tRCDWR from ns unit based from clock unit based. * Changed VIN /VOUT/VDDQ in absolute maximum ratings from -1.0V ~3.6V to -0.5V ~ 3.6V. Revision 0.4 (November 29, 2000) - Preliminary * Removed K4D263238M-QC40 * Several AC parameters of K4D263238M-QC45 have been changed - Changed tDQSQ from 0.4ns to 0.45ns. Changed tQH from tHP-0.6ns to tHP-0.45ns. - Changed tDQSCK & tAC from 0.6ns to 0.7ns - Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK. - Changed tDS/tDH from 0.4ns to 0.45ns. Changed tIS/tIH from 0.9ns to 1.0ns - Corrected tDAL from 5tCK to 6tCK * Several AC parameters of K4D263238M-QC50 have been changed - Changed tQH from tHP-0.6ns to tHP-0.45ns. - Changed tDQSCK & tAC from 0.6ns to 0.7ns - Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK. - Corrected tDAL from 5tCK to 6tCK * Several AC parameters of K4D263238M-QC55 have been changed - Changed tDQSQ from 0.45ns to 0.5ns. Changed tOH from tHP-0.6ns to tHP-0.5ns. - Changed tDQSCK & tAC from 0.6ns to 0.75ns - Changed tDS/tDH from 0.45ns to 0.5ns. Changed tIS/tIH from 1.0ns to 1.1ns - Changed tRC/tRFC from 60.5ns/71.5ns to 66ns/77ns. Changed tRP from 16.5ns to 22ns. - Corrected tRCDWR from 5.5ns to 11ns. Corrected tDAL from 5tCK to 6tCK * Changed tQH of K4D263238M-QC60 from tHP-0.75ns to tHP-0.5ns * Add DC Characteristics value * Define VIH(max) / V IL(min) as a note in Power & DC operating Condition table * Changed refresh cycle time from 16ms to 32ms.Accordingly, tREF has been changed from 3.9us to 7.8us. * Changed IIL,IOL test condition from 0V< VIN <VDD+0.3V to 0V< VIN <VDD. Revision 0.3 (June 8, 2000) * Removed Block Write function Revision 0.2 (April 10, 2000) * Separated tRCD into tRCDRD and tRCDWR - tRCDRD: Row to Column delay for READ - tRCDWR: Row to Column delay at WRITE Revision 0.1 (March 16, 2000) * Define the spec based on Vdd&Vddq=2.5V * Maximum target frequency upto 250MHz@CL4 * Removed Write Interrupt by Read function Revision 0.0 (December 27, 1999) - Target Spec * Defined Target Specification - 3 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL FEATURES * 2.5V 5% power supply * Data I/O transactions on both edges of Data strobe * SSTL_2 compatible inputs/outputs * DLL aligns DQ and DQS transitions with Clock transition * 4 banks operation * Edge aligned data & data strobe output * MRS cycle with address key programs * Center aligned data & data strobe input -. Read latency 3,4 (clock) * DM for write masking only -. Burst length (2, 4, 8 and Full page) * Auto & Self refresh -. Burst type (sequential & interleave) * 32ms refresh period (4K cycle) * Full page burst length for sequential burst type only * 100pin TQFP package * Start address of the full page burst should be even * Maximum clock frequency up to 222MHz * All inputs except data & DM are sampled at the positive * Maximum data rate up to 444Mbps/pin going edge of the system clock * Differential clock input * No Write Interrupted by Read function ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4D263238M-QC45 222MHz 444Mbps/pin K4D263238M-QC50 200MHz 400Mbps/pin K4D263238M-QC55 183MHz 366Mbps/pin K4D263238M-QC60 166MHz 333Mbps/pin Interface Package SSTL_2 100 TQFP GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 4 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CK CK CKE MCL A8(AP) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PIN CONFIGURATION (Top View) DQ29 81 50 A7 VSSQ 82 49 A6 DQ30 83 48 A5 DQ31 84 47 A4 VSS 85 46 VSS VDDQ 86 45 A9 N.C 87 44 N.C N.C 88 43 N.C N.C 89 42 N.C N.C 90 41 N.C N.C 91 40 N.C VSSQ 92 39 N.C RFU 93 38 N.C DQS 94 37 A11 VDDQ 95 36 A10 VDD 96 35 VDD DQ0 97 34 A3 DQ1 98 33 A2 VSSQ 99 32 A1 100 31 A0 20 x 14 mm2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DQ3 DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 WE CAS RAS CS BA0 BA1 0.65mm pin Pitch VDDQ DQ2 100 Pin TQFP PIN DESCRIPTION CK,CK Differential Clock Input BA 0, BA1 Bank Select Address CKE Clock Enable A 0 ~A11 Address Input CS Chip Select DQ 0 ~ DQ31 Data Input/Output RAS Row Address Strobe V DD Power CAS Column Address Strobe V SS Ground WE Write Enable V DDQ Power for DQs DQS Data Strobe V SSQ Ground for DQs DMi Data Mask MCL Must Connect Low RFU Reserved for Future Use - 5 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function CK, CK*1 Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQs and DM s that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQS Input/Output Data input and output are synchronized with both edge of DQS. DM0 ~ DM3 Input Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM 2 for DQ16 ~ DQ23, DM 3 for DQ24 ~ DQ31. DQ 0 ~ DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA0, BA1 Input Selects which bank is to be active. A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA 11, Column addresses : CA 0 ~ CA7. Column address CA8 is used for auto precharge. VDD/VSS Power Supply Power and ground for the input buffers and core logic. VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. MCL Must Connect Low Must connect Low *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. - 6 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank) 32 Intput Buffer I/O Control CK, CK Data Input Register Serial to parallel Bank Select LWE LDMi 64 1Mx32 32 Output Buffer 1Mx32 64 2-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer ADDR Address Register CK,CK 1Mx32 x32 DQi 1Mx32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length LRAS LCBR Strobe Gen. Programming Register LCKE Data Strobe DLL LWE LCAS LWCBR CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE - 7 - DMi Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M FUNCTIONAL DESCRIPTION * Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high. 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. Power up & Initialization Sequence 5 6 7 8 9 10 11 tRP 2 Clock min. 2 Clock min. tRP Command precharge ALL Banks EMRS MRS DLL Reset 1st Auto Refresh precharge ALL Banks 12 - 8 - 14 15 16 tRFC tRFC 200 Clock min. Inputs must be stable for 200us 13 4 2nd Auto Refresh 3 17 18 19 2 Clock min. Mode Register Set Any Command 2 1 0 CK CK Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 RFU 0 A11 A10 A9 RFU A8 A7 DLL TM A6 A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Address Bus Mode Register Burst Type Test Mode DLL A8 DLL Reset A3 Type A7 mode 0 Sequential 1 Interleave 0 No 0 Normal 1 Yes 1 Test Burst Length CAS Latency A2 A1 A0 Burst Type An ~ A0 A6 A5 A4 Latency Sequential Interleave 0 MRS 0 0 0 Reserved 0 0 0 Reserve Reserve 1 EMRS 0 0 1 Reserved 0 0 1 2 2 1 0 4 4 BA0 * RFU(Reserved for future use) should stay "0" during MRS cycle. 0 1 0 Reserved 0 0 1 1 3 0 1 1 8 8 1 0 0 4 1 0 0 Reserve Reserve 1 0 1 Reserved 1 0 1 Reserve Reserve 1 1 0 Reserved 1 1 0 Reserve Reserve Reserved 1 1 1 Full page Reserve 1 1 1 MRS Cycle 0 1 2 3 4 5 6 7 8 CK, CK Command NOP Precharge All Banks NOP NOP MRS NOP Any Command NOP NOP tMRD =2 tCK tRP *1: MRS can be issued only at all banks precharge state. *2: Minimum tRP is required to issue MRS command. - 9 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 RFU 1 BA0 A11 A10 A9 A8 A7 RFU A6 A5 D.I.C An ~ A 0 A6 A1 0 MRS 0 1 1 EMRS 1 1 A4 A3 A2 RFU Output Driver Impedance Control A1 A0 D.I.C DLL A0 Address Bus Extended Mode Register DLL Enable 60% of full drive strength 0 Enable Matched impedance 30% of full drive strength 1 Disable Weak * RFU(Reserved for future use) should stay "0" during EMRS cycle. Figure 7. Extend Mode Register set - 10 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VIN, V OUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 2.0 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, T A=0 to 65C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage VDD 2.375 2.50 2.625 V 1 Output Supply voltage VDDQ 2.375 2.50 2.625 V 1 Reference voltage VREF 0.49*VDDQ - 0.51*VDDQ V 2 Termination voltage Vtt VREF -0.04 VREF VREF +0.04 V 3 Input logic high voltage VIH VREF+0.15 - VDDQ +0.30 V 4 Input logic low voltage VIL -0.30 - VREF-0.15 V 5 Output logic high voltage VOH Vtt+0.76 - - V IOH=-15.2mA Output logic low voltage VOL - - Vtt-0.76 V IOL=+15.2mA Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 Note : 1. Under all conditions V DDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V REF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ , VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. V IL(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V VIN VDD is acceptable. For all other pins that are not under test VIN =0V. - 11 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, TA=0 to 65C) Parameter Version Symbol Test Condition Unit Note -45* -50 -55 -60 260 260 260 Operating Current (One Bank Active) ICC1 Burst Lenth=2 tRC tRC(min) IOL=0mA, tCC= tCC(min) 310 Precharge Standby Current in Power-down mode ICC2P CKE VIL(max), tCC= tCC(min) 90 Precharge Standby Current in Non Power-down mode ICC2N CKE VIH(min), CS VIH(min), tCC= tCC(min). 155 Active Standby Current power-down mode ICC3P CKE VIL(max), tCC= tCC(min) 105 Active Standby Current in in Non Power-down mode ICC3N CKE VIH(min), CS VIH(min), tCC= tCC(min) . 190 160 150 140 mA Operating Current ( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. 660 550 500 460 mA Refresh Current ICC5 tRC tRFC(min) 380 330 320 320 mA Self Refresh Current ICC6 CKE 0.2V 5 80 135 mA 1 mA 130 125 95 mA mA 4 2 mA Note: 1. Measured with outputs open. 2. Refresh period is 32ms. AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to V SS=0V, VDD/ VDDQ =2.5V+ 5%, TA=0 to 65C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V Input Low (Logic 0) Voltage; DQ VIL - - VREF-0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK VIX 0.5*V DDQ-0.2 - 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same - 12 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M AC OPERATING TEST CONDITIONS (VDD/ VDDQ=2.5V+ 5% , TA= 0 to 65C) Parameter Value Unit Input reference voltage for CK(for single ended) 0.50*V DDQ V 1.5 V CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) 1.0 V/ns VREF+0.35/V REF-0.35 V VREF V Vtt V Input timing measurement reference level Output timing measurement reference level Output load condition Note See Fig.1 Vtt=0.5*VDDQ R T=50 Output Z0=50 VREF =0.5*VDDQ CLOAD=30pF (Fig. 1) Output Load Circuit CAPACITANCE (VDD=2.5V, TA= 25C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK ) CIN1 1.0 5.0 pF Input capacitance(A0~A 10, BA0~BA1) CIN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ0~DQ 31) COUT 1.0 6.0 pF Input capacitance(DM0 ~ DM3) CIN4 1.0 6.0 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between VDD and VSS C DC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ C DC2 0.1 + 0.01 uF Note : 1. VDD and V DDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. - 13 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M AC CHARACTERISTICS Parameter Symbol CL=3 CL=4 -45* Min -50 -55 -60 Max Min Max Min Max Min Max Unit 10 5.0 10 5.5 10 6.0 10 CK high level width 4.5 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ns ns tCK CK low level width 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns - +0.45 - +0.45 - +0.5 - +0.5 ns 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.8 1.2 0.8 1.2 0.75 1.25 0.75 1.25 tCK CK cycle time tCK tCH tCL DQS out access time from CK tDQSCK Output access time from CK tAC Data strobe edge to Dout edge tDQSQ Read preamble tRPRE Read postamble tRPST CK to valid DQS-in tDQSS DQS-In setup time tWPRES DQS-in hold time tWPREH DQS write postamble tWPST DQS-In high level width tDQSH DQS-In low level width tDQSL Note 1 0 - 0 - 0 - 0 - ns 0.25 - 0.25 - 0.25 - 0.25 - tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK tIS 1.0 - 1.0 - 1.1 - 1.1 - ns 1.0 - 1.0 - 1.1 - 1.1 - ns 0.45 - 0.45 - 0.5 - 0.5 - ns DQ and DM hold time to DQS tIH tDS tDH - 0.5 tCLmin or tCHmin - 0.5 tCLmin or tCHmin - ns tHP 0.45 tCLmin or tCHmin - Clock half period 0.45 tCLmin or tCHmin - ns 1 Data output hold time from DQS tQH tHP-0.45 - tHP-0.45 - tHP-0.5 - tHP-0.5 - ns 1 Address and Control input setup Address and Control input hold DQ and DM setup time to DQS - - - Simplified Timing @ BL=2, CL=3 tCH tCL tCK 0 1 2 3 4 5 6 7 8 CK, CK tIS CS tIH tDQSCK tDQSS DQS tRPST tRPRE tWPRES tDQSQ tDQSH tWPST tWPREH Hi-Z tDS tDH tAC DQ Da1 Db0 Da2 Db1 Hi-Z DM WRITEB COMMAND READA - 14 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL3, BL2) tHP 0 1 2 3 4 5 CK, CK CS DQS tDQSQ(max) tQH tDQSQ(max) Da0 DQ COMMAND Da1 READA - 15 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M AC CHARACTERISTICS (I) Parameter Row cycle time Symbol tRC tRFC tRAS RAS to CAS delay for Read tRCDRD RAS to CAS delay for Write tRCDWR Row precharge time tRP Row active to Row active tRRD Last data in to Row precharge tWR -45* -50 -55 -60 Unit Max Min Max Min Max Min Max 13 - 12 - 12 - 10 - tCK 1 1 Refresh row cycle time 15 - 14 - 14 - 12 - Row active time 9 100K 8 100K 8 100K 7 100K 4 - 4 - 4 3 2 - tCK tCK tCK tCK tCK tCK tCK Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to read comPower down exit time Refresh interval time 4 2 - 2 - - 2 - 2 - 2 - tCK - 1 2 - 1 2 - 1 2 2 - tCK tCK 6 - 6 - 6 - 5 - tCK 2 2 4 2 - tCDLR 2 tCCD tMRD 1 tDAL tXSR tPDEX tREF Note Min 4 2 2 2 2 2 3 2 200 - 200 - 200 - 200 - tCK 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - ns us 7.8 7.8 7.8 7.8 Note :1 For normal write operation, even numbers of Din are to be written inside DRAM - 16 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M (Unit : Number of Clock) AC CHARACTERISTICS (II) K4D263238M-QC45* Frequency 222MHz ( 4.5ns ) 200MHz ( 5.0ns ) 183MHz ( 5.5ns ) 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 4 3 3 3 3 tRC 13 12 12 10 9 tRFC 15 14 14 12 11 tRAS 9 8 8 7 6 tRCDRD 4 4 4 3 3 tRCDWR 2 2 2 2 2 tRP 4 4 4 3 3 tRRD 2 2 2 2 2 Unit K4D263238M-QC50 Frequency 200MHz ( 5.0ns ) 183MHz ( 5.5ns ) 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 3 3 3 3 tRC 12 12 10 9 tRFC 14 14 12 11 tRAS 8 8 7 6 tRCDRD 4 4 3 3 tRCDWR 2 2 2 2 tRP 4 4 3 3 tRRD 2 2 2 2 Unit K4D263238M-QC55 Frequency 183MHz ( 5.5ns ) 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 3 3 3 tRC 12 10 9 tRFC 14 12 11 tRAS 8 7 6 tRCDRD 4 3 3 tRCDWR 2 2 2 tRP 4 3 3 tRRD 2 2 2 Unit K4D263238M-QC60 Frequency 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 3 3 tRC 10 9 tRFC 12 11 tRAS 7 6 tRCDRD 3 3 tRCDWR 2 2 tRP 3 3 tRRD 2 2 Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK * - 17 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M Simplified Timing(2) @ BL=4, CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CK, CK BA[1:0] BAa A8/AP Ra ADDR (A0~A7, A9~,A11) Ra BAa BAa Ca BAa BAb Ra Rb Ra Rb BAa BAb Ca Cb WE DQS Da0 Da1 Da2 Da3 DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM ACTIVEA WRITEA COMMAND PRECH ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRP tRC Normal Write Burst (@ BL=4) tRRD Multi Bank Interleaving Write Burst (@ BL=4) - 18 - Rev. 1.3 (Aug. 2001) 128M DDR SDRAM K4D263238M PACKAGE DIMENSIONS (TQFP) Dimensions in Millimeters 0 ~ 7 17.20 0.20 14.00 0.10 #100 #1 23.20 0.20 0.575 20.00 0.10 0.825 0.30 0.08 0.13 MAX 0.65 0.09~0.20 1.00 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 0.20 - 19 - Rev. 1.3 (Aug. 2001)