1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
DORPPACKAGE
(TOPVIEW)
1
2
3
4
6
7
A
B
R
RE
DE
D
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
3.3-V RS-485 TRANSCEIVERS
Check for Samples: SN65HVD10, SN65HVD10Q, SN75HVD10,SN65HVD11, SN65HVD11Q, SN75HVD11,SN65HVD12, SN75HVD12
1FEATURES DESCRIPTION
The SN65HVD10, SN75HVD10, SN65HVD11,
•Operates With a 3.3-V Supply SN75HVD11, SN65HVD12, and SN75HVD12
•Bus-Pin ESD Protection Exceeds 16 kV HBM combine a 3-state differential line driver and
•1/8 Unit-Load Option Available (Up to 256 differential input line receiver that operate with a
Nodes on the Bus) single 3.3-V power supply. They are designed for
balanced transmission lines and meet or exceed
•Optional Driver Output Transition Times for ANSI standard TIA/EIA-485-A and ISO 8482:1993.
Signaling Rates (1) of 1 Mbps, 10 Mbps, and These differential bus transceivers are monolithic
32 Mbps integrated circuits designed for bidirectional data
•Meets or Exceeds the Requirements of ANSI communication on multipoint bus-transmission lines.
TIA/EIA-485-A The drivers and receivers have active-high and
active-low enables respectively, that can be externally
•Bus-Pin Short Circuit Protection From –7 V to connected together to function as direction control.
12 V Very low device standby supply current can be
•Low-Current Standby Mode . . . 1 µA Typical achieved by disabling the driver and the receiver.
•Open-Circuit, Idle-Bus, and Shorted-Bus The driver differential outputs and receiver differential
Failsafe Receiver inputs connect internally to form a differential input/
•Thermal Shutdown Protection output (I/O) bus port that is designed to offer
minimum loading to the bus whenever the driver is
•Glitch-Free Power-Up and Power-Down disabled or VCC = 0. These parts feature wide positive
Protection for Hot-Plugging Applications and negative common-mode voltage ranges, making
•SN75176 Footprint them suitable for party-line applications.
APPLICATIONS
•Digital Motor Control
•Utility Meters
•Chassis-to-Chassis Interconnects
•Electronic Security Stations
•Industrial Process Control
•Building Automation
•Point-of-Sale (POS) Terminals and Networks
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2002–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PACKAGE
SIGNALING UNIT LOADS TASOIC MARKING
RATE SOIC(1) PDIP
32 Mbps 1/2 SN65HVD10D SN65HVD10P VP10
10 Mbps 1/8 –40°C to 85°C SN65HVD11D SN65HVD11P VP11
1 Mbps 1/8 SN65HVD12D SN65HVD12P VP12
32 Mbps 1/2 SN75HVD10D SN75HVD10P VN10
10 Mbps 1/8 –0°C to 70°C SN75HVD11D SN75HVD11P VN11
1 Mbps 1/8 SN75HVD12D SN75HVD12P VN12
32 Mbps 1/2 SN65HVD10QD SN65HVD10QP VP10Q
–40°C to 125°C
10 Mbps 1/8 SN65HVD11QD SN65HVD11QP VP11Q
(1) The D package is available taped and reeled. Add an R suffix to the part number (i.e., SN75HVD11DR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1) (2)
UNIT
VCC Supply voltage range –0.3 V to 6 V
Voltage range at A or B –9 V to 14 V
Input voltage range at D, DE, R or RE –0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100 Ω, see Figure 11 –50 V to 50 V
IOReceiver output current –11 mA to 11 mA
A, B, and GND ±16 kV
Human body model(3)
Electrostatic All pins ±4 kV
discharge Charged-device model(4) All pins charge ±1 kV
Continuous total power dissipation See Dissipation Rating Table
Electrical Fast Transient/Burst(5) A, B, and GND ±4 kV
TJJunction temperature 170°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A and IEC 60749-26.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
(5) Tested in accordance with IEC 61000-4-4.
PACKAGE DISSIPATION RATINGS
PACKAGE TA≤25°C DERATING FACTOR(1) TA= 70°C TA= 85°C TA= 125°C
POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING
D(2) 597 mW 4.97 mW/°C 373 mW 298 mW 100 mW
D(3) 990 mW 8.26 mW/°C 620 mW 496 mW 165 mW
P 1290 mW 10.75 mW/°C 806 mW 645 mW 215 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.
2Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted MIN NOM MAX UNIT
VCC Supply voltage 3 3.6
VIor VIC Voltage at any bus terminal (separately or common mode) –7(1) 12
VIH High-level input voltage D, DE, RE 2 VCC V
VIL Low-level input voltage D, DE, RE 0 0.8
VID Differential input voltage Figure 7 –12 12
Driver –60
IOH High-level output current mA
Receiver –8
Driver 60
IOL Low-level output current mA
Receiver 8
RLDifferential load resistance 54 60 Ω
CLDifferential load capacitance 50 pF
HVD10 32
Signaling rate HVD11 10 Mbps
HVD12 1
TJ(2) Junction temperature 145 °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information regarding this specification.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input clamp voltage II=–18 mA –1.5 V
IO= 0 2 VCC
|VOD| Differential output voltage(2) RL= 54 Ω, See Figure 1 1.5 V
Vtest =–7 V to 12 V, See Figure 2 1.5
Change in magnitude of differential output
Δ|VOD| See Figure 1 and Figure 2 –0.2 0.2 V
voltage
VOC(PP) Peak-to-peak common-mode output voltage 400 mV
VOC(SS) Steady-state common-mode output voltage 1.4 2.5 V
See Figure 3
Change in steady-state common-mode output –0.0
ΔVOC(SS) 0.05 V
voltage 5
IOZ High-impedance output current See receiver input currents
D–100 0
IIInput current μA
DE 0 100
IOS Short-circuit output current –7 V ≤VO≤12 V –250 250 mA
C(OD) Differential output capacitance VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 16 pF
RE at VCC,Receiver disabled and
D&DE at VCC, 9 15.5 mA
driver enabled
No load
RE at VCC,
D at VCC, Receiver disabled and
ICC Supply current 1 5 μA
DE at 0 V, driver disabled (standby)
No load
RE at 0 V, Receiver enabled and
D&DE at VCC, 9 15.5 mA
driver enabled
No load
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) For TA>85°C, VCC is ±5%.
Copyright ©2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
www.ti.com
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
HVD10 5 8.5 16
tPLH Propagation delay time, low-to-high-level output HVD11 18 25 40 ns
HVD12 135 200 300
HVD10 5 8.5 16
tPHL Propagation delay time, high-to-low-level output HVD11 18 25 40 ns
HVD12 135 200 300
HVD10 3 4.5 10
RL= 54 Ω, CL= 50 pF,
trDifferential output signal rise time HVD11 10 20 30 ns
See Figure 4
HVD12 100 170 300
HVD10 3 4.5 10
tfDifferential output signal fall time HVD11 10 20 30 ns
HVD12 100 170 300
HVD10 1.5
tsk(p) Pulse skew (|tPHL –tPLH|) HVD11 2.5 ns
HVD12 7
HVD10 6
tsk(pp) (2) Part-to-part skew HVD11 11 ns
HVD12 100
HVD10 31
Propagation delay time,
tPZH HVD11 55 ns
high-impedance-to-high-level output HVD12 300
RL= 110 Ω, RE at 0 V,
See Figure 5
HVD10 25
Propagation delay time,
tPHZ HVD11 55 ns
high-level-to-high-impedance output HVD12 300
HVD10 26
Propagation delay time,
tPZL HVD11 55 ns
high-impedance-to-low-level output HVD12 300
RL= 110 Ω, RE at 0 V,
See Figure 6
HVD10 26
Propagation delay time,
tPLZ HVD11 75 ns
low-level-to-high-impedance output HVD12 400
RL= 110 Ω, RE at 3 V,
tPZH Propagation delay time, standby-to-high-level output 6 μs
See Figure 5
RL= 110 Ω, RE at 3 V,
tPZL Propagation delay time, standby-to-low-level output 6 μs
See Figure 6
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT+ Positive-going input threshold voltage IO=–8 mA -0.01 V
Negative-going input threshold
VIT–IO= 8 mA –0.2
voltage
Vhys Hysteresis voltage (VIT+ - VIT-) 35 mV
VIK Enable-input clamp voltage II=–18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH =–8 mA, See Figure 7 2.4 V
VOL Low-level output voltage VID =–200 mV, IOL = 8 mA, See Figure 7 0.4 V
IOZ High-impedance-state output current VO= 0 or VCC RE at VCC –1 1 μA
VAor VB= 12 V 0.05 0.11
VAor VB= 12 V, VCC = 0 V 0.06 0.13
HVD11, HVD12, mA
Other input at 0 V
VAor VB=–7 V –0.1 –0.05
VAor VB=–7 V, VCC = 0 V –0.05 –0.04
IIBus input current VAor VB= 12 V 0.2 0.5
VAor VB= 12 V, VCC = 0 V 0.25 0.5
HVD10, mA
Other input at 0 V
VAor VB=–7 V –0.4 –0.2
VAor VB=–7 V, VCC = 0 V –0.4 –0.15
IIH High-level input current, RE VIH = 2 V –30 0 μA
IIL Low-level input current, RE VIL = 0.8 V –30 0 μA
CID Differential input capacitance VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 15 pF
RE at 0 V, Receiver enabled and driver
D&DE at 0 V, 4 8 mA
disabled
No load
RE at VCC,
D at VCC, Receiver disabled and driver
ICC Supply current 1 5 μA
DE at 0 V, disabled (standby)
No load
RE at 0 V, Receiver enabled and driver
D&DE at VCC, 9 15.5 mA
enabled
No load
(1) All typical values are at 25°C and with a 3.3-V supply.
Copyright ©2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Propagation delay time, low-to-high-level output HVD10 12.5 20 25 ns
tPHL Propagation delay time, high-to-low-level output HVD10 12.5 20 25
HVD11
tPLH Propagation delay time, low-to-high-level output 30 55 70 ns
HVD12 VID =–1.5 V to 1.5 V,
HVD11 CL= 15 pF,
tPHL Propagation delay time, high-to-low-level output 30 55 70 ns
HVD12 See Figure 8
HVD10 1.5
tsk(p) Pulse skew (|tPHL –tPLH|) HVD11 4 ns
HVD12 4
HVD10 8
tsk(pp) (2) Part-to-part skew HVD11 15 ns
HVD12 15
trOutput signal rise time 1 2 5
CL= 15 pF, ns
See Figure 8
tfOutput signal fall time 1 2 5
tPZH (1) Output enable time to high level 15
tPZL (1) Output enable time to low level 15
CL= 15 pF, DE at 3 V, ns
See Figure 9
tPHZ Output disable time from high level 20
tPLZ Output disable time from low level 15
tPZH (2) Propagation delay time, standby-to-high-level output 6
CL= 15 pF, DE at 0, μs
See Figure 10
tPZL (2) Propagation delay time, standby-to-low-level output 6
(1) All typical values are at 25°C and with a 3.3-V supply
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High−K board(3), No airflow D pkg 121
Junction−to−ambient thermal
θJA resistance(2) No airflow(4) P pkg 93
High−K board D pkg 67
Junction−to−board thermal
θJB °C/W
resistance See (4) P pkg 57
D pkg 41
Junction−to−case thermal
θJC resistance P pkg 55
HVD10 198 250
(32 Mbps)
RL= 60 Ω, CL= 50 pF,
DE at VCC, RE at 0 V, HVD11 141 176
PDDevice power dissipation mW
Input to D a 50% duty cycle square (10 Mbps)
wave at indicated signaling rate HVD12 133 161
(500 kbps)
High−K board, No airflow D pkg –40 116
TAAmbient air temperature No airflow(4) P pkg –40 123 °C
TJSD Thermal shutdown junction temperature 165
(1) See Application Information section for an explanation of these parameters.
(2) The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(3) JSD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(4) JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
6Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
60 Ω±1%
VOD
0or3V
_
+−7V<V(test) <12V
DE
VCC
A
B
D
375 Ω±1%
375 Ω±1%
IOA
VOD 54 Ω±1%
0or3V
VOA
VOB
IOB
DE
VCC
II
VI
A
B
VOC
27 Ω ± 1%
Input
A
B
VA
VB
VOC(PP) ∆VOC(SS)
VOC
27 Ω ± 1%
CL = 50 pF ±20%
DA
B
DE
VCC
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
CL Includes Fixture and
Instrumentation Capacitance
VOD
RL = 54 Ω
± 1%
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
tPLH tPHL
1.5 V 1.5 V
3 V
≈ 2 V
≈ –2 V
90%
10%
0 V
VI
VOD
trtf
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VCC
VI
Input
Generator 90% 0 V
10%
RL = 110 Ω
± 1%
Input
Generator 50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3 V S1
0.5 V
3 V
0 V
VOH
≈ 0 V
tPHZ
tPZH
1.5 V 1.5 V
VI
VO
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VO
VI
2.3 V
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD Test Circuit and Voltage and Figure 2. Driver VOD With Common-Mode Loading
Current Definitions Test Circuit
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Copyright ©2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
Input
Generator 50 Ω
3 V VO
S1
3 V
1.5 V 1.5 V
tPZL tPLZ
2.3 V 0.5 V
≈ 3 V
0 V
VOL
VI
VO
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
RL = 110 Ω
± 1%
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VI
≈ 3 V
Input
Generator 50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
1.5 V
0 V
1.5 V 1.5 V
3 V
VOH
VOL
1.5 V
10%
1.5 V
tPLH tPHL
trtf
90%
VI
VO
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
A
B
RE
VI
R
0 V
90%
10%
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 7. Receiver Voltage and Current Definitions
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
8Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
RE
R
A
B
3 V
0 V or 3 V
3 V
1.5 V 1.5 V
tPZH(1) tPHZ
1.5 V VOH –0.5 V
3 V
0 V
VOH
≈ 0 V
VO
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VI
DE
D1 kΩ ± 1%
VI
A
B
S1
D at 3 V
S1 to B
tPZL(1) tPLZ
1.5 V VOL +0.5 V
≈ 3 V
VOL
VO
D at 0 V
S1 to A
Input
Generator
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
Copyright ©2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
Input
Generator 50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
RE
R
A
B
3 V
1.5 V
tPZH(2)
1.5 V
3 V
0 V
VOH
GND
VI
VO
0 V or 1.5 V
1.5 V or 0 V CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VI
1 kΩ ± 1% A
B
S1
A at 1.5 V
B at 0 V
S1 to B
tPZL(2)
1.5 V
3 V
VOL
VO
A at 0 V
B at 1.5 V
S1 to A
Pulse Generator,
15 µs Duration,
1% Duty Cycle
tr, tf ≤ 100 ns
100 Ω
± 1%
_
+
A
BR
D
DE
RE
0 V or 3 V
NOTE:This test is conducted to test survivability only. Data stability at the R output is not specified.
3 V or 0 V
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
Figure 11. Test Circuit, Transient Over Voltage Test
10 Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
PARAMETER MEASUREMENT INFORMATION (continued)
FUNCTION TABLES
Table 1. DRIVER(1)
OUTPUTS
INPUT ENABLE A B
D DE
H H H L
L H L H
X L Z Z
Open H H L
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? =
indeterminate
Table 2. RECEIVER(1)
DIFFERENTIAL INPUTS ENABLE OUTPUT
VID = VA–VBRE R
VID ≤ –0.2 V L L
–0.2 V <VID < –0.01 V L ?
−0.01 V ≤VID L H
X H Z
Open Circuit L H
Short circuit L H
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? =
indeterminate
Copyright ©2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
9 V
1 kΩ
100 kΩ
Input
VCC
D and RE Inputs
9 V
1 kΩ
100 kΩ
Input
VCC
DE Input
16 V
16 V
R3 R1
R2
Input
A Input
16 V
16 V
R3 R1
R2
Input
B Input
16 V
16 V
VCC
A and B Outputs
9 V
VCC
R Output
5 ΩOutput
VCC
SN65HVD10
SN65HVD11
SN65HVD12
R1/R2
9 kΩ
36 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
VCC
Output
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
12 Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
30
40
50
60
70
0 2.5 5 7.5 10
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
Signaling Rate − Mbps
ICC− RMS Supply Current − mA
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
30
40
50
60
70
0 5 10 15 20 25 30 35 40
ICC
TA = 25°C
RE at VCC
DE at VCC
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
− RMS Supply Current − mA
Signaling Rate − Mbps
RL = 54 Ω
CL = 50 pF
30
40
50
60
70
100 400 700 1000
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
Signaling Rate − kbps
ICC− RMS Supply Current − mA
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
−200
−150
−100
−50
0
50
100
150
200
250
300
−7−6−5−4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
− Bus Input Current −IIAµ
VI − Bus Input Voltage − V
VCC = 0 V
VCC = 3.3 V
TA = 25°C
DE at 0 V
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS
HVD10 HVD11
RMS SUPPLY CURRENT RMS SUPPLY CURRENT
vs vs
SIGNALING RATE SIGNALING RATE
Figure 12. Figure 13.
HVD12 HVD10
RMS SUPPLY CURRENT BUS INPUT CURRENT
vs vs
SIGNALING RATE BUS INPUT VOLTAGE
Figure 14. Figure 15.
Copyright ©2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
−200
−150
−100
−50
0
50
100
150
−4 −2 0 2 4 6
TA = 25°C
DE at VCC
D at VCC
VCC = 3.3 V
VOH − Driver High-Level Output Voltage − V
IOH − High-Level Output Current − mA
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
−7−6−5−4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
− Bus Input Current −IIAµ
VI − Bus Input Voltage − V
VCC = 0 V
VCC = 3.3 V
TA = 25°C
DE at 0 V
− Driver Differential Output − V
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
−40 −15 10 35 60 85
VOD
TA − Free-Air Temperature − °C
VCC = 3.3 V
DE at VCC
D at VCC
−20
0
20
40
60
80
100
120
140
160
180
200
−4 −2 0 2 4 6 8
TA = 25°C
DE at VCC
D at 0 V
VCC = 3.3 V
VOL − Driver Low-Level Output Voltage − V
IOL− Low-Level Output Current − mA
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
HVD11 OR HVD12
BUS INPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
vs vs
BUS INPUT VOLTAGE DRIVER HIGH-LEVEL OUTPUT VOLTAGE
Figure 16. Figure 17.
LOW-LEVEL OUTPUT CURRENT DRIVER DIFFERENTIAL OUTPUT
vs vs
DRIVER LOW-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE
Figure 18. Figure 19.
14 Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
VCC − Supply Voltage − V
−35
−30
−25
−20
−40
−15
−10
−5
− Driver Output Current − mA
IO
00 0.50 1 1.50 2 2.50 3 3.50
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
HVD12
HVD11
0
100
400
500
600
-7 -2 3 8 13
HVD10
EnableTime − ns
V −
(TEST) Common-ModeVoltage − V
200
300
60 W
1%±
50 W
375 W1%±
-7V<V <12V
(TEST)
VOD
V (low)
OD
t (diff)
pZL
t (diff)
pZH
V
0or3V
375 W1%±
50%
0V
1.5V
D
Z
DE
Y
-1.5V
V (high)
OD
Input
Generator
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS (continued)ENABLE TIME
DRIVER OUTPUT CURRENT vs
vs COMMON-MODE VOLTAGE
SUPPLY VOLTAGE (SEE Figure 22)
Figure 20. Figure 21.
Figure 22. Driver Enable Time From DE to VOD
The time tPZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
Copyright ©2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
RTRT
Device
HVD10
HVD11
HVD12
Number of Devices on Bus
64
256
256
NOTE:The line should be terminated at both ends with its characteristic impedance (RT = ZO). Stub lengths of f the main line
should be kept as short as possible.
Stub
Driver Input
Driver Output
Receiver Input
Receiver Output
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
Figure 23. Typical Application Circuit
Figure 24. HVD12 Input and Output Through 2000 Feet of Cable
An example application for the HVD12 is illustrated in Figure 23. Two HVD12 transceivers are used to
communicate data through a 2000 foot (600 m) length of Commscope 5524 category 5e+ twisted pair cable. The
bus is terminated at each end by a 100-Ωresistor, matching the cable characteristic impedance. Figure 24
illustrates operation at a signaling rate of 250 kbps.
LOW-POWER STANDBY MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this
state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most
internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.
16 Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
THERMAL CHARACTERISTICS OF IC PACKAGES
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
•the PCB design (50% variation)
•altitude (20% variation)
•device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in θJA can be measured between these two test cards.
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of
package system, see Figure 25.
Figure 25. Thermal Resistance
Copyright ©2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K –FEBRUARY 2002–REVISED SEPTEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Revision J (February 2009) to Revision K Page
•Added new section 'LOW-POWER STANDBY MODE', in the Application Information section ......................................... 16
18 Submit Documentation Feedback Copyright ©2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
PACKAGE OPTION ADDENDUM
www.ti.com 2-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65HVD10D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD10DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD10DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD10DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD10P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD10PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD10QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD10QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD10QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD10QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD11D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD11DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD11DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD11DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD11P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD11PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD11QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD11QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 2-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65HVD11QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD11QDRG4 ACTIVE SOIC D 8 TBD Call TI Call TI
SN65HVD12D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD12DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD12DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD12DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD12P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD12PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD10D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD10DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD10DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD10DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD10P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD10PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD11D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD11DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD11DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD11DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD12D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD12DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 2-Sep-2011
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN75HVD12DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD12DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD12P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD12PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD10, SN65HVD11, SN65HVD12 :
•Enhanced Product: SN65HVD10-EP, SN65HVD12-EP
PACKAGE OPTION ADDENDUM
www.ti.com 2-Sep-2011
Addendum-Page 4
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD10DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD10QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD11DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD11QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD12DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75HVD10DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75HVD11DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75HVD12DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Sep-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD10DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD10QDR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD11DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD11QDR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD12DR SOIC D 8 2500 340.5 338.1 20.6
SN75HVD10DR SOIC D 8 2500 340.5 338.1 20.6
SN75HVD11DR SOIC D 8 2500 340.5 338.1 20.6
SN75HVD12DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Sep-2011
Pack Materials-Page 2
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