1A
GND
2A
1Y
VCC
2Y
1A
GND
2A
1Y
VCC
2Y
DRY PACKAGE
(TOP VIEW)
DSF PACKAGE
(TOP VIEW)
1
2
34
5
61
2
34
5
6
1
2
34
5
6
1A
GND
2A
1Y
VCC
2Y
YZP PACKAGE
(BOTTOM VIEW)
1A
GND
2A
1Y
VCC
2Y
DCK PACKAGE
(TOP VIEW)
1
2
34
5
6
1A
2A
1Y
VCC
2Y
DBV PACKAGE
(TOP VIEW)
1
2
34
5
6
SN74LVC2G17
www.ti.com
SCES381K JANUARY 2002REVISED JULY 2012
DUAL SCHMITT TRIGGER BUFFER
Check for Samples: SN74LVC2G17
1FEATURES
2 Available in the Texas Instruments NanoFree™ Typical VOHV (Output VOH Undershoot)
Package >2 V at VCC = 3.3 V, TA= 25°C
Supports 5-V VCC Operation Ioff Supports Partial-Power-Down Mode
Operation
Inputs Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 mA Per
Max tpd of 5.4 ns at 3.3 V JESD 78, Class II
Low Power Consumption, 10-μA Max ICC ESD Protection Exceeds JESD 22
±24-mA Output Drive at 3.3 V 2000-V Human-Body Model (A114-A)
Typical VOLP (Output Ground Bounce) 1000-V Charged-Device Model (C101)
<0.8 V at VCC = 3.3 V, TA= 25°C
DESCRIPTION/ORDERING INFORMATION
This dual Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G17 contains two buffers and performs the Boolean function Y = A. The device functions as two
independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going
(VT+) and negative-going (VT–) signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1A 1Y
1 6
2A 2Y
3 4
SN74LVC2G17
SCES381K JANUARY 2002REVISED JULY 2012
www.ti.com
ORDERING INFORMATION ORDERABLE TOP-SIDE
TAPACKAGE(1) (2) PART NUMBER MARKING(3)
NanoFree™ WCSP (DSBGA) Reel of 3000 SN74LVC2G17YZPR _ _ _C7_
0.23-mm Large Bump YZP (Pb-free)
QFN - DRY(4) Reel of 5000 SN74LVC2G17DRYR C7
µQFN - DSF(4) Reel of 5000 SN74LVC2G17DSFR C7
µQFN - DSF(4) Reel of 5000 SN74LVC2G17DSF2 C7
–40°C to 85°C Reel of 3000 SN74LVC2G17DBVR
SOT (SOT-23) DBV C17_
Reel of 250 SN74LVC2G17DBVT
Reel of 3000 SN74LVC2G17DCKR
SOT (SC-70) DCK C7_
Reel of 250 SN74LVC2G17DCKT
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
(4) ESD protection exceeds 150-V machine model.
FUNCTION TABLE
(EACH INVERTER)
INPUT OUTPUT
A Y
H H
L L
LOGIC DIAGRAM (POSITIVE LOGIC)
2Submit Documentation Feedback Copyright © 2002–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G17
SN74LVC2G17
www.ti.com
SCES381K JANUARY 2002REVISED JULY 2012
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VIInput voltage range(2) –0.5 6.5 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VOVoltage range applied to any output in the high or low state(2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
DBV package 165
DCK package 259
θJA Package thermal impedance (4) YZP package 123 °C/W
DRY package 234
DSF package 300
TJJunction temperature under bias 150 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN MAX UNIT
VCC Supply voltage Operating 1.65 5.5 V
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V –24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V 24
VCC = 4.5 V 32
TAOperating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2002–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN74LVC2G17
SN74LVC2G17
SCES381K JANUARY 2002REVISED JULY 2012
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
1.65 V 0.7 1.4
2.3 V 1 1.7
VT+
Positive-going input 3 V 1.3 2.0 V
threshold voltage 4.5 V 1.9 3.1
5.5 V 2.2 3.7
1.65 V 0.3 0.7
2.3 V 0.4 1
VT–
Negative-going input 3 V 0.8 1.3 V
threshold voltage 4.5 V 1.1 2
5.5 V 1.4 2.5
1.65 V 0.3 0.8
2.3 V 0.4 0.9
ΔVT
Hysteresis 3 V 0.4 1.1 V
(VT+ VT–)4.5 V 0.6 1.3
5.5 V 0.7 1.4
IOH = –100 μA 1.65 V to 5.5 V VCC 0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
VOH V
IOH = –16 mA 2.4
3 V
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100 μA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
VOL V
IOL = 16 mA 0.4
3 V
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
IIA input VI= 5.5 V or GND 0 to 5.5 V ±5 μA
Ioff VIor VO= 5.5 V 0 ±10 μA
ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 μA
ΔICC One input at VCC 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 μA
CiVI= VCC or GND 3.3 V 4 pF
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 3.9 9.3 1.9 5.7 2.2 5.4 1.5 4.3 ns
Operating Characteristics
TA= 25°C VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 17 18 19 21 pF
4Submit Documentation Feedback Copyright © 2002–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G17
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC2G17
www.ti.com
SCES381K JANUARY 2002REVISED JULY 2012
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2002–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN74LVC2G17
SN74LVC2G17
SCES381K JANUARY 2002REVISED JULY 2012
www.ti.com
REVISION HISTORY
Changes from Revision I (October 2009) to Revision J Page
Added orderable parts for DRY & DSF ................................................................................................................................. 2
Changes from Revision J (June 2012) to Revision K Page
Updated pin out graphic. ....................................................................................................................................................... 1
6Submit Documentation Feedback Copyright © 2002–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G17
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVC2G17DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DBVTE4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DCKT ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DRYR ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DSF2 ACTIVE SON DSF 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17DSFR ACTIVE SON DSF 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC2G17YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2G17 :
Automotive: SN74LVC2G17-Q1
Enhanced Product: SN74LVC2G17-EP
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC2G17DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G17DBVR SOT-23 DBV 6 3000 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3
SN74LVC2G17DBVT SOT-23 DBV 6 250 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3
SN74LVC2G17DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G17DCKR SC70 DCK 6 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC2G17DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC2G17DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G17DCKT SC70 DCK 6 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC2G17DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC2G17DSF2 SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3
SN74LVC2G17DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC2G17YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC2G17DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC2G17DBVR SOT-23 DBV 6 3000 205.0 200.0 33.0
SN74LVC2G17DBVT SOT-23 DBV 6 250 205.0 200.0 33.0
SN74LVC2G17DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G17DCKR SC70 DCK 6 3000 205.0 200.0 33.0
SN74LVC2G17DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G17DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC2G17DCKT SC70 DCK 6 250 205.0 200.0 33.0
SN74LVC2G17DRYR SON DRY 6 5000 180.0 180.0 30.0
SN74LVC2G17DSF2 SON DSF 6 5000 180.0 180.0 30.0
SN74LVC2G17DSFR SON DSF 6 5000 180.0 180.0 30.0
SN74LVC2G17YZPR DSBGA YZP 6 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
X: Max =
Y: Max =
1.43 mm, Min =
0.93 mm, Min =
1.37 mm
0.87 mm
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