MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
19-6465; Rev 0; 9/12
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX5318.related.
General Description
The MAX5318 is a high-accuracy, 18-bit, serial SPI input,
buffered voltage output digital-to-analog converter (DAC)
in a 4.4mm x 7.8mm, 24-lead TSSOP package. The
device features Q2 LSB INL (max) accuracy and a Q1
LSB DNL (max) accuracy over the full temperature range
of -40NC to +105NC.
The DAC voltage output is buffered resulting in a fast
settling time of 3Fs and a low offset and gain drift of
Q0.5ppm/NC of FSR (typ). The force-sense output (OUT)
maintains accuracy while driving loads with long lead
lengths. Additionally, a separate AVSS supply, allows the
output amplifier to go to 0V (GND) while maintaining full
linearity performance.
The MAX5318 includes user-programmable digital gain
and offset correction to enable easy system calibration.
At power-up, the device resets its outputs to zero or mid-
scale. The wide 2.7V to 5.5V supply voltage range and
integrated low-drift, low-noise reference buffer amplifier
make for ease of use.
The MAX5318 features a 50MHz 3-wire SPI interface. The
MAX5318 is available in a 24-lead TSSOP package and
operates over the -40NC to +105NC temperature range.
Applications
Benefits and Features
S Ideal for ATE and High-Precision Instruments
INL Accuracy Guaranteed with ±2 LSB (Max)
Over Temperature
S Fast Settling Time (3µs) with 10kI || 100pF Load
S Safe Power-Up-Reset to Zero or Midscale DAC
Output (Pin-Selectable)
Predetermined Output Device State in Power-Up
and Reset in System Design
S Negative Supply (AVSS) Option Allows Full INL
and DNL Performance to 0V
S SPI Interface Compatible with 1.8V to 5.5V Logic
S High Integration Reduces Development Time and
PCB Area
Buffered Voltage Output Directly Drives
2kI Load Rail-to-Rail
Integrated Reference Buffer
No External Amplifiers Required
S Small 4.4mm x 7.8mm, 24-Pin TSSOP Package
Test and Measurement
Equipment
Automatic Test Equipment
Gain and Offset
Adjustment
Data-Acquisition Systems
Process Control and
Servo Loops
Programmable Voltage
and Current Sources
Automatic Tuning and
Calibration
Communication Systems
Medical Imaging
Ordering Information and Typical Operating Circuit appear
at end of data sheet.
Functional Diagram
EVALUATION KIT AVAILABLE
18-BIT
DAC
INPUT/DAC
REGISTER
REF
CONTROL
LOGIC
SHUTDOWN
POWER-ON
RESET
SPI
INTERFACE
BUFFER
OUTPUT
BUFFER
V
DDIO
DGND BYPASS AGND_S AGND_F AVSS
AVDD1 AVDD2
REFO
RFB
OUT
7.8kI
7.8kI7.8kI
7.8kI
LDAC 5
9
8
7
6
2
4
1
3
10
11
23 22 13 19 20 12
15
16
17
21141824
READY
BUSY
RST
M/Z
TC/SB
PD
SCLK
DIN
DOUT
CS
AGND
MAX5318
DIGITAL
OFFSET
DIGITAL
GAIN
DIN
SPI
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
2Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
AGND to DGND ...................................................-0.3V to +0.3V
AGND_F, AGND_S to AGND ...............................-0.3V to +0.3V
AGND_F, AGND_S to DGND ...............................-0.3V to +0.3V
AVDD to AGND .......................................................-0.3V to +6V
AVDD to REF ...........................................................-0.3V to +6V
AVSS to AGND ........................................................-2V to +0.3V
VDDIO to DGND .......................................................-0.3V to +6V
BYPASS to DGND ....................................... -0.3V to the lower of
(VAVDD_ or VDDIO + 0.3V) and +4.5V
OUT, REFO, RFB to AGND ......................... -0.3V to the lower of
(VAVDD + 0.3V) and +6V
REF to AGND ...................-0.3V to the lower of VAVDD and +6V
SCLK, DIN, CS, BUSY, LDAC, READY,
M/Z, TC/SB, RST, PD, DOUT to DGND ....... -0.3V to the lower of
(VDDIO + 0.3V) and +6V
Continuous Power Dissipation (TA = +70NC)
TSSOP (derate 13.9mW/NC above +70NC).............1111.1mW
Operating Temperature Range ........................ -40NC to +105NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
TSSOP
Junction-to-Case Thermal Resistance (qJA) ...............13°C/W
Junction-to-Ambient Thermal Resistance (qJA) ..........72°C/W
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
ELECTRICAL CHARACTERISTICS
(VAVDD = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB =
PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless
otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution N 18 Bits
Integral Nonlinearity (Note 3) INL
DIN = 0x00000 to 0x3FFFF
(binary mode), DIN = 0x20000 to 0x1FFFF
(two’s complement mode)
-2 Q0.5 +2 LSB
DIN = 0x01900 to 0x3FFFF (binary
mode), DIN = 0x21900 to 0x1FFFF (two’s
complement mode), VAVSS = 0V
Differential Nonlinearity (Note 3) DNL -1 Q0.275 +1 LSB
Zero Code Error OE DIN = 0, TA = +25NC-48 Q4+48 LSB
DIN = 0, TA = -40NC to +105NCQ14
Zero Code Error Drift (Note 4) DIN = 0 -1.6 Q0.10 +1.6 ppm/NC
Gain Error GE TA = +25NC-16 Q1+16 LSB
TA = -40NC to +105NCQ27
Gain Error Temperature
Coefficient (Note 4) TCGE -2.5 Q0.10 +2.5 ppm/NC
of FSR
Output Voltage Range No load 0 VAVDD -
0.1 V
3Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB =
PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless
otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Reset Voltage Output VOUT-RESET
RST = pulse low M/Z = DGND 75 FV
M/Z = VDDIO 2.048 V
RST = pulse low,
VAVSS = 0V
M/Z = DGND 10 mV
M/Z = VDDIO 2.048 V
RST = DGND M/Z = DGND -68 mV
M/Z = VDDIO 2.036 V
RST = DGND,
VAVSS = 0V
M/Z = DGND 10 mV
M/Z = VDDIO 2.036 V
DC Output Impedance (Normal
Mode) ROUT Closed-loop connection (RFB connected
to OUT) 4mI
Output Resistance (Power-Down
Mode) PD = VDDIO 2kI
Output Current IOUT
Source/sink within 100mV of the supply
rails Q4
mA
Source/sink within 800mV of the supply
rails Q25
Load Capacitance to GND CL200 pF
Load Resistance to GND RLFor specified performance 2 kI
Short-Circuit Current ISC
OUT shorted to AGND or AVDD Q60
mAREFO shorted to AGND or AVDD Q65
BYPASS shorted to AGND or AVDD Q48
Short-Circuit Duration TSC Short to AGND or AVDD
Indefinite
s
DC Power-Supply Rejection DC PSRR VOUT at full scale, VAVDD = 4.5V to 5.5V -2.5 Q0.20 +2.5 LSB/V
VAVSS = -1.5V to -0.5V -2.5 Q0.012 +2.5
STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION
Reference High Input Range VREF 2.4 VAVDD -
0.1 V
Reference Input Capacitance CREF 10 pF
Reference Input Resistance RREF 10 MI
Reference Input Current IBQ0.15 FA
STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION
Reference High Output Range 2.4 VAVDD -
0.1 V
Reference High Output Load
Regulation 500 ppm/
mA
Reference Output Capacitor RESR < 5I0.1 nF
4Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB =
PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless
otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE—VBYPASS OUT SECTION
Output Voltage VBYPASS 2.3 2.4 2.5 V
Load Capacitance to GND CLRequired for stability, RESR = 0.1I (typ) 1 8 FF
POWER-SUPPLY REQUIREMENTS
Positive Analog Power-Supply
Range VAVDD 4.5 5.5 V
Digital Interface Power-Supply
Range VDDIO 1.8 VAVDD V
Negative Analog Power-Supply
Range VAVSS -1.5 -1.25 0 V
Positive Analog Power-Supply
Current IAVDD No load, external reference, output at zero
scale 5.2 6.5 mA
Negative Analog Power-Supply
Current IAVSS No load, external reference, output at zero
scale -1.5 -1.0 mA
Interface Power-Supply Current IVDDIO Digital inputs at VDDIO or DGND 0.2 5.0 FA
Positive Analog Power-Supply
Power-Down Current PD = VDDIO, power-down mode 20 50 FA
Negative Analog Power-Supply
Power-Down Current PD = VDDIO, power-down mode -5 -3 FA
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR From 10% to 90% full scale, positive and
negative transitions 4.9 V/Fs
Voltage Output Settling Time tS
From falling edge of LDAC to within
0.003% FS, RL = 10kI, DIN = 04000h
(6.25% FS) to 3C000h (93.75% FS)
3Fs
Busy Time tBUSY (Note 5) 1.9 Fs
DAC Glitch Impulse Major code transition (1FFFFh to 20000h),
RL = 10kI, CL = 50pF 4 nVs
Digital Feed Through CSB = VDDIO, fSCLK = 1kHz, all digital
inputs from 0V to VDDIO 1 nVs
Output Voltage-Noise Spectral
Density
At f = 1kHz to 10kHz, without reference,
code = 20000h 26 nV/Hz
Output Voltage Noise At f = 0.1Hz to 10Hz, without reference,
code = 20000h 1.55 FVP-P
Wake-Up Time From power-down mode 75 Fs
Power-Up Time From power-off 2 ms
5Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS
(VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC =
M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000,
TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution N 18 Bits
Integral Nonlinearity (Note 3) INL
DIN = 0x00000 to 0x3FFFF (binary
mode), DIN = 0x20000 to 0x1FFFF (two’s
complement mode) -2.0 Q0.75 +2.0 LSB
DIN = 0x01900 to 0x3FFFF (binary
mode), DIN = 0x21900 to 0x1FFFF (two’s
complement mode), VAVSS = 0V
Differential Nonlinearity (Note 3) DNL -1.0 Q0.3 +1.0 LSB
Zero Code Error OE DIN = 0, TA = +25NC -50 Q6 +50 LSB
DIN = 0, TA = -40NC to +105NCQ25
Zero Code Error Drift (Note 4) DIN = 0 -2.7 Q1.4 +2.7 ppm/NC
Gain Error GE TA = +25NC -16 Q1.5 +16 LSB
TA = -40NC to +105NCQ35
Gain Error Temperature
Coefficient (Note 4) TCGE -3.2 +3.2 ppm/NC
of FSR
Output Voltage Range No load 0 VAVDD -
0.1 V
Reset Voltage Output VOUT-RESET
RST = pulse low M/Z = DGND 75 FV
M/Z = VDDIO 1.25 V
RST = pulse low,
VAVSS = 0V
M/Z = DGND 10 mV
M/Z = VDDIO 1.25 V
RST = DGND M/Z = DGND -40 mV
M/Z = VDDIO 1.25 V
RST = DGND,
VAVSS = 0V
M/Z = DGND 10 mV
M/Z = VDDIO 1.24 V
DC Output Impedance ROUT Closed-loop connection, RFB connected
to OUT 4 mI
Output Current IOUT
Source/sink within 100mV of the supply rails Q4mA
Source/sink within 800mV of the supply rails Q25
Load Capacitance to GND CL200 pF
Load Resistance to GND RLFor specified performance 2 kI
Short-Circuit Current ISC
OUT shorted to AGND or AVDD Q60
mAREFO shorted to AGND or AVDD Q65
BYPASS shorted to AGND or AVDD Q48
Short-Circuit Duration tSC Short to AGND or AVDD
Indefinite
s
6Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC =
M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000,
TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC Power-Supply Rejection DCPSRR VOUT at full scale, VAVDD = 2.7V to 3.3V -2.5 Q0.4 +2.5 LSB/V
VAVSS = -1.5V to -0.5V -2.5 Q0.04 +2.5
STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION
Reference High Input Range VREF 2.4 VAVDD -
0.1 V
Reference Input Capacitance CREF 10 pF
Reference Input Resistance RREF 10 MI
Reference Input Current IB Q0.15 FA
STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION
Reference High Output Range 2.4 VAVDD -
0.1 V
Reference High Output Load
Regulation 500 ppm/mA
Reference Output Capacitor RESR < 5I0.1 nF
STATIC PERFORMANCE—VBYPASS OUT SECTION
Output Voltage VBYPASS 2.3 2.4 2.5 V
Load Capacitance to GND CLRequired for stability, RESR = 0.1I (typ) 1 8 FF
POWER-SUPPLY REQUIREMENTS
Positive Analog Power-Supply
Range VAVDD 2.7 3.3 V
Interface Power-Supply Range VDDIO 1.8 5.5 V
Negative Analog Power-Supply
Range VAVSS -1.5 -1.25 0 V
Positive Analog Power-Supply
Current IAVDD No load, external reference, output at zero
scale 5.0 6.5 mA
Negative Analog Power-Supply
Current IAVSS No load, external reference, output at zero
scale -1.5 -0.8 mA
Interface Power-Supply Current IVDDIO Digital inputs at VDDIO or DGND 0.2 5.0 FA
Positive Analog Power-Supply
Power-Down Current PD = VDDIO, power-down mode 20 50 FA
Negative Analog Power-Supply
Power-Down Current PD = VDDIO, power-down mode -5 -2 FA
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR From 10% to 90% full scale, positive and
negative transitions 4.9 V/Fs
Voltage Output Settling Time tS
From falling edge of LDAC to within
0.003% FS, RL = 10kI, DIN = 04000h
(6.25% FS) to 3C000h (93.75% FS)
3Fs
7Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC =
M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000,
TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
(VAVDD = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS
= 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Busy Time tBUSY (Note 5) 1.9 Fs
DAC Glitch Impulse Major code transition (1FFFFh to 20000h),
RL = 10kI, CL = 50pF 2.5 nVs
Digital Feedthrough CSB = VDDIO, fSCLK = 1kHz, all digital
inputs from 0V to VDDIO 1 nVs
Output Voltage-Noise Spectral
Density
At f = 1kHz to 10kHz, without reference,
code = 20000h 26 nV/Hz
Output Voltage Noise At f = 0.1Hz to 10Hz, without reference,
code = 20000h 1.55 FVP-P
Wake-Up Time From power-down mode 75 Fs
Power-Up Time From power-off 2 ms
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, DIN, CS, LDAC, M/Z, RST)
Input High Voltage VIH 0.7 x
VDDIO V
Input Low Voltage VIL 0.3 x
VDDIO V
Input Hysteresis (Note 4) VIHYST 200 300 mV
Input Leakage Current IIN Q0.1 Q1FA
Input Capacitance CIN 10 pF
DIGITAL OUTPUT CHARACTERISTICS (DOUT, READY, BUSY)
Output Low Voltage VOL ISOURCE = 5.0mA 0.25 V
Output High Voltage VOH ISINK = 5.0mA, except for BUSY VDDIO
- 0.25 V
Output Three-State Leakage IOZ DOUT only Q0.1 Q1FA
Output Three-State Capacitance COZ DOUT only 15 pF
Output Short-Circuit Current IOSS VDDIO = 5.25V Q150 mA
8Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS
= 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS
Serial Clock Frequency fSCLK
Stand-alone, write mode 50
MHz
Stand-alone, read mode and daisy-
chained read and write modes (Note 5) 12.5
SCLK Period tCP
Stand-alone, write mode 20
ns
Stand-alone, read mode and daisy-
chained read and write modes 80
SCLK Pulse Width High tCH 40% duty cycle 8 ns
SCLK Pulse Width Low tCL 40% duty cycle 8 ns
CS Fall to SCLK Fall Setup Time tCSSO First SCLK
falling edge
Stand-alone, write mode 8
ns
Stand-alone, read mode
and daisy-chained read
and write modes
38
CS Fall to SCLK Fall Hold Time tCSH0 Inactive falling edge preceding first falling
edge 0 ns
SCLK Fall to CS Rise Hold Time tCSH1 24th falling edge 2 ns
DIN to SCLK Fall Setup Time tDS 5 ns
DIN to SCLK Fall Hold Time tDH 4.5 ns
SCLK Rise to DOUT Settle Time tDOT CL = 20pF (Note 6) 32 ns
SCLK Rise to DOUT Hold Time tDOH CL = 0pF (Note 6) 2 ns
SCLK Fall to DOUT Disable Time tDOZ 24th active edge deassertion 2 30 ns
CS Fall to DOUT Enable tDOE Asynchronous assertion 2 30 ns
CS Rise to DOUT Disable tCSDOZ
Stand-alone, aborted sequence 35 ns
Daisy-chained, aborted sequence 70
SCLK Fall to READY Fall tCRF 24th falling-edge assertion, CL = 20pF 30 ns
SCLK Fall to READY Hold tCRH 24th falling-edge assertion, CL = 0pF 2 ns
SCLK Fall to BUSY Fall tCBF BUSY assertion 5 ns
CS Rise to READY Rise tCSR CL = 20pF 35 ns
CS Rise to SCLK Fall tCSA 24th falling edge, aborted sequence 20 ns
CS Pulse Width High tCSPW Stand alone 20 ns
SCLK Fall to CS Fall tCSF 24th falling edge 100 ns
LDAC Pulse Width tLDPW 20 ns
LDAC Fall to SCLK Fall Hold tLDH Last active falling edge 20 ns
RST Pulse Width tRSTPW 20 ns
9Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
(VAVDD = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS
= 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, DIN, CS, LDAC, M/Z, RST)
Input High Voltage VIH 0.8 x
VDDIO V
Input Low Voltage VIL 0.2 x
VDDIO V
Input Hysteresis (Note 4) VIHYST 200 300 mV
Input Leakage Current IIN Input = 0V at VDDIO Q0.1 Q1FA
Input Capacitance CIN 10 pF
DIGITAL OUTPUTS CHARACTERISTICS (DOUT, READY, BUSY)
Output Low Voltage VOL ISOURCE = 1.0mA 0.2 V
Output High Voltage VOH ISINK = 1.0mA, except for BUSY VDDIO
- 0.2 V
Output Three-State Leakage IOZ DOUT only Q0.1 Q1FA
Output Three-State Capacitance COZ DOUT only 15 pF
Output Short-Circuit Current IOSS VDDIO = 2.7V Q150 mA
TIMING CHARACTERISTICS
Serial Clock Frequency fSCLK
Stand-alone write mode 50
MHz
Stand-alone read mode and daisy-
chained read and write modes (Note 6) 8
SCLK Period tCP
Stand-alone write mode 20
ns
Stand-alone read mode and daisy-
chained read and write modes 125
SCLK Pulse-Width High tCH 40% duty cycle 9 ns
SCLK Pulse-Width Low tCL 40% duty cycle 9 ns
CS Fall to SCLK Fall Setup Time tCSSO First SCLK
falling edge
Stand-alone write mode 12
ns
Stand-alone read mode
and daisy-chained read
and write modes
72
CS Fall to SCLK Fall Hold Time tCSH0 Inactive falling edge preceding first
falling edge 0 ns
SCLK Fall to CS Rise Hold Time tCSH1 24th falling edge 4 ns
DIN to SCLK Fall Setup Time tDS 8 ns
DIN to SCLK Fall Hold Time tDH 8 ns
SCLK Rise to DOUT Settle Time tDOT CL = 20pF (Note 7) 40 ns
SCLK Rise to DOUT Hold Time tDOH CL = 0pF (Note 7) 2 ns
10Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS
= 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
Figure 1. Serial Interface Timing Diagram, Stand-Alone Operation
Note 2: All devices are 100% tested at TA = +25°C and TA = +105°C. Limits at TA = -40°C are guaranteed by design.
Note 3: Linearity is tested from VREF to AGND.
Note 4: Guaranteed by design.
Note 5: The total analog throughput time from DIN to VOUT is the sum of tS and tBUSY (4.9µs, typ).
Note 6: Daisy-chain speed is relaxed to accommodate (tCRF + tCSS0).
Note 7: DOUT speed limits overall SPI speed..
R3
12
tCSSO
345678 21 22 23 24 25
DIN
SCLK
tCSH0
R2 R1 R0 D17 D16 D15 D14 D1 D0 X––
0R3 R2 R1 R0 D17 D16 D15 D2 D1 D0 0 ZDOUT
CS
Z
tCSH1
tCSA
tDS
tDH
tCP
tCL
tCH
tDOH
tDOT
tDOE
tCSPW
tDOZ
tCRH
tCSF
tCRF tCSR
READY
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Fall to DOUT Disable Time tDOZ 24th active edge deassertion 2 40 ns
CS Fall to DOUT Enable tDOE Asynchronous assertion 2 50 ns
CS Rise to DOUT Disable tCSDOZ
Stand-alone, aborted sequence 70 ns
Daisy-chained, aborted sequence 130
SCLK Fall to READY Fall tCRF 24th falling edge assertion, CL = 20pF 60 ns
SCLK Fall to READY Hold tCRH 24th falling edge assertion, CL = 0pF 2 ns
SCLK Fall to BUSY Fall tCBF BUSY assertion 5 ns
CS Rise to READY Rise tCSR CL = 20pF 60 ns
CS Rise to SCLK Fall tCSA 24th falling edge, aborted sequence 20 ns
CS Pulse Width High tCSPW Stand alone 20 ns
SCLK Fall to CS Fall tCSF 24th falling edge 100 ns
LDAC Pulse Width tLDPW 20 ns
LDAC Fall to SCLK Fall Hold tLDH Last active falling edge 20 ns
RST Pulse Width tRSTPW 20 ns
11Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
MAX5318 toc01
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
CODE
INL (LSB)
19660813107265536
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
VREF = 5V
VAVDD = 5.25V
-2.0
0 262144
MAX5318 toc02
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
CODE
INL (LSB)
19660813107265536
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
VREF = 4.096V
VAVDD = 5V
-2.0
0 262144
MAX5318 toc03
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
CODE
INL (LSB)
19660813107265536
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
VREF = 2.5V
VAVDD = 3V
-2.0
0 262144
MAX5318 toc04
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
CODE
DNL (LSB)
19660813107265536
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
VREF = 5V
VAVDD = 5.25V
-2.0
0 262144
MAX5318 toc05
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
CODE
DNL (LSB)
19660813107265536
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
VREF = 4.096V
VAVDD = 5V
-2.0
0 262144
MAX5318 toc06
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
CODE
DNL (LSB)
19660813107265536
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
VREF = 2.5V
VAVDD = 3V
-2.0
0 262144
12Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics (continued)
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
DNL DISTRIBUTION vs. TEMPERATURE
MAX5318 toc09a
LSB
COUNT (NO. OF UNITS)
0.500.450.35 0.400.20 0.25 0.300.15
20
40
60
80
100
120
140
160
180
0
0.10
-40°C
+25°C
+105°C
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5318 toc10
TEMPERATURE (°C)
INL (LSB)
110956535 50 80520-25 -10
0
-40
-3.2
-2.4
-1.6
-0.8
0.8
1.6
2.4
3.2
4.0
-4.0
MIN INL
MAX INL
VREF = 4.096V
INL DISTRIBUTION vs. TEMPERATURE
MAX5318 toc10a
LSB
COUNT (NO. OF UNITS)
1.41.31.21.11.00.90.80.70.60.50.40.3
10
20
30
40
50
60
70
0
0.2
-40°C
+10°C
+25°C
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5318 toc07
TEMPERATURE (°C)
DNL (LSB)
110956535 50 80520-25 -10
0
-40
-1.6
-1.2
-0.8
-0.4
0.4
0.8
1.2
1.6
2.0
-2.0
MIN DNL
MAX DNL
VREF = 2.5V
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5318 toc08
TEMPERATURE (°C)
INL (LSB)
110956535 50 80520-25 -10
0
-40
-3.2
-2.4
-1.6
-0.8
0.8
1.6
2.4
3.2
4.0
-4.0
MIN INL
MAX INL
VREF = 2.5V
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5318 toc09
TEMPERATURE (°C)
DNL (LSB)
110956535 50 80520-25 -10
0
-40
-1.6
-1.2
-0.8
-0.4
0.4
0.8
1.2
1.6
2.0
-2.0
MIN DNL
MAX DNL
VREF = 4.096V
13Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics (continued)
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
INL DISTRIBUTION vs. TEMPERATURE
MAX5318 toc10b
LSB
COUNT (NO. OF UNITS)
1.41.31.21.11.00.90.80.70.60.50.40.3
10
20
30
40
50
60
70
0
0.2
+25°C
+40°C
+105°C
5.14.73.9 4.33.53.1
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5318 toc11
VAVDD (V)
DNL (LSB)
5.5
0
2.7
-1.6
-1.2
-0.8
-0.4
0.4
0.8
1.2
1.6
2.0
-2.0
MIN DNL
MAX DNL
VREF = 2.5V
5.14.73.9 4.33.53.1
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5318 toc12
VAVDD (V)
INL (LSB)
5.5
0
2.7
-1.6
-1.2
-0.8
-0.4
0.4
0.8
1.2
1.6
2.0
-2.0
MIN INL
MAX INL
VREF = 2.5V
4.84.43.6 4.03.22.8
DIFFERENTIAL NONLINEARITY
vs. REFERENCE VOLTAGE
MAX5318 toc13
REFERENCE VOLTAGE (V)
DNL (LSB)
5.2
0
2.4
-1.6
-1.2
-0.8
-0.4
0.4
0.8
1.2
1.6
2.0
-2.0
MIN DNL
MAX DNL
VAVDD = 5.25V
4.84.43.6 4.03.22.8
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
MAX5318 toc14
REFERENCE VOLTAGE (V)
INL (LSB)
5.2
0
2.4
-1.6
-1.2
-0.8
-0.4
0.4
0.8
1.2
1.6
2.0
-2.0
MIN INL
MAX INL
VAVDD = 5.25V
5.14.73.9 4.33.53.1
ZERO-SCALE OUTPUT ERROR
vs. SUPPLY VOLTAGE
MAX5318 toc15
VAVDD (V)
OUTPUT ERROR (LSB)
5.5
0
2.7
-1.6
-1.2
-0.8
-0.4
0.4
0.8
1.2
1.6
2.0
-2.0
VREF = 2.5V
CODE = 0x00000
14Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics (continued)
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
5.14.73.9 4.33.53.1
FULL-SCALE OUTPUT ERROR
vs. SUPPLY VOLTAGE
MAX5318 toc16
VAVDD (V)
OUTPUT ERROR (LSB)
5.5
0
2.7
-1.6
-1.2
-0.8
-0.4
0.4
0.8
1.2
1.6
2.0
-2.0
VREF = 2.5V
CODE = 0x3FFFF
ZERO-SCALE OUTPUT ERROR
vs. OUTPUT CURRENT
MAX5318 toc17
OUTPUT CURRENT (mA)
OUTPUT ERROR (LSB)
27243 6 9 15 1812 21
-3
-2
-1
0
1
2
3
4
-4
03
0
SOURCING
SINKING
CODE = 0x00000
VAVSS = -1.25V
VREF = 4.096V
ZERO CODE ERROR DISTRIBUTION
vs. TEMPERATURE
MAX5318 toc17a
LSB
COUNT (NO. OF UNITS)
5040-40 -30 -20 0 10 20-10 30
10
20
30
40
50
60
70
80
0
-50
-40°C
+10°C
+25°C
ZERO CODE ERROR DISTRIBUTION
vs. TEMPERATURE
MAX5318 toc17b
LSB
COUNT (NO. OF UNITS)
5040-40 -30 -20 0 10 20-10 30
10
20
30
40
50
60
70
80
0
-50
+25°C
+40°C
+105°C
ZERO CODE ERROR DRIFT
MAX5318 toc17c
DRIFT (ppm/°C)
COUNT (UNITS)
10
20
30
40
50
60
70
80
0
+10°C
-40°C
1.4 1.61.21.00.80.60.40.20
ZERO CODE ERROR DRIFT
MAX5318 toc17d
DRIFT (ppm/°C)
COUNT (UNITS)
10
20
30
40
50
60
70
0
+40°C
+105°C
1.4 1.61.21.00.80.60.40.20
15Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics (continued)
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
FULL-SCALE OUTPUT ERROR
vs. OUTPUT CURRENT
MAX5318 toc18
OUTPUT CURRENT (mA)
OUTPUT ERROR (LSB)
27243 6 9 15 1812 21
-3
-2
-1
0
1
2
3
4
-4
03
0
SOURCING
SINKING
CODE = 0x3FFFF
VREF = 4.096V
GAIN ERROR TEMPERATURE COEFFICIENT
MAX5318 toc18a
DRIFT (ppm/°C)
COUNT (UNITS)
10
20
30
40
50
60
70
0
+40°C
+105°C
0-0.4-0.6 -0.2-0.8-1.0-1.2-1.4-1.6-1.8-2.0
GAIN ERROR TEMPERATURE COEFFICIENT
MAX5318 toc18b
DRIFT (ppm/°C)
COUNT (UNITS)
10
20
30
40
50
60
70
0
+10°C
-40°C
0-0.4-0.6 -0.2-0.8-1.0-1.2-1.4-1.6-1.8-2.0
OUTPUT DRIVE CAPABILITY
MAX5318 toc19
OUTPUT CURRENT (mA)
OUTPUT ERROR (LSB)
764 52 31
-8
-6
-4
-2
0
2
4
6
8
10
-10
08
CODE = 0x01900
VAVSS = 0V
VREF = 4.096V
SINKING CURRENT
TA = +25°C
454030 3510 15 20 255
OUTPUT DRIVE CAPABILITY
MAX5318 toc20
OUTPUT CURRENT (mA)
OUTPUT ERROR (LSB)
-8
-6
-4
-2
0
2
4
6
8
10
-10
05
0
CODE = 0x00000
VAVSS = -1.25V
VREF = 4.096V
SINKING CURRENT
TA = +25°C
OUTPUT DRIVE CAPABILITY
MAX5318 toc21
OUTPUT CURRENT (mA)
OUTPUT ERROR (LSB)
764 52 31
-8
-6
-4
-2
0
2
4
6
8
10
-10
08
CODE = 0x3FFFF
VAVDD = 4.2V
VREF = 4.096V
SOURCING CURRENT
TA = +25°C
16Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics (continued)
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
454030 3510 15 20 255
OUTPUT DRIVE CAPABILITY
MAX5318 toc22
OUTPUT CURRENT (mA)
OUTPUT ERROR (LSB)
-8
-6
-4
-2
0
2
4
6
8
10
-10
05
0
CODE = 0x3FFFF
VAVDD = 5V
VREF = 4.096V
SOURCING CURRENT
TA = +25°C
454030 3510 15 20 255
OUTPUT DRIVE CAPABILITY
MAX5318 toc23
OUTPUT CURRENT (mA)
OUTPUT ERROR (LSB)
-8
-6
-4
-2
0
2
4
6
8
10
-10
05
0
CODE = 0x00000
VAVSS = -1.25V
VREF = 2.5V
SINKING CURRENT
TA = +25°C
454030 3510 15 20 255
OUTPUT DRIVE CAPABILITY
MAX5318 toc24
OUTPUT CURRENT (mA)
OUTPUT ERROR (LSB)
-7
-4
-1
2
5
8
11
14
17
27
-10
06
050 55
CODE = 0x3FFFF
VAVDD = 5V
VREF = 2.5V
SOURCING CURRENT
TA = +25°C
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5318 toc25
VAVDD (V)
IAVDD (mA)
5.255.004.75
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
5.0
4.50 5.50
TA = +105°C
TA = +25°C
TA = -40°C
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5318 toc26
VAVDD (V)
IAVDD (µA)
5.255.004.75
40
10
4.50 5.50
TA = +105°C
15
20
25
30
35
VPD = 5V
TA = +25°C
TA = -40°C
17Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics (continued)
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE
MAX5318 toc27
1s/div
VOUT
1µV/div
10k1k10010 100k
OUTPUT NOISE DENSITY
MAX5318 toc28
FREQUENCY (Hz)
VOLTAGE NOISE (nV/rt-Hz)
10
20
30
40
50
60
70
80
90
100
0
CODE = 0x20000
100
200
300
400
500
GROUND CURRENT vs. CODE
MAX5318 toc29
CODE
CURRENT (µA)
19660813107265536
600
CURRENT THROUGH
AGND_F AND AGND_S
VREF = 4.096V
0
0 262144
DIGITAL CLOCK FEEDTHROUGH
MAX5318 toc30
2µs/div
VOUT
1mV/div
VSCLK
5V/div
18Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics (continued)
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
MAJOR CARRY GLITCH
(1 LSB POSITIVE STEP)
MAX5318 toc31
400ns/div
VOUT
10mV/div
VLDAC
5V/div
MAJOR CARRY GLITCH
(1 LSB NEGATIVE STEP)
MAX5318 toc32
400ns/div
VOUT
10mV/div
VLDAC
5V/div
SETTLING TIME
(CODE = 0x3C000 to 0x04000)
MAX5318 toc33
1µs/div
VOUT
2V/div
VOUT
200µV/div
VLDAC
5V/div
SETTLING TIME
(CODE = 0x04000 to 0x3C000)
MAX5318 toc34
1µs/div
VOUT
2V/div
VOUT
200µV/div
VLDAC
5V/div
19Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Characteristics (continued)
(VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND,
RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.)
ENTERING POWER-DOWN RESPONSE
MAX5318 toc35
10µs/div
VOUT
2V/div
VPD
1V/div
RL = OPEN
EXITING POWER-DOWN RESPONSE
MAX5318 toc36
10µs/div
VOUT
2V/div
VPD
1V/div
SLOW POWER-UP RESPONSE
(RSTSEL = LOW)
MAX5318 toc37
4ms/div
VOUT
2V/div
VAVSS
2V/div
VBYPASS
2V/div
VREFO
2V/div
VAVDD
5V/div
SLOW POWER-UP RESPONSE
(RSTSEL = HIGH)
MAX5318 toc38
4ms/div
VOUT
2V/div
VAVSS
2V/div
VBYPASS
2V/div
VREFO
2V/div
VAVDD
5V/div
20Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Pin Description
Pin Configuration
M/Z
DOUT
DIN
SCLK
CS
AVDD2
AGND_F
AGND_S
REF
REFO
RST VDDIO
DGND
BYPASS
RFB
OUT
TC/SB
PD
AVSS AGND
AVDD1
BUSY
LDAC
READY
24
23
22
21
20
19
18
1
2
3
4
5
6
7
TOP VIEW
MAX5318
178
169
1510
1411
1312
TSSOP
+
PIN NAME FUNCTION
1RST
Active-Low Reset Input. Drive RST low to DGND to put the device into a reset state. A reset state sets all
SPI input registers to their default power-on reset states as defined by the state of inputs M/Z and TC/SB.
Set RST high to VDDIO, the DAC output remains at the state defined by M/Z until LDAC is taken low.
2READY
SPI Active-Low Ready Output. READY asserts low when the device successfully completes processing
an SPI data frame. READY asserts high at the next rising edge of CS. In daisy-chain applications, the
READY output typically drives the CS input of the next device in the chain or a GPIO of a microcontroller.
3 M/Z
Reset Select Input. M/Z selects the default state of the analog output (OUT) after power-on or a hardware
or software reset. Connect M/Z to VDDIO to set the default output voltage to midscale or to DGND to set
the default output voltage to zero scale.
4BUSY
Digital Input/Open-Drain Output. Connect a 2kI pullup resistor from BUSY to VDDIO. BUSY goes low
during the internal calculations of the DAC register data. During this time, the user can continue writing
new data to the DIN, OFFSET, and GAIN registers, but no further updates to the DAC register and
DAC output can take place. If LDAC is asserted low while BUSY is low, this event is stored. BUSY is
bidirectional, and can be asserted low externally to delay LDAC action. BUSY also goes low during
power-on reset, when RST is low, or when software reset is activated.
21Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Pin Description (continued)
PIN NAME FUNCTION
5LDAC
Active-Low Load DAC Logic Input. If LDAC is taken low while BUSY is inactive (high), the contents of the
input registers are transferred to the DAC register and the DAC output is updated. If LDAC is taken low
while BUSY is asserted low, the LDAC event is stored and the DAC register update is delayed until BUSY
deasserts. Any event on LDAC during power-on reset or when RST is low is ignored.
6 DOUT SPI Bus Serial Data Output. See the Serial Interface section for details.
7 DIN SPI Bus Serial Data Input. See the Serial Interface section for details.
8 SCLK SPI Bus Serial Clock Input. See the Serial Interface section for details.
9CS SPI Bus Active-Low Chip-Select Input. See the Serial Interface section for details.
10 TC/SB DIN Format Select Input. Connect TC/SB to DGND to set the data input format to straight binary or to
VDDIO to set it to two’s complement.
11 PD
Active-High Power-Down Input. Connect PD to DGND for normal operation. Connect PD to VDDIO to
place the device in power-down. In power-down, OUT (analog voltage output) is connected to AGND
through a 2kω resistor, but the contents of the input registers and the DAC latch do not change. The SPI
interface remains active in power-down.
12 AVSS Negative Analog Power-Supply Input. Connect to AGND or a negative supply voltage. When connected
to the negative supply voltage, bypass AVSS with a 0.1µF capacitor to AGND.
13 AGND Analog Ground. Connect to the analog ground plane.
14 AVDD1 Positive Analog Power-Supply Input. Bypass each AVDD_ locally with a 0.1µF and 10µF capacitor to
AGND (analog ground plane). Connect AVDD1 and AVDD2 together.
15 OUT
Buffered Analog Voltage Output. Connect OUT to RFB externally to close the output buffer feedback
loop. The buffered output is capable of directly driving a 10kω load. The state of M/Z sets the power-
on reset state of OUT (zero or midscale). In power-down, OUT is connected to AGND through a 2kω
pulldown resistor.
16 RFB Feedback Resistor Input. RFB is connected through the internal feedback resistor to the inverting input of
the analog output buffer. Externally connect RFB to OUT to close the output buffer feedback loop.
17 REFO Voltage Reference Buffered Output. Bypass with a 100pF capacitor to AGND.
18 REF High-Impedance 10Mω Voltage Reference Input
19 AGND_S DAC Analog Ground Sense
20 AGND_F DAC Analog Ground Force. Connect to the analog ground plane.
21 AVDD2 Positive Analog Power-Supply Input. AVDD2 supplies power to the internal digital linear regulator. Bypass
AVDD2 locally to AGND with 0.1µF and 10µF capacitors. Connect AVDD2 and AVDD1 together.
22 BYPASS Internal Bypass Connection. Connect BYPASS to DGND with 0.01µF and 1µF capacitors.
23 DGND Digital Ground
24 VDDIO Digital Interface Power-Supply Input. Connect to a 1.8V to 5.5V logic-level supply. Bypass VDDIO with a
0.1µF capacitor to DGND. The supply voltage at VDDIO sets the logic-level for the digital interface.
22Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Detailed Description
The MAX5318 is a high-accuracy, 18-bit, serial SPI input,
buffered voltage output digital-to-analog converter (DAC) in
a 4.4mm x 7.8mm, 24-lead TSSOP package. The device fea-
tures Q2 LSB INL (max) accuracy and a Q1 LSB DNL (max)
accuracy over the full temperature range of -40NC to +105NC.
The DAC voltage output is buffered resulting in a fast settling
time of 3Fs and a low offset and gain drift of Q0.5ppm/NC of
FSR (typ). The force-sense output (OUT) maintains accuracy
while driving loads with long lead lengths. Additionally, a
separate AVSS supply allows the output amplifier to go to 0V
(GND) while maintaining full linearity performance.
The MAX5318 includes user-programmable digital gain and
offset correction capability to enable easy system calibration.
At power-up, the device resets its outputs to zero or mid-
scale, providing additional safety for applications, which
drive valves or other transducers that need to be off on
power-up. This is selected by the state of the M/Z input on
power-up.
The wide 2.7V to 5.5V supply voltage range and integrated
low-drift, low-noise reference buffer amplifier makes for ease
of use. Since the reference buffer input has a high input
resistance, an external buffer is not required. The device
accepts an external reference between 2.4V and VAVDD -
0.1V for maximum flexibility and rail-to-rail operation.
The MAX5318 features a 50MHz, 3-wire SPI, QSPI,
MICROWIRE, and DSP-compatible serial interface. The sep-
arate digital interface supply voltage input (VDDIO) is com-
patible with a wide range of digital logic levels from 1.8V to
5.5V, eliminating the need for separate voltage translators.
DAC Reference Buffer
The external reference input has a high input (REF) imped-
ance of 10MI||10pF and accepts an input voltage from
+2.4V to VAVDD - 0.1V. Connect an external reference
supply between REF and AGND. Bypass the reference
buffer output REFO to AGND with a 100pF capacitor.
Connect the anode of an external Schottky diode to REF
and the cathode to AVDD1 to prevent internal ESD diode
conduction in the event that the reference voltage comes
up before AVDD at power up. Follow the recommenda-
tions described in the Power-Supply Sequencing section.
Visit www.maximintegrated.com/products/references
for a list of available external voltage-reference devices.
Output Amplifier (OUT)
The MAX5318 includes an internal buffer for the DAC
output. The internal buffer provides improved load
regulation for the DAC output. The output buffer slews at
5V/Fs and drives up to 2kI in parallel with 200pF. The
buffer has a rail-to-rail output capable of swinging to
within 100mV of AVDD_ and AVSS.
The positive analog supply voltage (AVDD_) determines
the maximum output voltage of the device as AVDD_
powers the output buffer.
The output is diode clamped to ground, preventing nega-
tive voltage excursions beyond approximately -0.6V.
Negative Supply Voltage (AVSS)
The negative supply voltage (AVSS) determines the mini-
mum output voltage. If AVSS is connected to ground, the
output voltage can be set to as low as 100mV without
degrading linearity. For operation down to 0V, connect
AVSS to a negative supply voltage between -0.1V and
-1.5V. The MAX1735 is recommended for generating
-1.25V from a -5V supply.
Force/Sense
The MAX5318 uses force/sense techniques to ensure
that the load is regulated to the desired output volt-
age despite line drops due to long lead lengths. Since
AGND_F and AGND_S have code dependent ground
currents, a ground impedance less than 13mω ensures
that the INL will not degrade by more than 0.1 LSB. Form
a star ground connection (Figure 2a) near the device
with AGND_F, AGND_S, and AGND tied together. Always
refer remote DAC loads to this system ground for best
performance. Figure 2b shows how to configure the
device and an external op amp for proper force/sense
operation. The amplifier provides as much drive as
needed to force the sensed voltage (measured between
RFB and AGND_S) to equal the desired voltage.
23Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
18-Bit Ideal Transfer Function
The MAX5318 features 18-bit gain and 18-bit offset
adjustment as shown in Figure 3.
The incoming DIN code is multiplied and offset compen-
sated by the generic equation shown in Equation 1. The
resulting value is then applied to the DAC.
Equation 1) Generic gain and offset adjustment
DAC DIN GAIN OFFSET=×+
The GAIN code is always an 18-bit straight binary word.
The OFFSET code is always two’s complement. It is
therefore simply added to the output of the multiplier.
To guarantee that a gain of exactly 1 is possible, the
actual gain coefficient applied to DIN is as defined in
Equation 2.
Equation 2) Calculation of gain
( )
18
GAIN 1
G
2
+
=
When DIN is straight binary, the ideal transfer function is
given by:
Equation 3) Straight binary ideal transfer function
OUT DIN OFFSET
V GV V=×+
When DIN is two’s complement, the ideal transfer func-
tion is given by:
Equation 4) Two’s complement ideal transfer function
REF
OUT DIN OFFSET
V
V GV V
2
= +
VDIN and VOFFSET are the voltages to which the DIN and
OFFSET codes are converted and VOUT is the voltage at
the DAC output buffer. See the Conversion Formulas for
DIN, GAIN, and OFFSET section for equations needed
to convert the DIN and OFFSET codes into VDIN and
VOFFSET.
Figure 2a. Star Ground Connection
Figure 2b. Force/Sense Connection
Figure 3. Gain and Offset Adjustment
OUT
RFB
AGND_F
AGND_S
AGND
MAX5318
OUT
RFB
AGND
AGND_F
AGND_S
MAX5318
SPI
INTERFACE
OFFSET
GAIN
DIN DAC
REGISTER
LDAC
24Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
The data DIN can be either straight binary or two’s com-
plement. In straight binary, zero code results in a zero-
scale output. In two’s complement, zero code results in
a midscale output.
To better understand how GAIN and OFFSET affect the
output voltage, see Figure 4 and Figure 5. Consider
the generation of a ramp. For now assume OFFSET
is set to 0x00000. In straight binary mode, with GAIN
set to 0x3FFFF (G = 1), DIN starts from 0x00000 and
increases to 0x3FFFF. The output voltage will start at 0V
and increase to (VREF - 1 LSB). If GAIN is reduced, the
ramp will still start at 0V but the maximum level reached
is reduced.
With DIN set to two’s complement mode, to generate the
same ramp, DIN would start at 0x20000 and increase
until it wraps around to 0x00000. At this point the
DAC output would be midscale. DIN then increases to
0x1FFFF where the output would be full-scale -1 LSB. As
GAIN is reduced, the start of the ramp becomes larger
and the end of the ramp becomes smaller. The ramp is
therefore centered at midscale.
In both cases, a nonzero value for OFFSET results in the
output moving up or down.
Should the output of the gain and offset adjust block
overflow full-scale or underflow zero-scale, the data is
clipped so the DAC output will be clipped rather than
overflow or underflow.
The effect of gain and offset adjustment is shown in
Figure 4 for straight binary mode and Figure 5 for two’s
complement mode.
If any of the DIN, GAIN, or OFFSET registers is changed,
the device takes 1.9µs (tBUSY) to compute the new val-
ues to present to the DAC. While the device is computing
the new DAC value, the BUSY output is set low. See the
section on the BUSY output and LDAC input for details.
Figure 4. Gain and Offset Adjustment in Straight Binary Mode Figure 5. Gain and Offset Adjustment in Two’s Complement
Mode
POSITIVE OFFSET
FULL-SCALE
VOUT
VREF
0V
00000h20000h
MIDSCALE
GAIN < 0x3FFFF (G < 1)
ZERO-SCALE
DIN
IDEAL CHARACTERISTIC
NEGATIVE OFFSET
3FFFFh
POSITIVE OFFSET
FULL-SCALE
VOUT
VREF
0V
20000h00000h
MIDSCALE
GAIN < 0x3FFFF (G < 1)
ZERO-SCALE
DIN
IDEAL CHARACTERISTIC
NEGATIVE OFFSET
1FFFFh
25Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Conversion Formulas for DIN,
GAIN, and OFFSET
Tables 1a and 1b show how to convert the DIN code to
VDIN in straight binary and two’s complement modes.
Table 2 shows how to convert the GAIN code to the gain
factor G, which is multiplied with VDIN. Table 3 shows
how to convert the OFFSET code to VOFFSET, which is
summed with the product G•VDIN.
Input, Gain, and Offset Ranges
The ranges of DIN, GAIN, and OFFSET are summarized
in Table 4 to Table 6. Also shown are the range values
for the 18-bit MAX5318 with a 4.096V reference. Note that
VREF is the reference voltage applied to REF and 1 LSB
is equal to VREF/218.
Table 1a. Converting DIN to VDIN (Straight Binary Mode)
Table 2. Converting GAIN to G
Table 3. Converting OFFSET to VOFFSET
Table 1b. Converting DIN to VDIN (Two’s Complement Mode)
DIN EQUATION FOR VDIN RANGE
0x00000 to 0x3FFFF DIN REF 18
DIN
VV
2
= × 0V to (VREF - 1 LSB)
OFFSET EQUATION RANGE
0x20000 to 0x3FFFF -VREF/2 to -1 LSB
0x00000 to 0x1FFFF 0V to (VREF/2 - 1 LSB)
DIN EQUATION FOR VDIN AND VOFFSET RANGE
0x20000 to 0x3FFFF VREF/2 to -1 LSB
0x00000 to 0x1FFFF 0V to (VREF/2 -
1 LSB)
REF
DIN REF 18
V
DIN - 0x20000
VV -
2
2

= ×


DIN REF 18
CODE
VV
2
= ×
GAIN EQUATION RANGE
0x00000 to 0x3FFFF 1/218 to 1
18
GAIN 1
G
2
+
=
REF
OFFSET REF 18
V
OFFSET 0x20000
VV 2
2

=×−


OFFSET REF 18
OFFSET
VV
2
= ×
26Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Table 6. OFFSET Range
Table 7. Straight Binary DIN Examples
Table 4a. DIN Range (Straight Binary Mode)
Table 4b. DIN Range (Two’s Complement Mode)
Table 5. GAIN Range
RANGE OFFSET VOFFSET (V) VALUE (V)
Minimum 0x20000 -VREF/2 -2.048
Maximum 0x1FFFF (VREF/2 - 1 LSB) 2.047992188
DIN VDIN (V) GAIN G OFFSET VOFFSET (V) CALCULATION COMMENT
0x20000 2.048 0x2FFFF 0.75 0x10000 1.024
VOUT = 0.75 x
2.048 + 1.024
= 2.56V
For VOUT, use Equation 3
For VDIN, use Table 1a
For G, use Table 2
For VOFFSET, use Table 3 second
formula
0x30000 3.072 0x0FFFF 0.25 0x30000 -1.024
VOUT = 0.25 x
3.072 - 1.024
= 0.512V
For VOUT, use Equation 3
For VDIN, use Table 1a
For G, use Table 2
For VOFFSET, use Table 3 first
formula
RANGE DIN VDIN (V) VALUE (V)
Minimum 0x00000 0 0
Maximum 0x3FFFF (VREF - 1 LSB) 4.095984375
RANGE DIN VDIN (V) VALUE (V)
Minimum 0x20000 0 0
Maximum 0x1FFFF (VREF - 1 LSB) 4.095984375
RANGE GAIN G VALUE (V)
Minimum 0x00000 1/218 0.0000038147
Maximum 0x3FFFF 1 1
27Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Numerical Examples
Several numerical examples for the MAX5318, as shown
in Table 7 and Table 8, illustrate how the gain and off-
set control changes the output voltage. The examples
assume a reference voltage of 4.096V. Note that if the
result of the calculation results in an under- or over-range
output voltage, VOUT is set to its zero or full-scale value,
respectively. An under-range output is less than 0V and
an over-range output is greater than VREF - 1 LSB.
Reset
The device is reset upon power-on, hardware reset using
RST, or software reset using register 0x4, bit 15, com-
mand RSTSW. After reset, the value of the input register,
the DAC latch and the output voltage are set to the values
defined by the M/Z input. If a hardware reset occurs dur-
ing a SPI programming frame, anything before and after
the reset for the frame will be ignored. A software reset
initiated through the SPI interface takes effect after the
end of the valid frame.
Output State Upon Reset
The output voltage can be set to either zero or mid-
scale upon power-up, or a hardware or software reset,
depending on the state of the M/Z input. After power-up,
if the device detects that this input is low, the output volt-
age is set to zero scale. If M/Z is high, the output voltage
is set to midscale.
Note that during reset, when RST is low or RSTSW is set
to 0, the output voltage is set slightly lower than the value
after coming out of reset. During reset, the output voltage
is set to the values shown for the VOUT-RESET specifica-
tion in the Electrical Characteristics.
Power-Down
The device can be powered down by either hardware
(pulling PD high) or software (setting the PD_SW bit in
either the 0x4 or 0xC registers). Note that the hardware
and software inputs are ORed. Asserting either is enough
to place the device in power-down mode.
In order to restore normal operation to the device, satisfy
both of these conditions:
1) Pull PD low.
2) Set the bits PD_SW’s (in both 0x4 and 0xC registers)
to 0.
In power-down, the output is internally connected to
AGND through a 2kI resistor. The SPI interface remains
active and the DAC register content remains unchanged.
Data Format Selection
(Straight Binary vs. Two’s Complement)
The MAX5318 interprets the data code input (DIN) as
either straight binary or two’s complement. To choose the
straight binary format, set the TC/SB input low. For two’s
complement, set the input high.
Table 8. Two’s Complement DIN Examples
DIN VDIN (V) GAIN G OFFSET VOFFSET (V) CALCULATION COMMENT
0x30000 -1.024 0x2FFFF 0.75 0x08000 0.512
VOUT = 4.096/2
+ 0.75 x (-1.024)
+ 0.512 = 1.792V
For VOUT, use Equation 4
For VDIN, use Table 1b first formula
For G, use Table 2
For VOFFSET, use Table 3 second
formula
0x10000 1.024 0x0FFFF 0.25 0x38000 -0.512
VOUT = 4.096/2
+ 0.25 x 1.024
- 0.512 = 1.792V
For VOUT, use Equation 4
For VDIN, use Table 1b first formula
For G, use Table 2
For VOFFSET, use Table 3 first
formula
28Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
LDAC and BUSY Interaction
The BUSY line is open drain and is normally pulled up
by an external resistor. It is software-configurable bidi-
rectional and can be pulled down externally. If any of the
DIN, GAIN, and OFFSET registers is changed, the device
must calculate the value to be presented to the DAC reg-
ister. To indicate to the host processor that the device is
busy, the device pulls the BUSY output low. Once com-
putation is complete, the device releases BUSY and the
host processor can load the DAC by toggling the LDAC
input. If LDAC is set low while BUSY is low, the LDAC
event is latched and implemented when the computation
is complete and BUSY rises.
There are four ways in which the LDAC and BUSY out-
puts can be used. This is shown graphically in Figure 6.
1) The host sends a new command. The device sets BUSY
low. The host monitors BUSY to determine when it goes
high. The device then pulses LDAC low to update the
DAC.
2) The host sends a new command. The device sets
BUSY low. The host toggles LDAC low then high
before BUSY goes high. The device latches the LDAC
event but does not implement it until processing is
complete. Then, BUSY goes high and the device
updates the DAC.
3) LDAC is held low. The host sends a new command
and the device sets BUSY low. The device updates
the DAC when the processing is complete and BUSY
goes high.
4)
BUSY is pulled down externally to delay DAC update.
The BUSY pin is bidirectional. To use BUSY as an
input, set the NO_BUSY bit to 1 using the 0x4 or 0xC
command. When configured as an input, pulling BUSY
low at least 50ns before the device releases the line
delays DAC update. DAC update occurs only after
BUSY is released and goes high. If used as an input,
drive BUSY with an open-drain output with a pullup
to VDDIO. The processing required for calculating the
final DAC code is controlled by an internally generated
clock. The clock frequency is not related to any exter-
nal signals and the frequency is not precisely defined.
Therefore, if the DAC must be updated at a precise
time with the least amount of jitter, use option 1.
Figure 6. BUSY and LDAC Timing
DIN
SCLK
BUSY
BUSY
LDAC
LDAC
LDAC
LDAC
VOUT
VOUT
VOUT
VOUT
OPTION 1
INPUT REGISTER LOADED
OPTION 2
OPTION 3
OPTION 4 (USED AS INPUT)
X1 2X21 22 23 X
tBUSY
tS
tCBF
tLDH
50ns
tLDPW
BUSY PULLED LOW EXTERNALLY
29Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Serial Interface
Overview
The SPI interface supports speeds up to 50MHz. When
CS is high, the remaining interface inputs are disabled to
reduce transient currents. The interface supports daisy
chaining to enable multiple devices to be controlled on
the same SPI bus.
The device has a double-buffered interface consisting
of two register banks: the input register and the DAC
register. The input register for DIN/GAIN/OFFSET is con-
nected directly to the 24-bit SPI input shift register. The
DAC latch contains the DAC code after digital process-
ing and is loaded as defined in the LDAC and BUSY
Interaction section above.
A valid SPI frame is 24-bit wide with 4-bit command R3
to R0, 18-bit data D17 to D0, and 2 unused LSBs. A full
24-bit SPI command sequence is required for all SPI
command operations, regardless of the number of data
bits actually used for the command. Any commands
terminating with less than a full 24-bit sequence will be
aborted without impacting the operation of the part (sub-
ject to tCSA timing requirements). Data is not written into
the SPI input register or DAC and it continues to hold the
preceding valid data. If a command sequence with more
than 24 bits is provided, the command will be executed
on the 24th SCLK falling edge and the remainder of the
command will be ignored.
All SPI commands result in the device assuming con-
trol of the DOUT line from the first SCLK edge through
the 24th SCLK edge. After relinquishing the DOUT line,
the MAX5318 returns to a high-impedance mode. An
optional bus hold circuit can be engaged to hold DOUT
at its last bit value while not interfering with other devices
on the bus.
DOUT is disabled at power-up and must be enabled
through the SPI interface. When enabled, DOUT echoes
the 4-bit command plus 18-bit data, which is being
programmed. During readback, DOUT echoes the 4-bit
command followed by the true readback data depending
upon the type of read command. Table 9 shows the bit
positions for DOUT and DIN within the 24-bit SPI frame.
The device is designed such that SCLK idles low, and
DIN and DOUT change on the rising clock edge and get
latched on the falling clock edge. The SPI host controller
should be set accordingly.
Daisy-Chain SPI Operation Using READY Output
The READY pulse appears 24 clock cycles after the neg-
ative edge of CS as shown in Figure 7 and can therefore
be used as the CS line for the next device in the daisy
chain. Since the device looks at the first 24 bits of the
transmission following the falling edge of CS, it is pos-
sible to daisy-chain the device with different command
word lengths. READY goes high after CS is driven high.
To perform a daisy-chain write operation, drive CS low
and output the data serially to DIN. The propagation of
the READY signal then controls how the data is read by
the device. As the data propagates through the daisy
chain, each individual command in the chain is executed
on the 24th falling clock edge following the falling edge
of the respective CS input. To update just one device
in a daisy chain, send the no-op command to the other
device in the chain. To update the first device in the
chain, raise the CS input after writing to that device.
Because daisy-chain operation requires parallel-
ing the DOUTs of all the MAX5318 in the chain, the
NO_HOLDEN bit in register 0x4 or 0xC should be set
to 1 for all devices. Doing so ensures that DOUT goes
into high-impedance after the SPI frame is complete
(i.e. after the 24th clock cycle) as shown in Figure 8.
Stand-Alone Operation
The diagram in Figure 9 shows a stand-alone connec-
tion of the MAX5318 in a typical SPI application. If more
than one peripheral device shares the DOUT bus, the
NO_HOLDEN bit in register 0x4 or 0xC should be set to 1
for the MAX5318. Doing so ensures that DOUT goes into
high-impedance after the SPI frame is complete (i.e. after
the 24th clock cycle).
Note that ‘X’ is don’t care.
Table 9. SPI Command and Data Mapping with Clock Falling Edges
CLOCK
EDGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DIN R3 R2 R1 R0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
DOUT 0 R3 R2 R1 R0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X
30Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Figure 7. Daisy-Chain SPI Connection Terminating with a Standard SPI Device.
Figure 8. Daisy-Chain SPI Connection Timing
µC
SLAVE 1
SCLK
DIN
DOUT
MOSI
MISO
I/O
SCK
SLAVE 3
SCLK
DIN
DOUT
SLAVE 2
SCLK
DIN
DOUT
CS READY CS READY
CS READY
CS
DIN
DOUT1
SCLK
12324222120432123 2422215432123 2422215432
SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA
READY 1
READY 3
READY 2
DOUT2 HI-Z HI-Z
HI-Z
HI-Z
DOUT3
31Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Command and Register Map
All command and data registers have read and write
functionality. The register selected depends on the com-
mand select bits R[3:0]. Each write to the device consists
of 4 command select bits (R[3:0]), 18 data bits (which are
detailed in Table 11 to Table 19), and 2 don’t care LSBs.
A summary of the commands is shown in Table 10.
Applications Information
Power-On Reset (POR)
Upon power-on, the output is set to either zero-scale
(if M/Z is low) and midscale (if M/Z is high). The entire
register map is set to their default values as shown in
Table 11 to Table 19.
Figure 9. Stand-Alone Operation
Table 10. Register Map Summary
CSm
CS1
CS CS
SCLK
µC
DWRITE
DREAD
SCLK
DIN
DOUT
MAX5318
TO OTHER DEVICES/CHAINS
HEX R3 R2 R1 R0 FUNCTION
00000No-op. Used mainly in daisy-chain communications.
10001DIN register write
20010OFFSET register write
30011GAIN register write
40100Configuration register write
5–8 Reserved
91001DIN register read
A 1 0 1 0 OFFSET register read
B 1 0 1 1 GAIN register read
C 1 1 0 0 Configuration and status register read.
D–F Reserved
32Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Register Details
Table 11. No-Op Command (0x0)
Table 12a. Straight Binary DIN Write Register (TC/SB) = 0) (0x1)
Table 12b. Two’s Complement DIN Write Register (TC/SB) = 1) (0x1)
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME X X X X X X X X X X X X X X X X X X
DEFAULT X X X X X X X X X X X X X X X X X X
BIT NAME DESCRIPTION
17:0 Don’t care No action on SPI shift register and DAC input registers. Use for daisy-chain purposes when
R[3:0] = 0000.
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEFAULT 0x00000 when M/Z = DGND (zero scale)
0x20000 when M/Z = VDDIO (midscale)
BIT NAME DESCRIPTION
17:0 B[17:0]
18-bit DAC input code in straight binary format. For clarity, a few examples are shown below:
00 0000 0000 0000 0000 0x00000 zero scale
01 0000 0000 0000 0000 0x10000 quarter scale
10 0000 0000 0000 0000 0x20000 midscale
11 0000 0000 0000 0000 0x30000 three-quarter scale
11 1111 1111 1111 1111 0x3FFFF full scale - 1 LSB
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEFAULT 0x20000 when M/Z = DGND (zero scale)
0x00000 when M/Z = VDDIO (midscale)
BIT NAME DESCRIPTION
17:0 B[17:0]
18-bit DAC input code in two’s complement format. For clarity, a few examples are shown below:
10 0000 0000 0000 0000 0x20000 zero scale
11 0000 0000 0000 0000 0x30000 quarter scale
11 1111 1111 1111 1111 0x3FFFF midscale - 1 LSB
00 0000 0000 0000 0000 0x00000 midscale
00 0000 0000 0000 0001 0x00001 midscale + 1 LSB
01 0000 0000 0000 0000 0x10000 three-quarter scale
01 1111 1111 1111 1111 0x1FFFF full scale - 1 LSB
33Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Table 13. OFFSET Register Write in Two’s Complement (0x2)
Table 14. GAIN Write Register (0x3)
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEFAULT 0x00000—Zero Offset
BIT NAME DESCRIPTION
17:0 B[17:0]
18-bit offset code in two’s complement format. For clarity, a few examples are shown below:
10 0000 0000 0000 0000 0x20000 offset of -217
11 1111 1111 1111 1111 0x3FFFF offset of -1
00 0000 0000 0000 0000 0x00000 offset of 0
00 0000 0000 0000 0001 0x00001 offset of +1
01 1111 1111 1111 1111 0x1FFFF offset of 217 – 1
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEFAULT 0x3FFFF—Gain of 1
BIT NAME DESCRIPTION
17:0 B[17:0]
18-bit gain code. For clarity, a few examples are shown below:
11 1111 1111 1111 1111 3FFFF\h Gain of 1. (218 – 1 + 1)/218
11 1111 1111 1111 1110 3FFFE\h Gain of 0.999996. (218 – 2 + 1)/218
01 1111 1111 1111 1111 1FFFF\h Gain of 0.5. (217 – 1 + 1)/218
01 1111 1111 1111 1110 1FFFE\h Gain of 0.499996. (217 – 2 + 1)/218
00 0000 0000 0000 0000 00000\h Gain of 0.0000076. 1/218
34Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Table 15. General Configuration Write Register (0x4)
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME PD_SW NO_HOLDEN RST_SW NO_BUSY DOUT_ON X X X X X X X X X X X X X
DEFAULT 0 0 1 0 0 X X X X X X X X X X X X X
BIT NAME DESCRIPTION
17 PD_SW
Software PD (Power-Down). Equivalent to the PD input.
0: Normal mode
1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor.
16 NO_HOLDEN
SPI Bus Hold Enable.
0: Bus hold enabled for SPI DOUT output. DOUT stays at its last value after the SPI CS
input rises at the end of the SPI frame (i.e. after the 24th clock cycle).
1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS
input rises at the end of the SPI frame (i.e. after the 24th clock cycle).
15 RST_SW
Software Reset. Equivalent to the RST input.
0: Place device in reset
1: Normal operation
Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low)
14 NO_BUSY
BUSY Input Disable.
0: BUSY input is active.
1: BUSY input is disabled.
Note that this does not affect the BUSY bit in the General Configuration and Status
Register. The BUSY pin is bidirectional. When enabled, it can be pulled down externally
to delay DAC updates.
13 DOUT_ON
SPI DOUT Output Disable. DOUT is disabled by default.
0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the
duration of the SPI frame.
1: DOUT output enabled.
12:0 Don’t care. These bits are reserved for the corresponding read command.
35Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Table 16. DIN Read Register (0x9)
Table 17. OFFSET Read Register (0xA)
Table 18. GAIN Read Register (0xB)
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NAME DESCRIPTION
17:0 B[17:0] 18-bit DIN readback value.
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NAME DESCRIPTION
17:0 B[17:0] 18-bit OFFSET readback value in two’s complement.
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BIT NAME DESCRIPTION
17:0 B[17:0] 18-bit GAIN readback value.
36Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Table 19. General Configuration and Status Read Register (0xC)
BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME PD_SW NO_
HOLDEN RST_SW NO_BUSY DOUT_ON BUSY X X X X X X REV_ID[3:0] X X
DEFAULT 0 0 1 0 0 0 0 0 0 0 0 0 0001 0 0
BIT NAME DESCRIPTION
17 PD_SW
Software PD (Power-Down). Equivalent to the PD input.
0: Normal mode.
1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor.
16 NO_HOLDEN
SPI Bus Hold Enable.
0: Bus hold enabled for SPI DOUT output. DOUT stays at its final value after the SPI CS input
rises at the end of the SPI frame.
1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS
input rises at the end of the SPI frame.
15 RST_SW
Software Reset. Equivalent to the RST input.
0: Place device in reset.
1: Normal operation.
Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low).
14 NO_BUSY
BUSY Input Disable.
0: BUSY input is active.
1: BUSY input is disabled.
Note that this does not affect the BUSY bit in the General Configuration and Status Register.
The BUSY pin is bidirectional. When enabled, it can be pulled down externally to delay DAC
updates.
13 DOUT_ON
SPI DOUT Output Disable. DOUT is disabled by default.
0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the duration
of the SPI frame.
1: DOUT output enabled.
12 BUSY
Global BUSY status readback.
0: Device is busy calculating output voltage.
1: Device is not busy.
11:6 Reserved. Will read back 0.
5:2 REV_ID[3:0] Device revision
1:0 Reserved. Will read back 0.
37Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Power Supplies and
Bypassing Considerations
For best performance, use a separate supply for the
MAX5318. Bypass VDDIO, AVDD_, and AVSS with high-
quality ceramic capacitors to a low-impedance ground
as close as possible to the device. A typical high-quality
X5R 10FF capacitor can become self resonant at 2MHz.
Therefore, it is actually an inductor above 2MHz and is
useless for decoupling signals above 2MHz. It is there-
fore recommended that several capacitors of different
values are connected in parallel. Figure 10 shows the
magnitude of impedance of typical 1FF, 100nF, and
10nF X5R capacitors. As the capacitance reduces, the
self-resonant frequency increases. In addition, the paral-
lel combination of all three is shown and exhibits a sig-
nificant improvement over a single capacitor. These plots
do not include any PCB trace inductance.
Minimize lead lengths to reduce lead inductance. Adding
just 2nH trace inductance to each of the typical capaci-
tors above produces the effects shown in Figure 11. This
shows significant reduction in the self-resonant frequen-
cies of the capacitors.
Internal Linear Regulator (BYPASS)
BYPASS is the output of an internal linear regulator and is
used to power digital circuitry. Connect BYPASS to DGND
with a ceramic capacitor in the range of 1FF to 10FF with
ESR in the range of 100mI to 20mI to ensure stability.
The typical voltage on this pin is 2.4V. Use a low-leakage
capacitor to ensure low power-down current.
Power-Supply Sequencing
During power-up, ensure that AVDD_ comes up before
the reference does. If this is not possible, connect a
Schottky diode between the REF and AVDD_ such as
the MBR0530T1G. If REF does come up before AVDD_,
the diode conducts and clamps REF to AVDD_. Once
AVDD_ has come up, the diode no longer conducts.
REF should always be below AVDD_ as specified in the
Electrical Characteristics. AVDD_ and AVDD_ should be
connected together and powered from the same supply.
VDDIO and AVSS can be sequenced in any order. Always
perform a reset operation after all the supplies are brought
up to place the device in a known operating state.
Layout Considerations
Digital and AC transient signals on AGND inputs can
create noise at the outputs. Connect both AGND inputs
to form the star ground for the DAC system. Refer remote
DAC loads to this system ground for the best possible
performance (see the Force/Sense section).
Use proper grounding techniques, such as a multilayer
board with a low-inductance ground plane, or star con-
nect all ground return paths back to AGND. Do not use
wire-wrapped boards and sockets. Use ground plane
shielding to improve noise immunity. Do not run analog
and digital signals parallel to one another (especially
clock signals) and avoid routing digital lines underneath
the device package.
For a recommended layout, consult the MAX5318
Evaluation Kit datasheet.
Figure 10. Typical X5R Capacitor Impedance Figure 11. Typical X5R Capacitor Impedance with Additional
2nH PCB Trace Inductance
3k
1k
100
10
1
100m
10m
100k 1M 10M 100M
4m
IMPEDANCE (I)
FREQUENCY (Hz)
10nF
1µF
100nF
3k
1k
100
10
1
100m
10m
100k 1M 10M 100M
4m
IMPEDANCE (I)
FREQUENCY (Hz)
10nF
1µF
100nF
10nF
1µF
100nF
38Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Voltage Reference Selection and Layout
The voltage reference should be placed close to the DAC.
The same power-supply decoupling and grounding rules
as the DAC should be implemented. Many voltage refer-
ences require an output capacitor for stability or noise
reduction. Provided the trace between the reference
device and the DAC is kept short and well shielded, a sin-
gle capacitor may be used and placed close to the DAC.
However, for improved noise immunity, additional capaci-
tors may be used but be careful not to exceed the recom-
mended capacitance range for the voltage reference.
Refer to Maxim Applications Note AN4300: Calculating
the Error Budget in Precision Digital-to-Analog Converter
(DAC) Applications for detailed description of voltage
reference parameters and trading off the error budget.
The MAX6126 is recommended for use with this device.
Optimizing Data Throughput Rate
The LDAC and BUSY Interaction section details the tim-
ing of data written to the device and how the DAC is
updated. Data throughput speed can be increased by
overlapping the data load time with the calibration and
settling time as shown below in Figure 12. Following the
24th SCLK falling edge, the device starts its calibration
period. Providing that the LDAC falling edge arrives
before the 24th SCLK falling edge, and assuming the SPI
clock frequency is high enough, the throughput period is
therefore limited by the internal calculation and settling
times only. A slight further increase in throughput time
can be gained by either toggling LDAC during the cal-
culation time or by pulling it low permanently. However,
the exact point at which the DAC update occurs is then
determined internally as indicated by the BUSY line rising
edge. This is not an exact time.
BUSY Line Pullup Resistor Selection
The BUSY pin is an open-drain output. It therefore
requires a pullup resistor. 2kI value is recommended as
a compromise between power and speed. Stray capaci-
tance on this line can easily slow the rise time to an
unacceptable level. The BUSY pin can sink up to 5mA.
Therefore a resistor as low as VDDIO/0.005 may be used
if faster rise times are required.
Producing Unipolar High-Voltage
and Bipolar Outputs
Figure 11 and Figure 12 show how external op amps can
be used to produce a unipolar high-voltage output and
a bipolar output
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function from
a straight line drawn between two codes. This line is drawn
between the zero and full-scale codes of the transfer func-
tion, once offset and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL is
less than or equal to 1 LSB, the DAC guarantees no miss-
ing codes and is monotonic.
Figure 12. Optimum Throughput with Stable Update Period
24TH SCLK
DIN
OUT
BUSY tBUSY
LDAC
24TH SCLK
LDAC FALLING EDGE BEFORE 24TH SCLK FALLING EDGE
39Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Offset Error
Offset error indicates how well the actual transfer func-
tion matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified
is at or near the zero-scale point of the transfer function.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a LDAC high-to-low transition or BUSY low-to-high
transition (whichever occurs last), until the DAC output
settles to within 0.003% of the final value.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
The glitch impulse occurs at the major carry transitions
along the segmented bit boundaries. It is specified as the
net area of the glitch impulse which appears at the output
when the digital input code changes by 1 LSB. The glitch
impulse is specified in nanovolts-seconds (nV-s).
Digital-to-Analog Power-Up Glitch Impulse
The digital-to-analog power-up glitch is the net area of
the glitch impulse which appears at the output when the
device exits power-down mode.
Figure 13. Unipolar High-Voltage Output Figure 14. Bipolar Output
OUT
0V TO KVREF
K = 1 + R2/R1
R2R1
MAX5318
MAX44250 OUT
REFO
-VREF
TO
VREF
R2
R1 = R2
R1
MAX5318
MAX9632
40Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Typical Operating Circuit
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information
2.4V TO (VAVDD - 0.1V) MBR0530T1G
VDDIO
2.0kI
24
REF
0.1µF 0.01µF
18
µC
GPIO’s
SPI
INTERFACE
0.1µF1µF 10µF
2.7V TO 5V
1.8V TO 5V
AVDD2
21
AVDD1
14
17 REFO
15 OUT
16 RFB
BYPASS
22
LINEAR
REGULATOR
MAX5318
23
DGND
13
AGND
19
AGND_S
20
AGND_F
12
AVSS
BUFFER
OUTPUT
BUFFER
0 TO -1.25V
4
BUSY
3
M/Z
10
TS/SB
11
PD
1
RST
5
LDAC
2
READY
9
CS
8
SCLK
7
DIN
6
DOUT
0.1µF
0.1µF
10µF
100pF
RL
INTERFACE
AND
CONTROL
DAC
REGISTER
DIGITAL GAIN
AND OFFSET
18-BIT
DAC
INPUT
REGISTER
PART TEMP RANGE PIN-PACKAGE
MAX5318GUG+ -40NC to +105NC24 TSSOP
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
24 TSSOP U24+1 21-0066 90-0118
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 41
© 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/12 Initial release