© Semiconductor Components Industries, LLC, 2012
November, 2017 − Rev. 3 1Publication Order Number:
FDMS3660S/D
FDMS3660S
PowerTrench) Power Stage
Asymmetric Dual N−Channel MOSFET
Description
This device includes two specialized N−Channel MOSFETs in a
dual PQFN package. The switch node has been internally connected to
enable easy placement and routing of synchronous buck converters.
The control MOSFET (Q1) and synchronous SyncFET (Q2) have
been designed to provide optimal power efficiency.
Features
Q1: N−Channel
•Max rDS(on) = 8 mW at VGS = 10 V, ID = 13 A
•Max rDS(on) = 11 mW at VGS = 4.5 V, ID = 11 A
Q2: N−Channel
•Max rDS(on) = 1.8 mW at VGS = 10 V, ID = 30 A
•Max rDS(on) = 2.2 mW at VGS = 4.5 V, ID = 27 A
•Low Inductance Packaging Shortens Rise/Fall Times, Resulting in
Lower Switching Losses
•MOSFET Integration Enables Optimum Layout for Lower Circuit
Inductance and Reduced Switch Node Ringing
•These Devices are Pb−Free and are RoHS Compliant
Applications
•Computing
•Communications
•General Purpose Point of Load
•Notebook VCORE
PQFN8
POWER 56
CASE 483AJ
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4
3
2
1
5
6
7
Q
81
Q
S2
S2
S2
G2
D1
D1
D1
G1
PHASE
2
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION
G1D1D1D1
G2S2 S2 S2
D1
PHASE
(S1/D2)
Pin 1
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MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Symbol Rating Q1 Q2 Unit
VDS Drain to Source Voltage 30 30 V
Bvdsst Bvdsst (Transient) < 100 ns 36 36 V
VGS Gate to Source Voltage (Note 3) ±20 ±12 V
IDDrain Current − Continuous (Package limited) (TC = 25°C) 30 60 A
Drain Current − Continuous (Silicon limited) (TC = 25°C) 60 145
Drain Current − Continuous (TA = 25°C) 13 (Note 6a) 30 (Note 6b)
Drain Current − Pulsed 40 120
EAS Single Pulse Avalanche Energy 33 (Note 4) 86 (Note 5) mJ
PDPower Dissipation for Single Operation (TA = 25°C) 2.2 (Note 6a) 2.5 (Note 6b) W
Power Dissipation for Single Operation (TA = 25°C) 1 (Note 6c) 1 (Note 6d)
TJ, TSTG Operating and Storage Junction Temperature Range −55 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
THERMAL CHARACTERISTICS
Symbol Parameter Q1 Q2 Unit
RqJA Thermal Resistance, Junction−to−Ambient 57 (Note 6a) 50 (Note 6b) °C/W
RqJA Thermal Resistance, Junction−to−Ambient 125 (Note 6c) 120 (Note 6d) °C/W
RqJC Thermal Resistance, Junction−to−Case 2.9 2.2 °C/W
PACKAGE MARKING AND ORDERING INFORMATION
Device Device Marking Package Reel Size Tape Width Quantity
FDMS3660S 22CF
07OD Power 56 13″12 mm 3000 Units
Table 1. ELECTRICAL CHARACTERISTICS TJ = 25°C unless otherwise noted
Symbol Parameter Test Conditions Type Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain to Source Breakdown Voltage ID = 250 mA, VGS = 0 V
ID = 1 mA, VGS = 0 V Q1
Q2 30
30 V
DBVDSS/
DTJ
Breakdown Voltage Temperature
Coefficient ID = 250 mA, referenced to 25°C
ID = 10 mA, referenced to 25°CQ1
Q2 16
24 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1
Q2 1
500 mA
mA
IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V
VGS = 12 V, VDS = 0 V Q1
Q2 100
100 nA
nA
ON CHARACTERISTICS
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA
VGS = VDS, ID = 1 mA Q1
Q2 1.1
1.1 1.9
1.5 2.7
2.2 V
DVGS(th)/
DTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 mA, referenced to 25°C
ID = 10 mA, referenced to 25°CQ1
Q2 −6
−3 mV/°C
rDS(on) Drain to Source On Resistance VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 11 A
VGS = 10 V, ID = 13 A, TJ =125°C
Q1 4
6
5.7
8
11
8.7
mW
VGS = 10 V, ID = 30 A
VGS = 4.5 V, ID = 27 A
VGS = 10 V, ID = 30 A, TJ = 125°C
Q2 1.3
1.5
1.86
1.8
2.2
2.6
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Table 1. ELECTRICAL CHARACTERISTICS TJ = 25°C unless otherwise noted
Symbol UnitsMaxTypMinTypeTest ConditionsParameter
ON CHARACTERISTICS
gFS Forward Transconductance VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 30 A Q1
Q2 62
231 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2 1325
4130 1765
5493 pF
Coss Output Capacitance Q1
Q2 466
915 620
1220 pF
Crss Reverse Transfer Capacitance Q1
Q2 46
124 70
185 pF
RgGate Resistance Q1
Q2 0.2
0.2 0.6
0.8 2
3W
SWITCHING CHARACTERISTICS
td(on) Turn−On Delay Time Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 W
Q2:
VDD = 15 V, ID = 30 A, RGEN = 6 W
Q1
Q2 7.7
11 15
20 ns
trRise Time Q1
Q2 2.2
510
10 ns
td(off) Turn−Off Delay Time Q1
Q2 19
40 34
64 ns
tfFall Time Q1
Q2 1.8
3.9 10
10 ns
QgTotal Gate Charge VGS = 0 V to
10 V Q1
VDD = 15 V, ID = 13 A
Q2
VDD = 15 V, ID = 30 A
Q1
Q2 21
62 29
87 nC
QgTotal Gate Charge VGS = 0 V to
4.5 V Q1
Q2 9.5
29 13
41 nC
Qgs Gate to Source Gate Charge Q1
VDD = 15 V, ID = 13 A
Q2
VDD = 15 V, ID = 30 A
Q1
Q2 3.9
9nC
Qgd Gate to Drain “Miller” Charge Q1
Q2 2.6
7nC
DRAIN−SOURCE DIODE CHARACTERISTICS
VSD Source to Drain Diode Forward Volt-
age VGS = 0 V, IS = 13 A (Note 2)
VGS = 0 V, IS = 2 A (Note 2)
VGS = 0 V, IS = 30 A (Note 2)
VGS = 0 V, IS = 2 A (Note 2)
Q1
Q1
Q2
Q2
0.8
0.7
0.8
0.6
1.2
1.2
1.2
1.2
V
trr Reverse Recovery Time Q1
IF = 13 A, di/dt = 100 A/ms
Q2
IF = 30 A, di/dt = 300 A/ms
Q1
Q2 26
29 42
46 ns
Qrr Reverse Recovery Charge Q1
Q2 10
32 20
50 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. RqJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. RqJC is guaranteed
by design while RqCA is determined by the user’s board design.
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. As an N−ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied with the negative Vgs
rating.
4. EAS of 33 mJ is based on starting TJ = 25°C; N−ch: L = 1.9 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 16 A.
5. EAS of 86 mJ is based on starting TJ = 25°C; N−ch: L = 0.6 mH, IAS = 17 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 31 A.
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(Note 6a) (Note 6b)
(Note 6c) (Note 6d)
G
DF
DS
SF
SS
G
DF
DS
SF
SS
G
DF
DS
SF
SS
G
DF
DS
SF
SS
6. a) 57°C/W when mounted on a 1 in2 pad of 2 oz copper
b) 50°C/W when mounted on a 1 in2 pad of 2 oz copper
c) 125°C/W when mounted on a minimum pad of 2 oz copper
d) 120°C/W when mounted on a minimum pad of 2 oz copper
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TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted
0.0 0.2 0.4 0.6 0.8 1.0
0
10
20
30
40
VGS = 6 V
VGS = 4 V
VGS = 10 V
VGS = 4.5 V
VGS = 3.5 V
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
0 10203040
0
1
2
3
4
VGS = 6 V
VGS = 3.5 V
PULSE DURATION = 80
ms
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON−RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 4 V
VGS = 4.5 V VGS = 10 V
−75 −50 −25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6 ID = 13 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON−RESISTANCE
TJ, JUNCTION TEMPERATURE (
oC)
246810
0
4
8
12
16
20
TJ= 125 oC
ID= 13 A
TJ= 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(on),DRAIN TO
SOURCE ON−RESISTANCE(mW)
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
1.5 2.0 2.5 3.0 3.5 4.0
0
10
20
30
40
TJ = 150 oC
VDS= 5 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
TJ = −55oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SO URCE VOLTAGE (V) 0.00.20.40.60.81.01.2
0.001
0.01
0.1
1
10
40
TJ = − 55oC
TJ = 25 oC
TJ= 150 oC
VGS= 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V )
Figure 1. On Region Characteristics Figure 2. Normalized On−Resistance vs. Drain
Current and Gate Voltage
Figure 3. Normalized On Resistance vs.
Junction Temperature Figure 4. On−Resistance vs. Gate to Source
Voltage
Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward
Voltage vs. Source Current
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TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted
0 5 10 15 20 25
0
2
4
6
8
10
ID= 13 A
VDD = 20 V
VDD = 10 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15 V
0.1 1 10 30
10
100
1000
2000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
0.001 0.01 0.1 1 10 100
1
10
100
TJ= 100 oC
TJ= 25 oC
TJ= 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
25 50 75 100 125 150
0
20
40
60
80
RqJC = 2.9 oC/W
VGS = 4.5 V
Limited by Package
VGS= 10 V
ID,DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
0.01 0.1 1 10 100 200
0.01
0.1
1
10
100
100 ms
DC
100 ms
10 ms
1 ms
1 s
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY r
DS(on)
SINGLE PULSE
TJ= MAX RATED
RqJA = 125oC/W
TA= 25oC
10 s
10−4 10−3 10−2 10−1 110
100 1000
0.1
1
10
100
1000
SINGLE PULSE
RqJA= 125 o C/W
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain to Source
Voltage
Figure 9. Unclamped Inductive Switching
Capability Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum Power
Dissipation
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TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted
10−4 10−3 10−2 10−1 11 0 100 1000
0.001
0.01
0.1
1
2
SINGLE PULSE
RqJA = 125 oC/W
(Note 1c)
DUTY CYCLE−DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZqJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZqJA x RqJA + TA
Figure 13. Junction−to−Ambient Transient Thermal Response Curve
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TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted
0.0 0.2 0.4 0.6 0.8 1.0
0
20
40
60
80
100
120
VGS =2.5V
VGS = 3 V
VGS = 10 V
VGS = 4.5 V
VGS = 3.5 V
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
0 20 40 60 80 100 120
0
1
2
3
4
VGS = 3 V
VGS = 3.5 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON−RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 2.5 V
VGS = 4.5 V VGS = 10 V
−75 −50 −25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6 ID = 30 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON−RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
246810
0
2
4
6
8
TJ= 125 oC
ID= 30 A
TJ= 25oC
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(on),DRAIN TO
SOURCE ON−RESISTANCE(mW)
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
1.0 1.5 2.0 2.5 3.0
0
20
40
60
80
100
120
TJ = 125 oC
VDS = 5 V
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
TJ = −55oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VO LTAGE (V) 0.0 0.2 0.4 0.6 0.8 1.0
0.001
0.01
0.1
1
10
100
TJ = −55oC
TJ = 25 oC
TJ= 125 oC
VGS= 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 14. On Region Characteristics Figure 15. Normalized On−Resistance vs.
Drain Current and Gate Voltage
Figure 16. Normalized On−Resistance vs.
Junction Temperature Figure 17. On−Resistance vs. Gate to Source
Voltage
Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward
Voltage vs. Source Current
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TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted
0 10203040506070
0
2
4
6
8
10 ID= 30 A
VDD = 20 V
VDD = 10 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15 V
0.1 1 10 30
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
0.001 0.01 0.1 1 10 100 1000
1
10
100
TJ= 100 oC
TJ= 2 5 oC
TJ= 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
25 50 75 100 125 150
0
40
80
120
160
Limited by Package
RqJC = 2.2oC/W
VGS = 4.5 V
VGS = 10 V
ID,DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
0.01 0.1 1 10 100 200
0.01
0.1
1
10
100
200
100 ms
DC
100 ms
10 ms
1 ms
1s
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY r
DS(on)
SINGLE PULSE
TJ= MAX RATED
RqJA= 120 oC/W
TA= 25oC
10s
10−4 10−3 10−2 10−1 110
100 1000
0.5
1
10
100
1000
2000 SINGLE PULSE
RqJA= 120 oC/W
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs. Drain to Source
Voltage
Figure 22. Unclamped Inductive Switching
Capability Figure 23. Maximum Continuous Drain
Current vs. Case Temperature
Figure 24. Forward Bias Safe Operating Area Figure 25. Single Pulse Maximum Power
Dissipation
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TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted
10−4 10−3 10−2 10−1 110
100 1000
0.0001
0.001
0.01
0.1
1
2
SINGLE PULSE
qJA = 120oC/W
(Note 1d)
DUTY CYCLE−DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZqJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1t2
NOTES:
DUTY FACTOR: D = t 1/t 2
PEAK TJ = PDM x ZqJA x RqJA + TA
Figure 26. Junction−to−Ambient Transient Thermal Response Curve
R
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TYPICAL CHARACTERISTICS (continued)
SyncFET Schottky Body Diode Characteristics
ON Semiconductor’s SyncFET process embeds a
Schottky diode in parallel with PowerTrench MOSFET.
This diode exhibits similar characteristics to a discrete
external Schottky diode in parallel with a MOSFET.
Figure 27 shows the reverses recovery characteristic of the
FDMS001N025DSD.
Schottky ba r rier diodes exhibit significant leakage at high
temperature and high reverse voltage. This will increase the
power in the device.
Figure 27. FDMS3660S SyncFET Body Diode
Reverse Recovery Characteristic Figure 28. SyncFET Body Diode Reverse Leakage
vs. Drain−Source Voltage
0 100 200 300 400
−5
0
5
10
15
20
25
30
35
didt = 300 A/ms
CURRENT (A)
TIME (ns) 0 5 10 15 20 25
10−6
10−5
10−4
10−3
10−2
TJ= 125 oC
TJ= 100 oC
TJ= 2 5 oC
IDSS, REVERSE LEAKAGE CURRENT (A)
VDS, REVERSE VOLTAGE (V)
Application Information
Switch Node Ringing Suppression
ON Semiconductor’s Power Stage products incorporate a
proprietary design that minimizes the peak overshoot,
ringing voltage on the switch node (PHASE) without the
need of any external snubbing components in a buck
converter. As shown in the Figure 29, the Power Stage
solution rings significantly less than competitor solutions
under the same set of test conditions.
Figure 29. Power Stage Phase Node Rising Edge, High Side Turn On
Power Stage Device Competitors Solution
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Figure 30. Shows the Power Stage in a Buck Converter Topology
Recommended PCB Layout Guidelines
As a PCB designer , it is necessary to address critical issues
in layout to minimize losses and optimize the performance
of the power train. Power Stage is a high power density
solution and all high current flow paths, such as VIN (D1),
PHASE (S1/D2) and GND (S2), should be short and wide
for better and stable current flow, heat radiation and system
performance. A recommended layout procedure is
discussed below to maximize the electrical and thermal
performance of the part.
Figure 31. Recommended PCB Layout
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Following is a guideline, not a requirement which the
PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must
be placed close to the D1 and S2 pins of Power
Stage to help reduce parasitic inductance and high
frequency conduction loss induced by switching
operation. C1 and C2 show the bypass capacitors
placed close to the part between D1 and S2. Input
capacitors should be connected in parallel close to
the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In
addition to being the current path from the Power
Stage package to the output inductor (L), it also
serves as heat sink for the lower FET in the Power
Stage package. The trace should be short and wide
enough to present a low resistance path for the
high current flow between the Power Stage and the
inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that
the PHASE node is a high voltage and high
frequency switching node with high noise
potential. Care should be taken to minimize
coupling to adjacent traces. The reference layout
in Figure 31 shows a good balance between the
thermal and electrical performance of Power
Stage.
3. Output inductor location should be as close as
possible to the Power Stage device for lower
power loss due to copper trace resistance. A
shorter and wider PHASE trace to the inductor
reduces the conduction loss. Preferably the Power
Stage should be directly in line (as shown in
Figure 31) with the inductor for space savings and
compactness.
4. The PowerTrench Technology MOSFETs used in
the Power Stage are effective at minimizing phase
node ringing. It allows the part to operate well
within the breakdown voltage limits. This
eliminates the need to have an external snubber
circuit in most cases. If the designer chooses to use
an RC snubber, it should be placed close to the
part between the PHASE pad and S2 pins to
dampen the high−frequency ringing.
5. The driver IC should be placed close to the Power
Stage part with the shortest possible paths for the
High Side gate and Low Side gates through a wide
trace connection. This eliminates the effect of
parasitic inductance and resistance between the
driver and the MOSFET and turns the devices on
and off as efficiently as possible. At
higher−frequency operation this impedance can
limit the gate current trying to charge the
MOSFET input capacitance. This will result in
slower rise and fall times and additional switching
losses. Power Stage has both the gate pins on the
same side of the package which allows for back
mounting of the driver IC to the board. This
provides a very compact path for the drive signals
and improves efficiency of the part.
6. S2 pins should be connected to the GND plane
with multiple vias for a low impedance grounding.
Poor grounding can create a noise transient offset
voltage level between S2 and driver ground. This
could lead to faulty operation of the gate driver
and MOSFET.
7. Use multiple vias on each copper area to
interconnect top, inner and bottom layers to help
smooth current flow and heat conduction. Vias
should be relatively large, around 8 mils to
10 mils, and of reasonable inductance. Critical
high frequency components such as ceramic
bypass caps should be located close to the part and
on the same side of the PCB. If not feasible, they
should be connected from the backside via a
network of low inductance vias.
PowerTrench is a registered trademark of Semiconductor Components Industries, LLC (SCILLC)
PQFN8 5X6, 1.27P (SAWN TYPE)
CASE 483AJ
ISSUE A
DATE 08 FEB 2021
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
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PQFN8 5X6, 1.27P
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PQFN8 5X6, 1.27P (PUNCHED TYPE)
CASE 483AJ
ISSUE A
DATE 08 FEB 2021
(SCALE: 2X)
c
L2
C
L
L
C
PKG
PKG
D
E
C
D2
e1
k1
TOP VIEW
SIDE VIEW
14
85
1234
876
0.10 C A B
0.05 C
5
SEE
DETAIL B
e
k
E4
(2X)
(2X)
E3 (6X)
D3
z (3X)
D1
E1
b1 (8X)
E2
b (8X)
0.10 C
Ac
SEATING
PLANE
8X
SEE
DETAIL C
(SCALE: 2X)
BOTTOM VIEW
0.10 C
0.10 C
0.08 C
L1 (3X)
e/2
L (5X)
e3
e4
z1
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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98AON13659G
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PAGE 2 OF 2
PQFN8 5X6, 1.27P
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