PCF2123BS/1,512 - NXP SEMICONDUCTORS

1. General description

The PCF2123 is a CMOS1 Real-Time Clock (RTC) and calendar optim ized for low power

applications. Data is transferred serially via a Seri al Peripheral Interface (SPI-bus) with a

maximum data rate of 6.25 Mbit/s. An alarm and timer function is also available providing

the possibility to generate a wake-up signal on an interrupt pin. An offset register allows

fine tuning of the clock.

2. Features and benefits

Real time clock provides year, month, day, weekday, hours, minutes, and seconds

based on a 32.768 kHz quartz crystal

Low backup current while running: typical 100 nA at VDD = 2.0 V and Tamb =25°C

Resolution: seconds to years

Watchdog functionality

Freely programmable timer and alarm with interrupt capability

Clock operating voltage: 1.1 V to 5.5 V

3 line SPI-bus with separate, but combinable data input and output

Serial interface at VDD =1.6Vto5.5V

1 second or 1 minute interrupt output

Integrated oscillator load capacitors for CL=7pF

Internal Power-On Reset (POR)

Open-drain interrupt and clock output pins

Programmable offset register for frequency adjustment

3. Applications

Time keeping application

Battery powered devices

Metering

High duration time rs

Daily alarms

Low standby power applications

PCF2123

SPI Real time clock/calendar

Rev. 5 — 27 April 2011 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.

Product data sheet Rev. 5 — 27 April 2011 2 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

4. Ordering information

[1] Unsawn wafer.

[2] Sawn 6 inch wafer on Film Frame Carrier (FFC) for 6 inch wafer, see Figure 37 on page 53.

[3] Sawn 6 inch wafer with gold bumps on Film Frame Carrier (FFC ) for 8 inch wafer, see Figure 38 on page 53.

5. Marking

Table 1. Ordering information

Type number Package

Name Description Version

PCF2123BS/1 HVQFN16 plastic thermal enhanced very thin quad flat package;

no leads; 16 terminals; body 3 × 3 × 0.85 mm SOT758-1

PCF2123TS/1 TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

PCF2123U/5GA/1 wire bond die 12 bonding pads[1] PCF2123U/10

PCF2123U/10AA/1 wire bond die 12 bonding pads[2] PCF2123U/10

PCF2123U/12AA/1 WLCSP12 wafer level chip size package; 12 bumps[3] PCF2123U/12

PCF2123U/12HA/1 WLCSP12 wafer level chip size package; 12 bumps[3] PCF2123U/12

Table 2. Marking codes

Type number Marking code

PCF2123BS/1 123

PCF2123TS/1 PCF2123

PCF2123U/5GA/1 PC2123-1

PCF2123U/10AA/1 PC2123-1

PCF2123U/12AA/1 PC2123-1

PCF2123U/12HA/1 PC2123-1

Product data sheet Rev. 5 — 27 April 2011 3 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

6. Block diagram

Fig 1. Block diagram of PCF2123

013aaa223

PCF2123

OSCILLATOR

32.768 kHz DIVIDER CLOCK OUT

INTERRUPT

CLKOUT

CLKOE

INT

OFFSET FUNCTION

Offset_register0Dh

MONITOR

POWER ON

RESET

WATCH

DOG

SPI

INTERFACE

OSCI

SCL

SDI

SDO

OSCO

VDD

TEST

VSS

TIMER FUNCTION

Timer_clkout0Eh

Countdown_timer0Fh

CONTROL

Control_100h

Control_201h

TIME

Seconds02h

Minutes03h

Hours04h

Days05h

ALARM FUNCTION

Minute_alarm09h

Hour_alarm0Ah

Day_alarm0Bh

Weekday_alarm0Ch

Weekdays06h

Months07h

Years08h

COSCI

COSCO

Rpd

Product data sheet Rev. 5 — 27 April 2011 4 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

7. Pinning information

7.1 Pinning

For mechanical details, see Figure 30 on page 45. Top view. For mechanical details, see Figure 31 on

page 46.

Fig 2. Pin configuration for HVQFN16 (PCF2123BS/1) Fig 3. Pin configu ration for TSSOP14 (PCF2123TS/1)

001aai550

PCF2123BS

Transparent top view

CE SDI

INT SCL

TEST CLKOE

OSCO CLKOUT

VSS

n.c.

SDO

OSCI

n.c.

VDD

4 9

310

211

112

terminal 1

index area

PCF2123TS

OSCI V

OSCO CLKOUT

n.c. CLKOE

TEST n.c.

INT SCL

CE SDI

SDO

001aai551

Viewed from active side. For mechanical details, see Figure 33 on page 48 and Figure 34 on

page 49.

Fig 4. Pin configuration for PCF2123Ux (bare die)

001aai54

OSCI

VDD

PCF2123U

8OSCO

9TEST

10INT

11CE

12VSS

5 CLKOUT

4 CLKOE

3 SCL

2 SDI

1 SDO

Product data sheet Rev. 5 — 27 April 2011 5 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

7.2 Pin description

[1] The die paddle (exposed pad) is wired to VSS and should be electrically isolated.

[2] The substrate (rear side of the die) is wired to VSS and should be electrically isolated.

Table 3. Pin description

Symbol Pin Description

HVQFN16

(PCF2123BS/1) TSSOP14

(PCF2123TS/1) PCF2123Ux

(bare die)

OSCI 16 1 7 oscillator input; high-impedance node ; minimize wire length

between quartz and package

OSCO 1 2 8 oscillator output; high-impedance node; minimize wire length

between quartz and package

n.c. 6, 7, 14, 15 3, 11 - do not co nnect and do not use as feed through; connect to

VDD if floating pins are not allowed

TEST 2 4 9 test pin; not user accessible; connect to VSS or leave floating

(internally pulled down)

INT 3 5 10 interrupt output (open-drain; active LOW)

CE 4 6 11 chip enable input (active HIGH) with internal pull down

VSS 5[1] 712

[2] ground

SDO 8 8 1 serial data output, push-pull; high-impedance when not

driving; can be connected to SDI for single wire data line

SDI 9 9 2 serial data input; may float when CE is inactive

SCL 10 10 3 serial clock input; may float when CE is inactive

CLKOE 11 12 4 CLKOUT enable or disable pin; enabl e is active HIGH

CLKOUT 12 13 5 clock output (open-drain)

VDD 13 14 6 supply voltage; positive or negative steps in VDD may affect

oscillator performance; recommend 100 nF decoupling close

to the device (see Figure 29)

Product data sheet Rev. 5 — 27 April 2011 6 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8. Functional description

The PCF2123 contains 16 8-bit registers with an auto-incrementing address counter, an

on-chip 32.768 kHz oscillator with two integrated load capacitors, a frequency divider

which provides the source clock for the Real Time Clock (RTC), a programmable clock

output, and a 6.25 Mbit/s SPI-bus. An offset register allows fine tuning of the clock.

All 16 registers are designed as addressable 8-bit parallel registers although not all bits

are implemented.

•The first two registers (memory address 00h and 01h) are used as control registers.

•The memory addresses 02h through 08h are used as counters for the clock function

(seconds up to years). The registers Seconds, Minutes, Hours, Days, Weekdays,

Months, and Year s are all coded in Binary Coded Decimal (BCD) format. When one of

the RT C register s is written or read the conten t s of a ll counters ar e frozen. Th erefore,

faulty writing or reading of the clock and calendar during a carry condition is

prevented.

•Addresses 09h through 0Ch define the alarm condition.

•Address 0Dh defines the offset calibration.

•Address 0Eh defines the clock out and timer mode.

•Address registers 0Eh and 0Fh are used for the countdown timer function. The

countdown timer has four selectable source clocks allowing for countdown periods in

the range from 244 μs up to four hours. There are also two pre-defined timers which

can be used to generate an interrupt once per second or once per minute. These are

defined in register Control_2 (01h).

8.1 Low power operation

Minimum power operation will be achieved by reducing the number and frequency of

switching signals inside the IC, i.e., low frequency timer clocks and a low frequency

CLKOUT will result in lower operating power. A second prime consideration is the series

resistance Rs of the quartz used.

8.1.1 Power consumption with respect to quartz series resistance

The series resistance acts as a loss element. Low Rs will reduce current consumption

further.

Product data sheet Rev. 5 — 27 April 2011 7 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.1.2 Power consumptions with respect to timer mode

Four source clocks are possible for the timer. The 4.096 kHz source clock will add the

greatest part to the power consumption. The selection of 64 Hz, 1 Hz, or 1⁄60 Hz will be

almost indistinguishable and add very little.

Configuration: CLKOUT disabled, VDD = 3 V, timer clock set to 1⁄60 Hz.

(1) IDD (nA) minimum power mode.

(2) Maximum value for RS is 100 kΩ.

Fig 5. IDD with respect to quartz RS

Rs(2) (kΩ)

0 1008040 6020

001aai558

130

170

210

250

IDD(1)

(nA)

Configuration: CLKOUT disabled, quartz RS=15kΩ.

(1) IDD (nA) minimum power mode.

(2) Timer clock = 4 kHz.

(3) Timer clock = 64 Hz, 1 Hz, 1⁄60 Hz.

Fig 6. IDD with respect to timer clock selection

VDD (V)

0 642

001aai559

200

100

300

400

IDD(1)

(nA)

(2)

(3)

Product data sheet Rev. 5 — 27 April 2011 8 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.2 Register overview

16 registers are available. The time registers are encoded in the Binary Coded Decimal

(BCD) format to simplify application use. Other registers are eith e r bit- wise or standard

binary.

[1] Except in the case of software reset, see Section 8.3.1.1.

Table 4. Registers overview

Bit positions labelled as - are not implemented and will return a 0 when read. The bit position labelled as -- is not implemented

and will return a 0 or 1 when read. Bit positions labelled with N should always be written with logic 0[1].

Address Register name Bit

7 6 5 4 3 2 1 0

Control and status registers

00h Control_1 EXT_TEST N STOP SR N 12_24 CIE N

01h Control_2 MI SI MSF TI_TP AF TF AIE TIE

Time and date registers

02h Seconds OS SECONDS (0 to 59)

03h Minutes -- MINUTES (0 to 59)

04h Hours - - AMPM HOURS (1 to 12) in 12 h mode

HOURS (0 to 23) in 24 h mode

05h Days - - DAYS (1 to 31)

06h Weekdays - - - - - WEEKDAYS (0 to 6)

07h Months - - - MONTHS (1 to 12)

08h Years YEARS (0 to 99)

Alarm registers

09h Minute_alarm AE_M MINUTE_ALARM (0 to 59)

0Ah Hour_ala rm AE_H - AMPM HOUR_ALARM (1 to 12) in 12 h mode

HOUR_ALARM (0 to 23) in 24 h mode

0Bh Day_alarm AE_D - DAY_ALARM (1 to 31)

0Ch Weekday_alarm AE_W - - - - WEEKDAY_ALARM (0 to 6)

Offset register

0Dh Offset_register MODE OFFSET[6:0]

Tim er registers

0Eh Timer_clkout - COF[2:0] TE - CTD[1:0]

0Fh Countdown_timer COUNTDOWN_TIMER[7:0]

Product data sheet Rev. 5 — 27 April 2011 9 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.3 Control registers

8.3.1 Register Control_1

[1] Default value.

[2] For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.3.1.1).

8.3.1.1 Reset

A reset is automatically generated at power-on. A reset can also be initiated with the

software reset command. It is generally recommended to make a software reset after

power-on.

A software re set can be initia ted by setting the bits 6, 4 and 3 in register Con trol_ 1 logic 1

and all other bit s logic 0 by sending the bit sequence 01011000 (58h), see Figure 7. If this

bit sequence is not correct, the software reset instruction will be ignored to protect the

device from acciden tly bein g re set. Wh en sen din g th e software instr uc tio n, the ot he r bits

are not written.

Table 5. Control_1 - control and status register 1 (address 00h) bit desc ription

Bit Symbol Value Description Reference

7 EXT_TEST 0[1] normal mode Section 8.10

1 external clock test mode

6 N - unused -

5STOP 0

[1] the RT C sourc e clock runs Section 8.11

1 the RTC clock is stopped;

RTC divider chain flip-flops are

asynchronously set to logic 0;

CLKOUT at 32.768 kHz, 16.384 kHz or

8.192 kHz is still available

4SR 0

[1] no software reset Section 8.3.1.1

1 initiate software reset[2];

this register will always return a 0 when

read

3 N - unused -

2 12_24 0[1] 24 hour mode is selected -

1 12 hour mode is selected

1CIE 0

[1] no correction interrupt generated Section 8.9

1 interrupt pulses will be generated at every

correction cycle

0 N - unused -

Product data sheet Rev. 5 — 27 April 2011 10 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

After reset, the following mode is entered:

•32.768 kHz on pin CLKOUT ac tive

•24 hour mode is selected

•Offset register is set to 0

•No alarms set

•Time r disabled

•No interrupts ena bled

(1) When CE is inactive, the interface is reset.

Fig 7. Software reset command

Table 6. Register reset values

Bits labeled as - are not implemented. Bits labeled as X are undefined at power-on and unchanged

by subsequent resets.

Address Register name Bit

76543210

00hControl_1 00000000

01hControl_2 00000000

02h Seconds 1XXXXXXX

03h Minutes - XXXXXXX

04h Hours - - XXXXXX

05h Days - - XXXXXX

06hWeekdays -----XXX

07h Months - - - XXXXX

08h Years XXXXXXXX

09h Minute_alarm 1XXXXXXX

0Ah Hour_alarm 1- XXXXXX

0Bh Day_alarm 1- XXXXXX

0ChWeekday_alarm1----XXX

0DhOffset_register00000000

0EhTimer_clkout - 0000- 11

0Fh Countdown_timerXXXXXXXX

001aai5

addr 00

HEX

software reset 58

HEX

R/W

internal

reset signal

SCL

(1)

Product data sheet Rev. 5 — 27 April 2011 11 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.3.2 Register Control_2

[1] Default value.

Table 7. Control_2 - control and status register 2 (address 01h) bits description

Bit Symbol Value Description Reference

7MI 0

[1] minute interrupt is disabled Section 8.6.3

1 minute interrupt is enabled

6SI 0

[1] second interrupt is disabled

1 second interrupt is enabled

5MSF 0

[1] no minute or second interrupt generated

1 flag set when minute or second interrupt

generated;

flag must be cleared to clear interrupt

when TI_IP = 0

4TI_TP 0

[1] interrupt pin follows timer flags Section 8.7.2

1 interrupt pin generates a pulse

3AF 0

[1] no alarm interrupt generated Section 8.5.5

1 flag set when alarm trigge red;

flag must be cleared to clear interrupt

2TF 0

[1] no countdown timer interrupt generated Section 8.6.4

1 flag set when countdown timer interrupt

generated;

flag must be cleared to clear interrupt

when TI_IP = 0

1AIE 0

[1] no interrupt generated from the alarm flag Section 8.7.3

1 interrupt generated when alarm flag set

0TIE 0

[1] no interrupt generated from the countdown

timer Section 8.7.2

1 interrupt generated by the countdown timer

Product data sheet Rev. 5 — 27 April 2011 12 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.4 T ime and date function

The majority of th e registers are coded in the Binary Coded Decimal (BCD) format. BCD is

used to simplify applica tio n us e. An exam p le is sho wn for th e sec on d s in Table 9.

8.4.1 Register Seconds

[1] Default value.

8.4.1.1 OS flag

The PCF2123 includes a fla g (OS in register Second s, see Table 8) which is set whenever

the oscillator is stopped (see Figure 8 and Figure 9). The flag will remain set until cleared

by software. If the flag cannot be cleared, then the PCF2123 oscillator is not running. This

method can be used to monitor the oscillator and to determine if the supply voltage has

reduced to the point where oscillation fails.

Table 8. Seconds - seconds register (address 02h) bit description

Bit Symbol Value Place value Description

7 OS 0 - clock integrity is guaranteed

1[1] - clock integrity is not guaranteed;

oscillator has stopped or has

been interrupted

6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD

format, see Table 9

3 to 0 0 to 9 unit place

Table 9. Seconds coded in BCD fo rmat

Seconds val ue

(decimal) Upper-digit (te n’s place) Digit (unit place)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 00000000

01 00000001

02 00000010

: ::::::::

09 00001001

10 00010000

: ::::::::

58 01011000

59 01011001

Fig 8. OS set by failing VDD

001aai56

VDD

VOSC(MIN)

battery operation

main supply

Product data sheet Rev. 5 — 27 April 2011 13 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI

or OSCO. The oscillator is also considered to be stopped during the time between

power-on and stable crystal resonance. This time may be in the range of 200 ms to 2 s

depending on crystal type, temperature and supply voltage. At power-on the OS flag is

always set.

8.4.2 Register Minutes

8.4.3 Register Hours

[1] Hour mode is set by the 12_24 bit in register Control_1.

Fig 9. OS flag

001aai55

OS = 1 and flag can not be cleared OS = 1 and flag can be cleared

OS flag cleared

by software

OS flag set when

oscillation stops

oscillation now stable t

oscillation

OS flag

Table 10. Minutes - minutes register (addr ess 03h) bit description

Bit Symbol Value Place value Description

7 - - - unused

6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD

format

3 to 0 0 to 9 unit place

Table 11. Hours - hours register (address 04h) bit description

Bit Symbol Value Place value Description

7 to 6 - - - unused

12 hour mode[1]

5 AMPM 0 - indicates AM

1 - indicates PM

4 HOURS 0 to 1 ten’s place actual hours in 12 hour mode

coded in BCD format

3to0 0to9 unit place

24 hour mode[1]

5 to 4 HOURS 0 to 2 ten’s place actual hours in 24 hour mode

coded in BCD format

3to0 0to9 unit place

Product data sheet Rev. 5 — 27 April 2011 14 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.4.4 Register Days

[1] The PCF2123 compensates for leap years by adding a 29th day to February if the year counter contains a

value which is exactly divisible by 4, including the year 00.

8.4.5 Register Weekdays

[1] Definition may be re-assigned by the user.

8.4.6 Register Months

Table 12. Days - days re gister (address 05h) bit description

Bit Symbol Value Place value Description

7 to 6 - - - unused

5to4 DAYS

[1] 0 t o 3 ten’s place actual day coded in BCD format

3to0 0to9 unit place

Table 13. Weekdays - weekdays register (address 06h) bit description

Bit Symbol Value Description

7 to 3 - - u nused

2to0 WEEKDAYS 0to6 actual weekday values, seeTable 14

Table 14. Weekday assignments

Day[1] Bit

210

Sunday 0 0 0

Monday 0 0 1

Tuesday 0 1 0

Wednesday 0 1 1

Thursday 1 0 0

Friday 1 0 1

Saturday110

Table 15. Months - months register (address 07h) bit description

Bit Symbol Value Place value Description

7 to 5 - - - unused

4 MONTHS 0 to 1 ten’s place actual month coded in BCD

format, see Table 16

3 to 0 0 to 9 unit place

Product data sheet Rev. 5 — 27 April 2011 15 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.4.7 Register Years

8.4.8 Setting and reading the time

Figure 10 shows the data flow and data dependencies starting from the 1 Hz clock tick.

Table 16. Month assignments in BCD format

Month Upper-digit

(ten’s place) Digit (unit place)

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

January 0 0 0 0 1

February 0 0 0 1 0

March 0 0 0 1 1

April00100

May00101

June00110

July00111

August01000

September 0 1 0 0 1

October10000

November10001

December10010

Table 17. Years - years regi ster (08h ) bit description

Bit Symbol Value Place value Description

7 to 4 YEARS 0 to 9 ten’s place actual year coded in BCD format

3to0 0to9 unit place

Fig 10. Data flow of the time function

001aaf90

1 Hz tick

12_24 hour mode

WEEKDAY

SECONDS

MINUTES

HOURS

DAYS

LEAP YEAR

CALCULATION

MONTHS

YEARS

Product data sheet Rev. 5 — 27 April 2011 16 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

During read/write operations, the time counting circuits (memory locations 02h through

08h) are blocked.

This prevents

•Faulty reading of the clock and calenda r dur ing a carr y con d itio n

•Incrementing the time registers during the read cycle

After this read/write access is completed, the time circuit is released again and any

pending request to increment th e time counters that occurred during the read/write access

is serviced. A maximum of 1 request can be stored; therefore, all accesses must be

completed withi n 1 se con d (s ee Figure 11).

As a consequence of this method, it is very important to make a read or write access in

one go, that is, setting or reading seconds th roug h to ye ars sho uld be made in on e single

access. Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a

second access the date is set, it is possible that the time may increment between the two

accesses. A similar pr ob lem exists when reading. A roll over may occu r be twe e n read s

thus giving the minutes from one moment and the hours from the next. Therefore it is

advised to read all time and da te registers in one access.

Fig 11. Access time for read/write operations

t < 1 s

013aaa22

COMMANDdata bus

chip enable

DATA DATADATA

Product data sheet Rev. 5 — 27 April 2011 17 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.5 Alarm function

When one or more of these registers are loaded with a valid minute, hour, day, or

weekday and its corr esponding alarm enable bit (AE_x) is logic 0, then that information

will be compared with the current minute, hour, day, and weekday.

8.5.1 Register Minute_alarm

[1] Default value.

8.5.2 Register Hour_alarm

[1] Default value.

[2] Hour mode is set by the 12_24 bit in register Control_1.

8.5.3 Register Day_alarm

[1] Default value.

Table 18. Minute_alarm - minute alarm register (address 09h) bi t description

Bit Symbol Value Place value Description

7 AE_M 0 - minute alarm is enabled

1[1] - minute alarm is disabled

6 to 4 MINUTE_ALARM 0 to 5 ten’s place minute alarm information coded in

BCD format

3 to 0 0 to 9 unit place

Table 19. Hour_alarm - hour alarm regist er (address 0Ah) bit description

Bit Symbol Value Place value Description

7 AE_H 0 - hour alarm is enabled

1[1] - hour alarm is disabled

6 - - - unused

12 hour mode[2]

5 AMPM 0 - indicates AM

1 - indicates PM

4 HOUR_ALARM 0 to 1 ten’s place hour alarm informati on coded in

BCD format when in 12 hour

mode

3to0 0to9 unit place

24 hour mode[2]

5 to 4 HOUR_ALARM 0 to 2 ten’s place hour alarm information coded in

BCD format when in 24 hour

mode

3to0 0to9 unit place

Table 20. Day_alarm - day ala rm register (address 0Bh) bit description

Bit Symbol Value Place value Description

7 AE_D 0 - day alarm is enabled

1[1] - day alarm is disabled

6 - - - unused

5 to 4 DAY_ALARM 0 to 3 ten’s place day alarm information coded in

BCD format

3 to 0 0 to 9 unit place

Product data sheet Rev. 5 — 27 April 2011 18 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.5.4 Register Weekday_alarm

[1] Default value.

8.5.5 Alarm flag

By clearing the MSB, AE_x (Alarm Enable), of one or more of the alarm registers the

corresponding alarm condition(s) are active. When an alarm occurs, AF (register

Control_2, see Table 7) is set logic 1. The asserted AF can be used to generate an

interrupt (INT). The AF is cleared using the interface.

The registers at addresses 09 h through 0Ch contain alarm information. When one or

more of these registers is loaded with minute, hour, day, or weekday, and its

corresponding Alarm Enable bit (AE_x) is logic 0, then that information is compared with

the current min ut e, hour, da y, and weekda y. When all enabled co mpariso ns first ma tch ,

the Alarm Flag (AF) is set logic 1.

Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description

Bit Symbol Value Description

7 AE_W 0 weekday alarm is enabled

1[1] weekday alarm is disa bled

6 to 3 - - u nused

2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information coded in BCD

format

(1) Only when all enabled alarm settings are matching.

It’s only on increment to a matched case that the alarm flag is set, see Section 8.5.5.

Fig 12. Alarm function bloc k dia g ra m

013aaa088

WEEKDAY ALARM

AE_W

WEEKDAY TIME

DAY ALARM

AE_D

DAY TIME

HOUR ALARM

AE_H

HOUR TIME

MINUTE ALARM

AE_M

MINUTE TIME

check now signal

set alarm flag AF (1)

AE_M = 1

example

Product data sheet Rev. 5 — 27 April 2011 19 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

The generation of interrupts from the alarm function is controlled via bit AIE (register

Control_2, see Table 7). If bit AIE is enabled, the INT pin fo llows the condition of bit AF. AF

will remain set until cleared by the interface. Once AF has been cleared, it will only be set

again when the time increments to match the alarm condition once more. Alarm registers

which have their AE_x bit logic 1 are ignored.

Generation of interrupts from the alarm function is described in Section 8.7.3.

Figure 13, Table 22, and Table 23 show an example for clearing bit AF, but leaving bit

MSF and bit TF unaf fe cted. The fl ags are cle ared by a write command, there fore bit s 7, 6,

4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has

no influence on the functional behavior.

To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed

during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by

writing logic 1. Writing logic 1 will result in the flag value remaining unchanged.

Table 23 shows what instruction must be sent to clear bit AF. In this example, bit MSF and

bit TF are unaffected.

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 13. Alarm flag timing

Table 22. Flag location in register Control_2

76543210

Control_2--MSF-AFTF--

Table 23. Example to clear only AF (bit 3) in register Control_2

76543210

Control_2 - - 1 - 0 1 - -

001aaf9

44 45

45minute alarm

minutes counter

INT when AIE = 1

Product data sheet Rev. 5 — 27 April 2011 20 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.6 T imer functions

The countd own timer h as four sele ctable source clocks allowing for count down pe rio ds in

the range from 244 μs to 4 h 15 min. There are also two pre-defined timers which can be

used to generate an interrupt once per second or once per minute. For periods greater

than 4 hours, the alarm function can be us ed. Registers 01h, 0Eh and 0Fh are used to

control the timer function and output.

8.6.1 Register Timer_clkout

[1] Values of COF[2:0] see Table 35.

[2] Default value.

8.6.2 Register Countdown_timer

8.6.3 Minute and second interrupt

The minute and second interrupts (bits MI and SI) are pre-defined timers for generating

periodic interrupt s. Th e timers can be enab led indep endently fr om one anoth er. However,

a minute interrupt enabled on top of a second interrupt will not be distinguishable since it

will occur at the same time; see Figure 14.

Table 24. Timer_clkout - timer contro l register (address 0Eh) bit descrip tion

Bit Symbol Value Description Reference

7- - unused -

6 to 4 COF[2:0] [1] CLKOUT control Section 8.8

3 TE 0 countdown timer is disabled Section 8.6.4

1 countdown timer is enabled

2 - - unused

1 to 0 CTD[1:0] 00 4.096 kHz countdown timer source clock

01 64 Hz countd own timer source clock

10 1 Hz countdown timer source cloc k

11[2] 1⁄60 Hz countdown timer source clock

Table 25. Countdown_timer - countdown timer register (address 0Ah) bit description

Bit Symbol Value Description Reference

7 to 0 COUNTDOWN_TIMER[7:0] 0h to FFh countdown period in seconds:

where n is the countdown value

Section 8.6.4

CountdownPeriod n

SourceClockFrequency

---------------------------------------------------------------

Product data sheet Rev. 5 — 27 April 2011 21 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

The minute and second flag (bit MSF) is set logic 1 when either the seconds or the

minutes counter increments according to the currently enabled interrupt. The flag can be

read and cleared by the interface. The status of bit MSF does not affect the INT pulse

generation. If th e MSF flag is not cleared prior to the next coming interrupt period, an INT

pulse will still be generated.

The purpose of the flag is to allow the controlling system to interrogate the PCF2123 and

identify the source of the interrupt, i.e., minute or second, countdown timer or alarm.

The duration of both of these timers will be affected by the register Offset_regis ter (see

Section 8.9). Only when the Offset_register has the value 00h the periods will be

consistent.

In this example, TI_TP is set to logic 1 resulting in 1⁄64 Hz wide interrupt pulse and the MSF flag is

not cleared after an interrupt.

Fig 14. INT example for MI and SI

Table 26. Effect of bits MI and SI on INT generation

Minute interrupt (bit MI) Second interrupt (bit SI) Result

0 0 no interrupt generated

1 0 an interrupt once per minute

0 1 an interrupt once per second

1 1 an interrupt once per second

Table 27. Effect of MI and SI on MSF

Minute interrupt (bit MI) Second interrupt (bit SI) Result

0 0 MSF never set

1 0 MSF set when minutes counter

increments

0 1 MSF set when seconds counter

increments

1 1 MSF set when seconds counter

increments

001aaf9

58 59 59 00

seconds counter

minutes counter

INT when SI enabled

MSF when SI enabled

INT when only MI enabled

MSF when only MI enabled

00 01

Product data sheet Rev. 5 — 27 April 2011 22 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.6.4 Countdown timer function

The 8-bit countdown timer at address 0Fh is controlled by the register Timer_clkout at

address 0Eh. The register Timer_clkout selects one of 4 source clock frequencies for the

timer (4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer.

[1] When not in use, CTD must be set to 1⁄60 Hz for power saving.

[2] Time periods can be affected by correction pulses.

Remark: Note that all timings which are generated from the 32.768 kHz oscillator are

based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency

will result in deviation in timings. This is not applicable to interface timing.

The timer counts down from a software-loaded 8-bit binary value, n. Loading the counter

with 0 stops the timer. Values from 1 to 255 are valid. When the counte r reaches 1, the

countdown timer flag (bit TF) will be set and the counter automatically re-loads and starts

the next timer period. Reading the timer will return the current value of the countdown

counter (see Figure 15).

If a new value of n is written before the end of the current timer period, then this value will

take immediate effect. NXP does not recommend changing n without first disabling the

counter (by setting bit TE = 0). The update of n is asynchronous to the timer clock,

Table 28. Bits CTD0 and CTD1 for timer frequency selection and countdown timer

durations

CTD[1:0] Timer source clock

frequency[1] Delay

Minimum timer duration

n= 1 Maximum timer duration

n=255

00 4.096 kHz 244 μs 62.256 ms

01 64 Hz 15.625 ms 3.984 s

10 1 Hz[2] 1 s 255 s

11 1⁄60 Hz[2] 60 s 4 h 15 min

In this example it is assumed that the timer flag is cleared before the next countdown period

expires and that the pin INT is set to pulsed mode.

Fig 15. General coun tdown timer behavior

001aaf90

duration of first timer period after

enable may range from n − 1 to n + 1

03xx 02 01 03 02 01 03 02 01 03

03xxcountdown value, n

timer source clock

countdown counter

INT

Product data sheet Rev. 5 — 27 April 2011 23 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

therefore changing it witho ut setting bi t TE = 0 may result in a corrupted value loaded into

the countdown counter which results in an undetermined countdown period for the first

period. The countdown value n will, however, be correctly stored and correctly loaded on

subsequent timer periods.

When the countdown timer flag is set, an interrupt signal on INT will be generated

provided that this mode is enabled. See Section 8.7.2 for details on how the interrupt can

be controlled.

When starting the timer for the first time, the first period will have an uncert ainty which is a

result of the enable instruction being generated from the interface clock which is

asynchronous from the timer source clock. Subsequent timer periods will have no such

delay. The amount of delay for the first timer period will depend on the chosen source

clock, see Table 29.

At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF

may only be cleared by software. The asserted bit TF can be used to generate an

interrupt (INT). The interrupt may be generated as a pulsed signal every countdown

period or as a permanently active signal whic h follows the condition of bit TF. Bit TI_TP is

used to control this mode selection and the inte rrupt output may be disabled with bit TIE,

see Table 7.

When reading the timer, the current countdown value is returned and not the initial

value n. Since it is not possible to freeze the count down timer counte r dur ing read back, it

is recommended to read the register twice and check for consistent results.

Timer source clock frequency selection of 1 Hz and 1⁄60 Hz will be affected by the

Offset_register. The duration of a program period will vary according to when the offset is

initiated. For example, if a 100 s timer is set us ing the 1 Hz clock as source, then some

100 s periods will contain correction pulses and therefor be longer or shorter depending

on the setting of the Offset_register. See Section 8.9 to understand the operation of the

Offset_register.

8.6.5 Timer flags

When a minute or seco nd interrupt occu rs, bit MSF is set logic 1. Similarly, at the end of a

timer countdown or alarm event, bit TF or AF are set logic 1. These bits maintain their

value until overwritten by software. If both count down timer and minute or second

interrupt s are req uired in th e applicatio n, the source of the interrupt can be dete rmined by

reading these bits. To prevent one flag being overwritten while clearing another a logical

AND is performed during a write access. A flag is cleared by writing logic 0 whilst a flag is

not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining

unchanged.

Table 29. First period delay for timer counter value n

Timer source clock Minimum timer period Maximum timer period

4.096 kHz n n + 1

64 Hz n n + 1

1 Hz (n − 1) + 1⁄64 Hz n + 1⁄64 Hz

1⁄60 Hz (n − 1) + 1⁄64 Hz n + 1⁄64 Hz

Product data sheet Rev. 5 — 27 April 2011 24 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

Three examples are given for clearin g the fl ags. Clearing the flags is made by a write

command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values.

Repeatedly re-writing thes e bits has no influence on the functional behavior.

Table 31, Table 32, and Table 33 show what instruction mu st be sent to clea r th e

appropriate flag.

Clearing the alarm flag (bit AF) operates in exactly the same way, see Section 8.5.5.

Table 30. Flag location in register Control_2

76543210

Control_2 - - MSF - AF TF - -

Table 31. Example to clear only TF (bit 2) in register Control_2

76543210

Control_2 - - 1 - 1 0 - -

Table 32. Example to clear only MSF (b it 5) in register Control_2

76543210

Control_2 - - 0 - 1 1 - -

Table 33. Example to clear both TF and MSF (bit 2 and bit 5) in register Control_2

76543210

Control_2 - - 0 - 1 0 - -

Product data sheet Rev. 5 — 27 April 2011 25 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.7 Interrupt output

An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits

of register Control_2. Interrupts may be sourced from four places: second and minute

timer, countdown timer, alarm function or offset function.

With bit TI_TP, the timer generated interrupt s can be configured to eithe r generate a pulse

or to follow the status of the interrupt flags (bits TF and MSF). Correction interrupt pulses

are always 1⁄128 second long. Alarm interrupts always follow the condition of AF.

Remark: Note that the interrupts from the four sources are wired-OR, meaning they will

mask one another (see Figure 16).

When bits SI, MI, TIE, AIE, and CIE are all disabled, pin INT will remain high-impedance.

Fig 16. Interrupt scheme

001aai55

SECONDS COUNTER

MSF: MINUTE

SECOND FLAG

CLEAR

SET

PULSE

GENERATOR 1

CLEAR

TRIGGER

SI MI

MINUTES COUNTER

COUNTDOWN COUNTER

from interface:

clear MSF

to interface:

read MSF

AF: ALARM

FLAG

CLEAR

SET

to interface:

read AF

TF: TIMER

CLEAR

SET

PULSE

GENERATOR 2

CLEAR

TRIGGER

TIE

INT

from interface:

clear TF

from interface:

clear AF

set alarm

flag, AF

offset circuit: add/substract

1/64 Hz pulse

to interface:

read TF

TI_TP

AIE

E.G.AIE

PULSE

GENERATOR 3

CLEAR

TRIGGER

CIE

from interface:

set CIE

Product data sheet Rev. 5 — 27 April 2011 26 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.7.1 Minute and second interrupts

The pulse generator for the minute and second interrupt operates from an internal 64 Hz

clock and conseq ue n tly ge ne r ate s a pu lse of 1⁄64 second in duration.

If the MSF flag is cleared before the end of the INT pulse, then the INT pulse is shortened .

This allows the source of a system interrupt to be cleared immediately it is serviced, i.e.,

the system does not have to wait for the completion of the pulse before continuing; see

Figure 17. Instructions for clearing MSF are given in Section 8.6.5.

The timing shown for clearing bit MSF in Figure 17 is also valid for the non-pulsed

interrupt mode i.e. when bit TI_TP = 0, INT may be shortened b y setting both MI and SI or

MSF to logic 0.

8.7.2 Countdown timer interrupts

The generation of interrupts from the countdown timer is controlled via bit TIE.

The pulse generator for the countdown timer interrupt also u ses an inter nal clock, but thi s

time it is dependent on the selected source clock for the countdown timer and on the

countdown value n. As a consequence, the width of the interrupt pulse varies (see

Table 34).

[1] n = loaded countdown value. Timer stopped when n = 0.

If the TF flag is cleared before the end of the INT pulse, then the INT pulse is shortened.

This allows the source of a system interrupt to be cleared immediately it is serviced, i.e.,

the system does not have to wait for the completion of the pulse before continuing (see

Figure 18). Instructions for clearing MSF can be found in Section 8.6.5.

(1) Indicates normal duration of INT pulse (bit TI_TP = 1)

Fig 17. Example of shortening the INT pulse by clearing the MSF flag

001aaf9

58seconds counter

MSF

INT

SCL

instruction

CLEAR INSTRUCTION

8th clock

(1)

Table 34. INT operat ion (bit TI_TP = 1)

Source clock (Hz) INT period (s)

n = 1[1] n > 1

4096 1⁄8192 1⁄4096

64 1⁄128 1⁄64

11⁄64 1⁄64

1⁄60 1⁄64 1⁄64

Product data sheet Rev. 5 — 27 April 2011 27 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

The timing shown for clearing bit TF in Figure 18 is also valid for the non-pulsed interrupt

mode, i.e., when bit TI_TP = 0; INT may be shortened by setting bit TIE to logic 0.

8.7.3 Alarm interrupts

The generation of interru pts from th e alarm function is controlled via bit AIE (see Table 7).

If bit AIE is enabled, the INT pin follows the condition of bit AF. Clearing bit AF will

immediately clear INT. No pulse generation is possible for alarm interrupts (see

Figure 19).

8.7.3.1 Correctio n pulse interrupts

Interrupt pulses generated by correction events can be shortened by writing logic 1 to bit

CIE in register Control_1.

(1) Indicates normal duration of INT pulse (bit TI_TP = 1).

Fig 18. Example of shortening the INT pulse by clearing the TF flag

001aaf9

01countdown counter

CDTF

INT

SCL

instruction

CLEAR INSTRUCTION

8th clock

(1)

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 19. AF timing

001aaf9

minute counter

minute alarm

INT

SCL

instruction

CLEAR INSTRUCTION

8th clock

Product data sheet Rev. 5 — 27 April 2011 28 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.8 Clock output

A programmable square wave is available at pin CLKOUT. Operation is controlled by the

COF[2:0] bits in the register Timer_clkout. Frequencies of 32.768 kHz (default) down to

1 Hz can be generated for u se as a system clock, microcontroller clock, input to a charge

pump, or for calibration of the oscillator.

Pin CLKOUT is an open-d rain output an d enabled a t power-on. When disabled the output

is high-impedance.

The duty cycle of the selected clock is not controlled. However, due to the nature of the

clock generation, all will be 50 : 50 except the 32.768 kHz frequencies.

The STOP bit function can also affect the CLKOUT signal, depending on the selected

frequency. When the STOP bit is set logic 1, the CLKOUT pin will generate a continuous

LOW for those frequencies tha t can be sto pped. For more det ails of the ST OP bit fu nction

see Section 8.11.

[1] Duty cycle definition: % HIGH-level time : % LOW-level time.

[2] 1 Hz clock pulses will be affected by offset correction pulses.

8.8.1 CLKOE pin

The CLKOE pin can be used to b lock the CLKOUT fun c tion a nd fo rce the CL KOUT pi n to

a high-impedance state. The effect is the same as setting COF[2:0] = 111.

Table 35. CLKOUT frequency sele ction

Bits COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1] Effect of STOP bit

000 32768 60 : 40 to 40 : 60 no effect

001 16384 50 : 5 0 no effect

010 8192 50 : 50 no effect

011 4096 50 : 50 CLKOUT = LOW

100 2048 50 : 50 CLKOUT = LOW

101 1024 50 : 50 CLKOUT = LOW

110 1[2] 50 : 50 CLKOUT = LOW

111 CLKOUT = high-Z - -

Product data sheet Rev. 5 — 27 April 2011 29 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.9 Offset register

The PCF2123 incorpora tes an offset register (address 0Dh) which can be used to

implement several functions, such as:

•Ageing adjustme nt

•Temperature compensation

•Accuracy tuning

The offset is made once every two hours in the normal mode, or once every hour in the

course mode. Each LSB will introduce an offset of 2.17 ppm for normal mode and

4.34 ppm for course mode. The va lues of 2.17 ppm and 4.34 ppm are based on a nomina l

32.768 kHz clock. The offset value is coded in two’ s complem ent giving a range of

+63 LSB to −64 LSB.

[1] Default mode.

The correction is made by adding or subtracting 64 Hz clock correction pulses, thereby

changing the period of a single second.

In normal mode, the cor rection is triggered once per two h ours and then correction pulse s

are applied once per mi nute until the programmed correction values have been

implement.

In course mode, the correction is triggered once per hour and then correction pulses are

applied once per minu te up to a maximum of 60 mi nutes. When corr ection value s greater

than 60 are used, additio nal correction p ulses are made in th e 59th minute (see Table 38).

Table 36. Register Offset _register

OFFSET[6:0] Offset value in

decimal Offset value in ppm

Normal mode

MODE = 0 Course mode

MODE = 1

0 1 1 1 1 1 1 +63 +136.71 +273.42

0 1 1 1 1 1 0 +62 +134.54 +269.08

::::

0000010 +2 +4.34 +8.68

0000001 +1 +2.17 +4.34

0000000 0

[1] 00

1111111 −1−2.17 −4.34

1111110 −2−4.34 −8.68

::::

1000001 −63 −136.71 −273.42

1000000 −64 −138.88 −277.76

Table 37. Example of converting the offset in ppm to seconds

Offset in ppm Seconds per

Day Week Month Year

2.17 0.187 1.31 5.69 68.2

4.34 0.375 2.62 11.4 136

Product data sheet Rev. 5 — 27 April 2011 30 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

[1] Example is given in a time range from 2:00 to 2:59.

[2] Correction INT pulses are 1⁄128 s wide. F or multiple pulses they are repeated at 1⁄64 s interval.

It is possible to monitor when correction pulses are applied. The correction interrupt

enable mode (bit CIE) will generate a 1⁄128 second pulse on INT for every correction

applied. In the case where multiple correction pulses are applied, a 1⁄128 second interrupt

pulse will be generated and repeated every 1⁄64 seconds.

Correction is applied to the 1 Hz clock. Any timer or clock outp ut using a frequency of 1 Hz

or below will also be affected by the correction pulses.

Table 38. Correct ion pulses for course mode

Correction value Hour:Minute[1] Correction pulses on INT per

minute[2]

+1 or −1 02:00 1

02:01 to

02:59 0

+2 or −2 02:00 1

02:01 1

02:02 to

02:59 0

+3 or −3 02:00 1

02:01 1

02:02 1

02:03 to

02:59 0

:::

+59 or −59 02:00 to

02:58 1

02:59 0

+60 or −60 02:00 to

02:59 1

+61 or −61 02:00 to

02:58 1

02:59 2

+62 or −62 02:00 to

02:58 1

02:59 3

+63 or −63 02:00 to

02:58 1

02:59 4

−64 02:00 to

02:58 1

02:59 5

Product data sheet Rev. 5 — 27 April 2011 31 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

Table 39. Effect of correctio n pulses

Frequency (Hz) Effect of correction

CLKOUT

32768 no effect

16384 no effect

8192 no effect

4096 no effect

2048 no effect

1024 no effect

1effected

Time source clock

4096 no effect

64 no effect

1effected

1⁄60 effected

Product data sheet Rev. 5 — 27 April 2011 32 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.10 External clock test mode

A test mode is available which allo ws for on-board testing. In this mode it is possible to set

up test condition s an d co nt ro l the op e ratio n of th e RTC.

The test mode is entered by setting bit EXT_TEST in register Control_1. Then

pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the

signal applied to pin CLKOUT.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided

down to 1 Hz by a 26divide chain called a prescaler. The prescaler can be set into a

known state by using bit ST OP. When bit STOP is set, the prescaler is reset to 0. (STOP

must be cleared before the prescaler can operate again.)

From a stop condition, the first 1 second increment will take place after 32 positive edges

on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.

Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When

entering the test mode, no assumption as to the state of the prescaler can be made.

Operation ex am p l e:

1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1).

2. Set STOP (Control_1, bit STOP = 1).

3. Clear STOP (Control_1, bit STOP = 0).

4. Set time re gisters to desired value.

5. Apply 32 clock pulses to pin CLKOUT.

6. Read time registers to see the first change.

7. Apply 64 clock pulses to pin CLKOUT.

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

Product data sheet Rev. 5 — 27 April 2011 33 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

8.11 STOP bit function

The function of the STOP bit is to allow for accurate starting of the t ime circuits. The ST OP

bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and

thus no 1 Hz ticks will be generated. The time circuits can then be set and will not

increment until the STOP bit is released (see Figure 21 and Table 40).

The STOP bit function will not affect the output of 32.768 kHz, 16.384 kHz, or 8.192 kHz

(see Section 8.8).

The lower two stages of the prescaler (F0 and F1) are not reset and because the SPI-bus

is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be

between 0 and one 8.192 kHz cycle (see Figure 21).

The first increment of the time circuits is between 0.499878 s and 0.500000 s after STOP

bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset

(see Table 40).

Fig 20. STOP bit functional diagram

001aai556

OSCILLATOR

32768 Hz

16384 Hz

OSCILLATOR STOP

DETECTOR

F0F1F13

RESET

F14

RESET

2 Hz

1 Hz

1024 Hz

16384 Hz

8192 Hz

1 Hz tick

stop

CLKOUT source

oscillator stop flag

8192 Hz

4096 Hz

Fig 21. STOP bit release timing

001aaf91

8192 Hz

stop released

0 μs to 122 μs

Product data sheet Rev. 5 — 27 April 2011 34 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

[1] F0 is clocked at 32.768 kHz.

Table 40. First increment of time circuits after STOP bit release

Bit Prescaler bits[1] 1Hz tick Time Comment

STOP F0F1-F2 to F14 hh:mm:ss

Clock is running normally

01-0 0001 1101 0100

12:45:12 pr escaler counting normally

STOP bit is activated by user. F0F1 are not reset and values cannot be pr edicted externally

XX-0 0000 0000 0000

12:45:12 prescaler is reset; time circuits are frozen

New time is set by user

XX-0 0000 0000 0000

08:00:00 prescaler is reset; time circuits are frozen

STOP bit is released by user

XX-0 0000 0000 0000

08:00:00 prescaler is now running

XX-1 0000 0000 0000

08:00:00 -

XX-0 1000 0000 0000

08:00:00 -

XX-1 1000 0000 0000

08:00:00 -

11-1 1111 1111 1110

08:00:00 -

00-0 0000 0000 0001

08:00:01 0 to 1 transition of F14 increments the time circuits

10-0 0000 0000 0001

08:00:01 -

11-1 1111 1111 1111

08:00:01 -

00-0 0000 0000 0000

08:00:01 -

10-0 0000 0000 0000

08:00:01 -

11-1 1111 1111 1110

08:00:01 -

00-0 0000 0000 0001

08:00:02 0 to 1 transition of F14 increments the time circuits

013aaa352

0.499878 s to 0.500000 s

1 s

Product data sheet Rev. 5 — 27 April 2011 35 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

9. 3-line serial interface

Data transfer to and from the device is made via a 3-wire SPI-bus (see Table 41). The

data lines for input and ou tput ar e split. The da ta input and output lines can be connected

together to facilitate a bidirectional dat a bus. The chip enable signal is used to identify the

transmitted dat a. Each data transfer is a byte, wi th the Most Significant Bit (MSB) sent first

(see Figure 23).

The transmission is controlled by the active HIGH chip enable signal CE. The first byte

transmitted is the command byte. Subsequent bytes will be either data to be written or

data to be read. Data is sampled on the rising edge of the clock and transferred internally

on the falling edge.

The command byte defines the address of the first register to be accessed and the

read/write mode. The address counter will auto increment after every access and will

rollover to zero after the last register is accessed. The read/write bit (R/W) defines if the

following bytes will be read or write information.

Table 41. Serial interface

Symbol Function Description

CE chip enable input when LOW, the interface is reset; pull-down resistor

included; active input may be higher than VDD, but may not

be wired permanently HIGH

SCL serial clock input when CE is LOW, this input may float; input may be higher

than VDD

SDI serial data input when CE is LOW, inpu t may float; input may be higher than

VDD; input data is sampled on the rising edge of SCL

SDO serial data output pu sh-pull output; drives from VSS to VDD; output data is

changed on the falling edge of SCL; will be high-Z when not

driving; may be connected directly to SDI

Fig 22. SDI , SDO configurations

Fig 23. Data transfer overview

001aai56

SDI

two wire mode

SDO

SDI

single wire mode

SDO

001aaf9

COMMANDdata bus

chip enable

DATA DATADATA

Product data sheet Rev. 5 — 27 April 2011 36 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

In Figure 24, the register Seconds is set to 45 seconds and the register Minutes is set to

10 minutes.

Table 42. Comman d byte definition

Bit Symbol Value Description

7R/W data read or data write selection

0 write data

1 read data

6 to 4 SA 001 s ubaddress; other codes will cause the device

to ignore data transfer

3 to 0 RA 0h to Fh register address range

Fig 24. Serial bus write example

001aaf915

address

counter

SDI

SCL

02 03 04

seconds data 45BCD minutes data 10BCD

R/W addr 02HEX

Fig 25. Serial bus read example

001aaf916

address

counter

SDO

SDI

SCL

07 08 09

months data 11

BCD

years data 06

BCD

R/W addr 07

HEX

Product data sheet Rev. 5 — 27 April 2011 37 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

In Figure 25, the Months and Years registers are read. In this example, pins SDI and SDO

are not connected together. For this configuration, it is important that pin SDI is never left

floating. It must always be driven either HIGH or LO W. If pin SDI is left open, high IDD

currents may result. Short transition periods in the order of 200 ns will not cause any

problems.

9.1 Interface watchdog timer

During read/w rite op erat i on s, th e tim e cou nt in g circ uits are froze n . To pr ev en t a situ atio n

where the acces sin g de vice be com e s lock ed and does not clear the interface by setting

pin CE LOW, the PCF2123 has a built in watchdog timer. Should the interface be active

for more than 1 s from the time a valid subaddress is transmitted, then the PCF2123 will

automatically clear the interface a nd allow th e ti me cou nting cir cuits to continue counting.

CE must return LOW once more before a new data transfer can be executed.

The watchdog is implemented to prevent the excessive loss of time due to interface

access failure e.g. if main power is removed from a battery backed-up system during an

interface access.

Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The

watchdog will trigger between 1 s and 2 s after receiving a valid subaddress.

a. Correct data transfer: read or write

b. Incorrect data transfer: read or write

Fig 26. Interface watchdog timer

001aai56

valid sub-address

running

time

counters

WD timer

data

WD timer running

time counters frozen running

data

w(CE)

< 1 s

data data

001aai56

valid sub-address

running

time

counters

WD timer

data

WD timer running

data transfer fail

WD trips

time counters frozen running

data

1 s < t

w(CE)

< 2 s

data data

Product data sheet Rev. 5 — 27 April 2011 38 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

10. Internal circuitry

Fig 27. Device di ode protection diagram of PCF2123

001aai55

SDO

SDI

SCL

CLKOUT

CLKOE

OSCI

OSCO

TEST

INT

PCF2123

Product data sheet Rev. 5 — 27 April 2011 39 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

11. Limiting values

[1] With respect to VSS.

[2] Pass level; Human Body Model (HBM) according to Ref. 8 “JESD22-A114”

[3] Pass level; latch-up testing, according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).

[4] According to the NXP store and transport requirements (see Ref. 11 “NX3-00092”) the devices have to be

stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products

deviant conditions are described in that document.

Table 43. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage [1] −0.5 +6.5 V

IDD supply current −50 +50 mA

VIinput voltage [1] −0.5 +6.5 V

VOoutput voltage [1] −0.5 +6.5 V

IIinput curr en t −10 +10 mA

IOoutput current −10 +10 mA

Ptot total power dissipation - 300 mW

VESD electrostatic discharge

voltage HBM [2] -±3000 V

Ilu latch-up current [3] -200mA

Tstg storage temperature [4] −65 +150 °C

Tamb ambient temperature operating device −40 +85 °C

Product data sheet Rev. 5 — 27 April 2011 40 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

12. Static characteristics

Table 44. Static characteristics

VDD = 1.1 V to 5.5 V; VSS =0V; T

amb =

−

C to +85

C; fosc = 32.768 kHz; quartz Rs=15k

; CL= 7 pF; unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage for clock data integrity;

SPI-bus inactive [1] 1.1 - 5.5 V

Tamb =25°C-0.9-V

SPI-bus active 1.6 - 5.5 V

IDD supply current SPI-bus active

fSCL = 4.5 MHz;

VDD =5V - 250 400 μA

fSCL = 1.0 MHz;

VDD =3V -3080μA

SPI-bus inactive;

CLKOUT disabled [2]

Tamb =25°C;

VDD =2.0V - 100 - nA

Tamb =25°C;

VDD =3.0V -110-nA

Tamb =25°C;

VDD =5.0V - 120 - nA

SPI-bus inactive;

CLKOUT disabled;

Tamb =−40 °Cto +85°C

[2]

VDD = 2.0 V - - 330 nA

VDD = 3.0 V - - 350 nA

VDD = 5.0 V - - 380 nA

SPI-bus inactive;

CLKOUT enabled at 32 kHz;

Tamb =25°C

VDD = 2.0 V - 260 - nA

VDD = 3.0 V - 340 - nA

VDD = 5.0 V - 520 - nA

SPI-bus inactive;

CLKOUT enabled at 32 kHz;

Tamb =−40 °C to +85 °C

VDD = 2.0 V - - 450 nA

VDD = 3.0 V - - 550 nA

VDD = 5.0 V - - 750 nA

Product data sheet Rev. 5 — 27 April 2011 41 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

[1] For reliable oscillator start at power-on: VDD =V

DD(min) +0.3V.

[2] Timer source clock = 1⁄60 Hz, level of pins CE, SDI, and SCL is VDD or VSS.

[3] In case of an ESD event, the value may increase slightly.

[4] Implicit by design.

[5] Refers to external pull-up voltage.

[6] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: .

Inputs

VIL LOW-level input voltage - - 0.3VDD V

VIH HIGH-level input voltage 0.7VDD --V

VIinput voltage on pins CE, SDI, SCL, OSCI,

CLKOE, CLKOUT −0.5 - +5.5 V

ILI input leakage current VI=V

DD or VSS on pins SDI,

SCL, OSCI, CLKOE, CLKOUT [3] -0-μA

VI=V

SS on pin CE −10 - μA

Rpd pull-down resistance on pin CE - 240 550 kΩ

Ciinput capacitance on pins SDI, SCL, CLKOE and

CE [4] --7pF

Outputs

VOoutput voltage on pins CLKOUT and INT [5] −0.5 - +5.5 V

on pin OSCO −0.5 - +5.5 V

on pin SDO −0.5 - VDD +0.5 V

VOH HIGH-level output voltage on pin SDO 0.8VDD -V

DD V

VOL LOW-level output voltage on pin SDO VSS -0.2V

DD V

on pins CLKOUT and INT;

VDD =5V;

IOL =1.5mA

VSS -0.4V

IOH HIGH-level output current outpu t source current;

VOH =4.6V;

VDD = 5 V on pin SDO

1.5--mA

IOL LOW-level output current output sink current;

VOL =0.4V;

VDD = 5 V on pins INT, SDO

and CLKOUT

1.5--mA

ILO output leakage current VO=V

DD or VSS [3] -0-μA

CL(itg) integrated load

capacitance on pins OSCO and OSCI [6] 3.3 7 14 pF

Rsseries resistance - - 100 kΩ

Table 44. Static characteristics …continued

VDD = 1.1 V to 5.5 V; VSS =0V; T

amb =

−

C to +85

C; fosc = 32.768 kHz; quartz Rs=15k

; CL= 7 pF; unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Unit

CLitg()

COSCI COSCO

⋅()

COSCI COSCO

+()

--------------------------------------------

Product data sheet Rev. 5 — 27 April 2011 42 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

13. Dynamic characteristics

Table 45. SPI-bus characteristics

VSS =0V; T

amb =

−

C to +85

C. All timing values are valid within the operating supply voltage and temperature range and

referenced to VIL and VIH with an input voltage swing of VSS to VDD.

Symbol Parameter Conditions VDD = 1.6 V VDD = 2.4 V VDD = 3.3 V VDD = 5.0 V Unit

Min Max Min Max Min Max Min Max

Timing characteristics (se e Figure 28)

fclk(SCL) SCL clock frequency - 2.9 - 4.54 - 5.71 - 8.0 MHz

tSCL SCL time 345 - 220 - 175 - 125 - ns

tclk(H) clock HIGH time 90 - 50 - 45 - 40 - ns

tclk(L) clock LOW time 200 - 120 - 95 - 70 - ns

trrise time for SCL signal - 100 - 100 - 50 - 50 ns

tffall time for SCL signal - 100 - 100 - 50 - 50 ns

tsu(CE) CE set-up time 40 - 35 - 30 - 25 - ns

th(CE) CE hold time 40 - 30 - 25 - 15 - ns

trec(CE) CE recovery time 30 - 25 - 20 - 15 - ns

tw(CE) CE pulse width measur ed after valid

subaddress is

received

- 0.99 - 0.99 - 0.99 - 0.99 s

tsu set-up time set-up time for SDI

data 10-5-3-2-ns

thhold time hold time for SDI data 25 - 10 - 8 - 5 - ns

td(R)SDO SDO read delay time bus load = 50 pF - 190 - 108 - 85 - 60 ns

tdis(SDO) SDO disable time no load value; bus will

be held up by bus

capacitance; use RC

time constant with

application values

- 70 - 45 - 40 - 27 ns

tt(SDI-SDO) transition time from

SDI to SDO to avoid bus conflict 0 - 0 - 0 - 0 - ns

Product data sheet Rev. 5 — 27 April 2011 43 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

Fig 28. SPI-bus timing

001aai554

R/W SA2 RA0 b7 b6 b0

b7 b6 b0

b0b6b7SDI

SDO

Hi Z

SDI

SCL

WRITE

READ

tw(CE)

80%

20%

tclk(L)

tfth(CE)

trec(CE)

tdis(SDO)

td(R)SDO

tt(SDI-SDO)

tsu

tclk(H)

tSCL

tsu(CE)

Product data sheet Rev. 5 — 27 April 2011 44 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

14. Application information

A 1 farad super capacitor combined with a low VF diode can be used as a standby or back-up

supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC

may operate for weeks.

Fig 29. Typical application diagram

001aai55

CLKOEVDD CLKOUT

VSS

OSCI

OSCO

SCL

SDI

SDO

PCF2123

INT

100 nF

1 F

supercapacitor

Product data sheet Rev. 5 — 27 April 2011 45 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

15. Package outline

Fig 30. Package outline SOT758-1 (HVQFN16) of PCF2123BS/1

terminal 1

index area

0.51

A1Eh

UNIT y

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.75

1.45

3.1

2.9

1.75

1.45

1.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT758-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT758-

VQFN16: plastic thermal enhanced very thin quad flat package; no leads;

6 terminals; body 3 x 3 x 0.85 mm

A(1)

max.

detail X

y1C

16 13

02-03-25

02-10-21

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 5 — 27 April 2011 46 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

Fig 31. Package outline SOT402-1 (TSSOP14) of PCF2123TS/1

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.72

0.38

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402

-1

max.

1.1

pin 1 index

Product data sheet Rev. 5 — 27 April 2011 47 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

a. SOT758-1 (HVQFN16) of PCF2123BS/1

b. SOT402-1 (TSSOP14) of PCF2123TS/1

Fig 32. Three dimensional package drawings of PCF2123BS/1 and PCF2123TS/1

HVQFN16

PCF8885TS

Product data sheet Rev. 5 — 27 April 2011 48 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

16. Bare die outline

[1] Nominal die thickness. Compare with wafer thickness given in Table 50.

[2] Dimension includes saw lane.

[3] P1 and P3: pad size.

[4] P2 and P4: passivation opening.

Fig 33. Bare die outline PCF2123U/10 of PCF2123U/5GA/1 and PCF2123U/10AA/1 (for dimensions see Table 46)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

PCF2123U/10

Wire bond die; 12 bonding pads PCF2123U/10

08-07-24

11-04-06

scale

1 mm

P4P3

detail X

Table 46. Dimensions of PCF2123U /10

Original dimensions are in mm.

Unit (mm) A[1] D[2] E[2] eDP1[3] P2[4] P3[3] P4[4]

PCF2123U/5GA/1

nom 0.20 1.492 1.449 1.296 0.09 0.081 0.09 0.081

PCF2123U/10AA/1

nom 0.20 1.492 1.449 1.296 0.09 0.081 0.09 0.081

Product data sheet Rev. 5 — 27 April 2011 49 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

Fig 34. Bare die outline PCF2123U/12 of PCF2123U/12AA/1 and PCF2123U/12HA/1 (for dimensions see Table 47)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

PCF2123U/12 - - -

- - -

pcf2123u_12_do

10-07-13

11-04-06

WLCSP12: wafer level chip size package; 12 bumps. PCF2123U/12

0 0.5 1 mm

scale

detail Y

P4P3

detail X

0x 0

PC2123-1

Product data sheet Rev. 5 — 27 April 2011 50 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

[1] Nominal die thickness. Compare with wafer thickness given in Table 50.

[2] Dimension includes saw lane.

[3] P1 and P3: pad size.

[4] P2 and P4: bump size.

Table 47. Dimensions of PCF2123U /12

Original dimensions are in mm.

Unit (mm) A[1] A1A2[1] D[2] E[2] e P1[3] P2[4] P3[3] P4[4]

PCF2123U/12AA

max - 0.018 - - - 1.296 - 0.084 - 0.084

nom 0.22 0.015 0.2 1.492 1.449 - 0.09 0.081 0.09 0.081

min - 0.012 - - - 0.198 - 0.078 - 0.078

PCF2123U/12HA

max - 0.018 - - - 1.296 - 0.084 - 0.084

nom 0.17 0.015 0.15 1.492 1.449 - 0.09 0.081 0.09 0.081

min - 0.012 - - - 0.198 - 0.078 - 0.078

Table 48. Bump locations of all PCF2123U types

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip; see Figure 33 and Figure 34.

Symbol Bump Coordinates

x y

SDO 1 648.0 −575.0

SDI 2 648.0 −377.0

SCL 3 648.0 −179.0

CLKOE 4 648.0 171.2

CLKOUT 5 648.0 369.2

VDD 6 648.0 625.7

OSCI 7 −648.0 639.0

OSCO 8 −648.0 421.9

TEST 9 −648.0 −25.9

INT 10 −648.0 −223.9

CE 11 −648.0 −441.0

VSS 12 −648.0 −639.0

Product data sheet Rev. 5 — 27 April 2011 51 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

[1] The x/y coordinates of the alignment mark location represent the position of the REF point (see Figure 35)

with respect to the center (x/y = 0) of the chip; see Figure 33 and Figure 34.

[2] The x/y values of the dimensions represent t he extensions of the alignment mark in direction of the

coordinate axis (see Figure 35).

Table 49. Alignment mark dimen sion and location of all PCF2123U types

Coordinates

x y

Location[1]

693 −516.2

Dimension[2]

16 μm13μm

Fig 35. Alignme n t mark

013aaa231

REF

Product data sheet Rev. 5 — 27 April 2011 52 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

17. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent

standards.

18. Packing information

[1] Wafer mapping information will be distributed to customer’s ftp server.

(1) Die marking code.

Seal ring plus gap to active circuit ~18 μm.

Fig 36. PCF2123Ux wafer information

013aaa232

Saw lane

~18 μm

45 μm

70 μm

~18 μm

detail X

1.449 mm

1.492 mm

straight edge

of the wafer

(1)

Table 50. PCF2123Ux wafer information

Type number Wafer thickness (μm) Wafer diameter Marking of bad die

PCF2123U/5GA/1 687 6 inch wafer mapping[1]

PCF2123U/10AA/1 200 6 inch inking

PCF2123U/12AA/1 200 6 inch wafer mapping[1]

PCF2123U/12HA/1 150 6 inch inking

Product data sheet Rev. 5 — 27 April 2011 53 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

Fig 37. Film Frame Carrier (FFC) for 6 inch wafer (PCF2123U/10AA/1)

013aaa350

1.2+0 mm

−0.1

73.68 mm 71.79 mm

∅ 193.50 mm

∅ 225.50 mm

214.50 mm

0.25

metal frame

plastic film

straight edge

of the wafer

Fig 38. Film Frame Carrier (FFC) for 8 inch wafer (PCF2123U/12AA/1 and PCF2123U/12HA/1)

013aaa35

2.6 mm

60.2 mm 63.5 mm

∅ 250 mm

∅ 296 mm

276 mm

0.3

plastic frame

plastic film

straight edge

of the wafer

Product data sheet Rev. 5 — 27 April 2011 54 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

19. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

19.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

19.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orie ntation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

19.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 5 — 27 April 2011 55 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

19.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 39) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 51 and 52

Moisture sensitivity precautions, as indicated on the packing, must be respe cted at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 39.

Table 51. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperatu re (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 52. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperatu re (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 5 — 27 April 2011 56 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 39. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 5 — 27 April 2011 57 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

20. Footprint information for reflow soldering

Fig 40. Footprint information for reflow soldering of SOT758-1 (HVQFN16) package of PCF2123BS/1

SOT758-

ootprint information for reflow soldering of HVQFN16 package

Dimensions in mm

Ax Ay Bx By D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hx Hy

4.000 4.000 2.200 2.200

0.500 0.240

0.900 1.500 1.500 0.650 0.650 0.650 0.650 3.300 3.300 4.250 4.250

nSPx nSPy

sot758-1_fr

occupied area

SLx

AyBySLy

P 0.025 0.025

(0.105)

SPx tot

SPy tot

nSPx

nSPy

SPx

SPy

solder land plus solder paste

solder land

solder paste deposit

Generic footprint pattern

Refer to the package outline drawing for actual layout

Issue date 07-05-07

09-06-15

Product data sheet Rev. 5 — 27 April 2011 58 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

Fig 41. Footprint information for reflow soldering of SOT402-1 (TSSOP14) package of PCF2123TS/1

DIMENSIONS in mm

Ay By D1 D2 Gy HyP1 C Gx

sot402-1_fr

SOT402-

solder land

occupied area

ootprint information for reflow soldering of TSSOP14 package

AyByGy

Generic footprint pattern

Refer to the package outline drawing for actual layout

(0.125) (0.125)

D2 (4x)

7.200 4.500 1.350 0.400 0.600 4.950 5.300 7.4505.8000.650 0.750

Product data sheet Rev. 5 — 27 April 2011 59 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

21. Abbreviations

Table 53. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

BCD Binary Coded Decimal

ESD ElectroStatic Discharge

FFC Film Frame Carrier

HBM Hu ma n Body Model

LSB Least Significant Bit

MM Machine Model

MOS Metal Oxide Semiconductor

MSB Most Significant Bit

MSL Moisture Sensitivity Level

PCB Printed-Circuit Board

RTC Real Time Clock

SMD Surface Moun t Device

SPI Serial Peripheral Interface

Product data sheet Rev. 5 — 27 April 2011 60 of 63

NXP Semiconductors PCF2123

SPI Real time clock/calendar

22. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10366 — HVQFN application information

[3] AN10706 — Handling bare die

[4] AN10853 — Handling precautions of ESD sensitive devices

[5] IEC 60134 — Rating syst ems for electronic tubes and valves and analogous

semiconductor devices

[6] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[7] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[8] JESD22-A 11 4 — Elec trostatic Discharge (ESD) Sensitiv ity Testing Human Body

Model (HBM)

[9] JESD78 — IC Latch-Up Test

[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[11] NX3-00092 — NXP store and transport requirements

[12] SNV-FA-01-02 — Marking Formats Integrated Circuits

23. Revision history

Table 54. Revision history

Document ID Release date Data sheet st atus Change notice Supersedes

PCF2123 v.5 20110427 Product data sheet - PCF2123 v.4

Modifications: •Added product type PCF2123U/5GA/1

•Adjusted the bare die outline drawings

•Added 3d package drawings

•Added footprint information

PCF2123 v.4 20101222 Product data sheet - PCF2123 v.3

PCF2123 v.3 20101005 Product data sheet - PCF2123_2

PCF2123_2 20091204 Product data sheet - PCF2123_1

PCF2123_1 2 0081119 Product da ta sheet - -

Product data sheet Rev. 5 — 27 April 2011 61 of 63

NXP Semiconductors PCF2123

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24. Legal information

24.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

24.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

24.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expect ed

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 5 — 27 April 2011 62 of 63

NXP Semiconductors PCF2123

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Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifi cations, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semiconductors’

standard warrant y and NXP Semiconductors’ product specifications.

Bare die — All die are tested on compliance with their related technical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Ac cordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qua lify their application in

which the die is used.

All die sales are conditione d upon and sub ject to the custo mer enter ing into a

written die sale agreement with NXP Semiconductors through its legal

department.

24.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

25. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCF2123

SPI Real time clock/calendar

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 April 2011

Document identifier: PCF2123

Please be aware that important notices concerning this document and the product(s)

described herein, have been in cluded in section ‘Legal information’.

26. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Functional description . . . . . . . . . . . . . . . . . . . 6

8.1 Low power operation . . . . . . . . . . . . . . . . . . . . 6

8.1.1 Power consumption with respect to

quartz series resistance . . . . . . . . . . . . . . . . . . 6

8.1.2 Pow er consumption s with respec t to

timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8.2 Register overview. . . . . . . . . . . . . . . . . . . . . . . 8

8.3 Control registers. . . . . . . . . . . . . . . . . . . . . . . . 9

8.3.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9

8.3.1.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8.3.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11

8.4 Time and date function. . . . . . . . . . . . . . . . . . 12

8.4.1 Register Seconds . . . . . . . . . . . . . . . . . . . . . . 12

8.4.1.1 OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8.4.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 13

8.4.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 13

8.4.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 14

8.4.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 14

8.4.6 Register Months . . . . . . . . . . . . . . . . . . . . . . . 14

8.4.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 15

8.4.8 Setting and reading the time. . . . . . . . . . . . . . 15

8.5 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 17

8.5.1 Register Minute_alarm . . . . . . . . . . . . . . . . . . 17

8.5.2 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 17

8.5.3 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 17

8.5.4 Register Weekday_alarm . . . . . . . . . . . . . . . . 18

8.5.5 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.6 Timer functions. . . . . . . . . . . . . . . . . . . . . . . . 20

8.6.1 Register Timer_clkout. . . . . . . . . . . . . . . . . . . 20

8.6.2 Register Countdown_timer. . . . . . . . . . . . . . . 20

8.6.3 Minute and second interrupt. . . . . . . . . . . . . . 20

8.6.4 Countdown timer function. . . . . . . . . . . . . . . . 22

8.6.5 Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.7 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 25

8.7.1 Minute and second interrupts . . . . . . . . . . . . . 26

8.7.2 Countdown timer interrupts. . . . . . . . . . . . . . . 26

8.7.3 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 27

8.7.3.1 Correction pulse inte rrupts . . . . . . . . . . . . . . . 27

8.8 Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.8.1 CLKOE pin. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.9 Offset register . . . . . . . . . . . . . . . . . . . . . . . . 29

8.10 External clock test mode . . . . . . . . . . . . . . . . 32

8.11 STOP bit function. . . . . . . . . . . . . . . . . . . . . . 33

9 3-line serial interface . . . . . . . . . . . . . . . . . . . 35

9.1 Interface watchdog timer . . . . . . . . . . . . . . . . 37

10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 38

11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 39

12 Static characteristics . . . . . . . . . . . . . . . . . . . 40

13 Dynamic chara cteristics. . . . . . . . . . . . . . . . . 42

14 Application information . . . . . . . . . . . . . . . . . 44

15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 45

16 Bare die outline. . . . . . . . . . . . . . . . . . . . . . . . 48

17 Handling information . . . . . . . . . . . . . . . . . . . 52

18 Packing information . . . . . . . . . . . . . . . . . . . . 52

19 Soldering of SMD packages. . . . . . . . . . . . . . 54

19.1 Introduction to soldering. . . . . . . . . . . . . . . . . 54

19.2 Wave and reflow soldering. . . . . . . . . . . . . . . 54

19.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 54

19.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 55

20 Footprint information for reflow soldering. . 57

21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 59

22 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

23 Revision history . . . . . . . . . . . . . . . . . . . . . . . 60

24 Legal information . . . . . . . . . . . . . . . . . . . . . . 61

24.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 61

24.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

24.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 61

24.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 62

25 Contact information . . . . . . . . . . . . . . . . . . . . 62

26 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63