MC100LVEL16DG - ON SEMICONDUCTOR

August, 2008 − Rev. 6

1Publication Order Number:

MC100LVEL16/D

MC100LVEL16

3.3V ECL Differential

Receiver

Description

The MC100LVEL16 is a differential receiver. The device is

functionally equivalent to the EL16 device, operating from a 3.3 V

supply. The LVEL16 exhibits a wider VIHCMR range than its EL16

counterpart. With output transition times and propagation delays

comparable to the EL16 the LVEL16 is ideally suited for interfacing

with high frequency sources at 3.3 V supplies.

Under open input conditions, the Q input will be pulled down to VEE

and the Q input will be biased to VCC/2. This condition will force the

Q output low.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

Features

•300 ps Propagation Delay

•High Bandwidth Output Transitions

•The 100 Series Contains Temperature Compensation

•PECL Mode Operating Range: VCC = 3.0 V to 3.8 V

with VEE = 0 V

•NECL Mode Operating Range: VCC = 0 V

with VEE = −3.0 V to −3.8 V

•Internal Input Pulldown Resistors on D, Pullup and Pulldown

Resistors on D

•Q Output will Default LOW with Inputs Open or at VEE

•Pb−Free Packages are Available

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAMS*

KV16

ALYWG

SOIC−8

D SUFFIX

CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

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KVL16

ALYW

DFN8

MN SUFFIX

CASE 506AA

4B M G

(Note: Microdot may be in either location)

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M = Date Code

G= Pb−Free Package

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Figure 1. Logic Diagram and Pinout Assignment

D, D ECL Data Inputs

Q, Q ECL Data Outputs

VBB Reference Voltage Output

VCC Positive Supply

VEE Negative Supply

NC No Connect

Table 1. PIN DESCRIPTION

PIN FUNCTION

VEE

VCC

VBB

EP (DFN8 only) Thermal exposed pad

must be connected to a sufficient

thermal conduit. Electrically connect

to the most negative supply (GND) or

leave unconnected, floating open.

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 kW

Internal Input Pullup Resistor 75 kW

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 4 KV

> 400 V

> 2 kV

Moisture Sensitivity (Note 1) Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 79

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. Refer to Application Note AND8003/D for additional information.

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Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V

VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI  VCC

VI  VEE

6 to 0

−6 to 0

Iout Output Current Continuous

Surge

100

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM

500 LFPM

SO−8

190

130

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board SO−841 to 44 ± 5% °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM

500 LFPM

TSSOP−8

185

140

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−841 to 44 ± 5% °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

DFN8

129

°C/W

Tsol Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265

°C

qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

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Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 3)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 17 23 17 23 18 24 mA

VOH Output HIGH Voltage (Note 4) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV

VOL Output LOW Voltage (Note 4) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV

VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV

VIL Input LOW Voltage (Single−Ended) 1490 1825 1490 1825 1490 1825 mV

VBB Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 5)

Vpp < 500 mV

Vpp y 500 mV

1.2

1.5

2.9

1.1

1.4

2.9

1.1

1.4

2.9

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D

0.5

−600

0.5

−600

0.5

−600

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.

4. Outputs are terminated through a 50 W resistor to VCC − 2 V.

5. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.

Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.

Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 6)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 17 23 17 23 18 24 mA

VOH Output HIGH Voltage (Note 7) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV

VOL Output LOW Voltage (Note 7) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV

VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV

VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV

VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 8)

Vpp < 500 mV

Vpp y 500 mV

−2.1

−1.8

−0.4

−2.2

−1.9

−0.4

−2.2

−1.9

−0.4

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D

0.5

−600

0.5

−600

0.5

−600

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

6. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.

7. Outputs are terminated through a 50 W resistor to VCC − 2 V.

8. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.

Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.

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Table 6. AC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V or VCC= 0.0 V; VEE= −3.3 V (Note 9)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Toggle Frequency 1.75 1.75 1.75 GHz

tPLH

tPHL

Propagation Delay to Output

Differential

Single−Ended

150

100

275

400

450

225

175

300

375

425

240

190

315

390

440

tSKEW Duty Cycle Skew (Differential) (Note 10) 5 30 5 20 5 20 ps

tJITTER Random Clock Jitter (RMS) 0.7 0.7 0.7 ps

VPP Input Swing (Note 11) 150 1000 150 1000 150 1000 mV

Output Rise/Fall Times Q

(20% − 80%)

120 220 320 120 220 320 120 220 320 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

9. VEE can vary ±0.3 V.

10.Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.

11. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.

Figure 2. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

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ORDERING INFORMATION

Device Package Shipping†

MC100LVEL16D SO−898 Units / Rail

MC100LVEL16DG SO−8

(Pb−Free)

98 Units / Rail

MC100LVEL16DR2 SO−82500 Tape & Reel

MC100LVEL16DR2G SO−8

(Pb−Free)

2500 Tape & Reel

MC100LVEL16DT TSSOP−8100 Units / Rail

MC100LVEL16DTG TSSOP−8

(Pb−Free)

100 Units / Rail

MC100LVEL16DTR2 TSSOP−82500 Tape & Reel

MC100LVEL16DTR2G TSSOP−8

(Pb−Free)

2500 Tape & Reel

MC100LVEL16MNR4 DFN8 1000 / Tape & Reel

MC100LVEL16MNR4G DFN8

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC100LVEL16

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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PACKAGE DIMENSIONS

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

TSSOP−8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

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PACKAGE DIMENSIONS

DFN8

CASE 506AA−01

ISSUE D

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

ÇÇÇÇ

C0.10

PIN ONE

2 X

REFERENCE

2 X

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

8 X

SEATING

PLANE

e/2 e

8 X

NOTE 3

8 X 0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

K0.20 −−−

L0.25 0.35

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

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Phone: 81−3−5773−3850

MC100LVEL16/D

ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).

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