2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 1
TC1232
Features
• Precision Voltage Monitor
- Adjustable +4.5V or +4.75V
• Reset Pulse Width – 250 msec minimum
• No Externa l Compo nen t s
• Adjustable Watchdog Timer
- 150 msec, 600 msec or 1.2 sec
• Operating Voltage 4.0V to 5.5V
• Debounced Manual Reset Input for External
Override
Block Diagram
General Description
The TC1232 is a fully-integrated processor supervisor
that provides three important functions to safeguard
processor sanity: precision power on/off reset control,
watchdog timer and external reset override.
On power-up, the TC1232 holds the processor in the
reset state for a minimum of 250 msec after VCC is
within tolerance to ensure a stable system start-up.
Microprocessor sanity is monitored by the onboard
watchdog circuit. The microprocessor must provide a
periodic low-going signal on the ST input. Should the
processor fail to supply this signal within the selected
time-out period (150 msec, 600 msec or 1200 msec),
an out-of-control processor is indicated and the
TC1232 issues a processor reset as a result.
The outputs of the TC1232 are immediately driven
active when the PB input is brought low by an external
push button switch or other electronic signal. When
connected to a push button switch, the TC1232
provides contact debounce.
The TC12 32 is packag ed in a space-s aving 8-Pin PDIP
or SOIC package, a 16-Pin SOIC (wide) package and
requires no external components.
Package Types
Device Features
+
–
VREF
++
–
RST
RST
Tolerance
Select
(5% or 10%)
TOL
VCC
Debounce
Watchdog
Timebase
Select
PB RST
TD Watchdog
Timer ST
Reset
Generator
Device
RST pin RST pin T rip Points
(Max)
Minimum
Reset
Active Tim e
(ms)
WDI Input
Typical
Timeouts (ms)
MR
Input
Type Pull-up
Resistor Active
Level Type Active
Level
TC1232 Open-drain External Low Push-pull High 4.75V
or 4.5V 250 150, 600 or
1200 Yes
13
12
11
10
9
15
14
18
27
36
45
TC1232
RST
RST
GND
TOL
TD
PB RST
RST
ST
VCC
RST
ST
18
27
36
45
RSTGND
TOL
TD
PB RST
RST
ST
VCC PB RST VCC
1
2
3
4
5
6
7
8
16
NC
TD
NC NC
TOL
GND
NC
NC
NC
TC1232
NC
NC
16-Pin SOIC (Wide)8-Pin PDIP 8-Pin SOIC
TC1232
18
36
45
TC1232
Microprocessor Monitor
TC1232
DS21370D-page 2 Preliminary 2002-2012 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
Voltage on Any Pin (With Respect to GND)
......................................................-0.3V to +5.8V
Operati ng Temperatu r e Range :
C-Version ........................................0°C to +70°C
E-Version......................................-40°C to +85°C
Storage Temperature Range: ............-65°C to +150°C
† Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and funct ional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unle ss otherwi se noted, TA = TMIN to TMAX; VCC = +4.0V to 5.5V.
Parameters Sym Min Typ Max Units Conditions
Supply Voltage VCC 4.0 5.0 5.5 V
ST and PB RS T Input High Le vel VIH 2.0 — VCC +0.3 V Note 1
ST and PB RST Input Low Level VIL -0.3 — +0.8 V
Input Leakage ST, TOL IL-1.0 — +1.0 µA
Output Current RST IOH -1.0 -12 — mA VOH = 2.4V
Current RST, RST IOL 2.0 10 — mA VOL = 0.4V
Operati ng Curren t ICC — 50 200 µA Note 2
VCC 5% Trip Point VCCTP 4.50 4.62 4.74 V TOL = GND (Note 3)
VCC 10% Trip Point VCCTP 4.25 4.37 4.49 V TOL = VCC (Note 3)
Capacitance Electrical Characteristics: Unless otherw is e note d, TA = +2 5°C. (Note 4)
Input Ca pacitance ST, TOL CIN —— 5 pF
Output Capacitance RST, RST COUT —— 7 pF
Note 1: PB RST is internally pulled up to VCC with an internal impedance of typically 40 k.
2: Measured with outputs open.
3: All voltages referenced to GND.
4: Ensured by design.
2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 3
TC1232
FIGURE 1-1: Rise Time, Fall Time and Reset Detected to Reset Active Timing Waveforms.
AC CHARACTERISTICS
Electrical Specifications: Unle ss otherwi se noted, TA = TMIN to TMAX; VCC = +4.0V to 5.5V.
Parameters Sym Min Typ Max Units Conditions
VCC Fall Time tF10 — — µs Note 1
VCC Rise Time tR0——µsNote 1
VCC Trip Point Detected
to RST High and RST Low tRPD — — 100 ns VCC falling
VCC Trip Point Detected
to RST High and RST Open tRPU 250 610 1000 ms VCC ris ing (Note 2)
Note 1: Ensured by design.
2: tR = 5 µs.
+4.75V
tF
VCC
+4.25V
tR
VCC
+4.25V
+4.75V
VCC = 5V
+4. 5V (5% Trip Point)
+4.25V (10% Trip Point)
RST
RST VOL
VOH
tRPD
VCC
4.6V (5% Trip Point)
4.5V(10% Trip Point)
RST
RST VOL
VOH
tRPU
Determined by
external Pull-up
resistor
Determined by
external Pull-up
resistor
TC1232
DS21370D-page 4 Preliminary 2002-2012 Microchip Technology Inc.
FIGURE 1-2: Push Button Reset and Watchdog Timer Reset Timing Waveforms.
AC CHARACTERISTICS (CONTINUE D)
Electrical Specifications: Unle ss otherwi se noted, TA = TMIN to TMAX; VCC = +4.0V to 5.5V.
Parameters Sym Min Typ Max Units Conditions
PB RST Pulse Width tPB 20 — — ms Note 1
PB RST Falling Edge Low to
Res et Active tPBD 1420ms
PB RST Rising Edge High to
Reset Inactive tRST 250 610 1000 ms
ST Pulse Width tST 20 — — ns
ST Time-out Period tTD 62.5 150 250 ms TD Pin = 0V
250 600 1000 ms TD Pin = Open
500 1200 2000 ms TD Pin = VCC
Note 1: PB RST must be held low for a minimum of 20 ms to ensure a reset.
RST
VIL
tPB
RST
tPBD
VIH
tRST
PB RST
The debounced PB RST input ignores input pulses less
than 1 ms and is designed to recognize pulses of
20 ms or greater.
tST
ST tTD
RST (when tTD tTD (min)) “H”
RST
(when tTD(min) tTD tTD(max))
(when tTD tTD(max))
RST
RST (when tTD tTD(min)) “L”
RST
(when tTD(min) tTD tTD(max))
(when tTD tTD(max))
RST
2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 5
TC1232
2.0 TYPICAL PERFORMANCE CURVES
Perf orma nce G raphs are not available.
TC1232
DS21370D-page 6 Preliminary 2002-2012 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
The desc riptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLES
Pin No.
Symbol Pin
Type
Buffer/
Driver
Type Function
8-pin
PDIP,
SOIC
16-pin
SOIC
1 2 PB RST I ST Push-button Reset Input.
Input for a Manual Reset Switch. This input debounces (ignores) puls es
less than 1 ms in duration and is ensured to recognize inputs of 20 ms or
greater.
L = Manual Reset Switch is Active, Force RST/RST pins Active
H = Manual Reset Switc h is Ina ctive . State of RST/RST pins det ermine d by
other system conditions.
2 4 TD I ST Time Delay Input.
The voltage level on this input determines the watchdog timer time-out
period.
TD = 0V tTD = 150 ms
TD = Open tTD = 600 ms
TD = VCC tTD = 1.2 sec
3 6 TOL I ST Tolerance Input.
TOL = GND, Max Voltage Trip Point (VCCTP) = 4.75V (5% tolerance)
TOL = VCC, Max Voltage Trip Point (VCCTP) = 4.5V (10% toleranc e)
4 8 GND — P The ground reference for the device.
59RSTOPush
Pull Reset Output (Active-High)
Goes active (High) if one of these conditions occurs:
1. If VCC falls below the selected reset voltage threshold.
2. If PB RST pin is forced low.
3. If ST pin is not stro bed withi n the mini mum s electe d time-o ut period .
(see TD pin)
4. During power-up
611RST
O Open
Drain Reset Output (Active-Low)
Goes active (Low) if one of these conditions occurs:
1. If VCC falls below the selected reset voltage threshold.
2. If PB RST pin is forced low.
3. If ST pin is not stro bed withi n the mini mum s electe d time-o ut period .
(see TD pin)
4. During power-up
713 ST I ST Strobe Input
Input for Watchdog Timer. WDT period determined by state of TD pin
Falling Edge Resets Watchdog Timer counter (no time-out)
815V
CC — P The positive supply (+5V) for the device.
— 1,3,5,
7,10,1
2,16
NC — — No internal connection.
2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 7
TC1232
4.0 OPERATIONAL DESCRIPTION
4.1 Power Monitor
The TC1232 provides the function of warning the
processor of a power fai lure . When VCC is detected as
being below the voltage levels defined by the TOL pin,
the TC1232’s comparator outputs the RST and RST
signal s to a logic level tha t warns the syste m of an out-
of-tolerance power supply. The RST and RST signals
switch at a th reshold value of 4.5V i f TO L is tied to VCC,
and at a value of 4.75 volts if TOL is grounded. The
RST and RST signal s are held ac tiv e for a min im um of
250 ms to ensure that the power supply voltage has
been stabilized.
Figure 4-1 shows the VCC fall time .
Figure 4-2 shows the VCC rise time.
Figure 4-3 shows the time from when the voltage trip
point is detected to the reset output pin going active.
Figure 4-4 shows the time from when the voltage trip
point is exited to the reset output pin going inactive.
FIGURE 4-1: Power-Down Slew Rate.
FIGURE 4-2: Power-up Slew Rate.
FIGURE 4-3: VCC Detect Reset Output
Delay (Power-Down).
FIGURE 4-4: VCC Detect Reset Output
Delay (Power-Up).
+4.75V
tF
VCC
+4.25V
tR
VCC
+4.25V
+4.75V
VCC = 5V
+4.5V (5% Trip Point)
+4.25V (10% Trip Point)
RST
RST VOL
VOH
tRPD
VCC SLEW RATE = 1.66 mV/µs (0.5V/300 µs)
VCC
4.6V (5% Trip Point)
4.5V(10% Trip Point )
RST
RST VOL
VOH
tRPU
TC1232
DS21370D-page 8 Preliminary 2002-2012 Microchip Technology Inc.
4.2 Push Button Reset Input
The debo unced man ual reset inpu t (PB RST) manu ally
forces the reset outputs into their active states.
Figure 4-5 shows a block diagram for using the
TC1232 with a push button switch.
Once PB RST has been low for a time tPBD (the push-
button delay time), the reset outputs go active. The
reset outputs remain in their active states for a
minimum of 250 ms after PB RST rises above VIH.
Figure 4-6 shows a waveform for the push button
switch input and the reset pins output.
A mechanical push button or active logic signal can
drive the P B RST input. The debounced input ignores
input pulses less than 1 ms and recognizes pulses of
20 ms or greater. No external pull-up resistor is
required because the PB RST input has an internal
pull-up to VCC of approximately 100 µA. FIGURE 4-5: Push Button Reset and
Watchdog Timer.
FIGURE 4-6: Push Button Reset –
PB RST Input.
VCC
TOL
PB RST
GND
RST
ST I/O
Reset
+5V
TC1232
TD
Microprocessor
RST
VIL
tPB
RST
tPBD
VIH
tRST
PB RST
The debounced PB RST input ignores input pulses less
than 1 ms and is designed to recognize pulses of
20 ms or greater .
2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 9
TC1232
4.3 Watchdog Timer
When the ST input is not stimulated for a preset time
period, the watchdog timer function forces RST and
RST signals to the active state. The preset time period
is determined by the TD inputs to be 150 ms with TD
connected to ground, 600 ms with TD floating or
1200 ms with TD connected to VCC (typ.). The
watchdog timer starts timing-out from the set time
period as s oon as RST and R ST are inactiv e. If a high-
to-low transition occurs on the ST input pin prior to
time-out, the watchdog timer is reset and begins to
time-ou t again. If the watchdo g timer is allowed to time-
out, the RST and RST signals are driven to the active
state for 250 ms, minimum (Figure 4 -7).
The software routine that strobes ST is critical. The
code must be in a section of software that is executed
frequently enough so the time between toggles is less
than the watchdog time-out period. One common
techniq ue controls the microprocessor I/O line from two
sectio ns of the p rogram. The sof tware migh t set the I/O
line high while operating in the Foreground mode and
set it low whi le in the Ba ckgro und o r Interru pt mo des. If
both modes do not execute correctly, the watchdog
timer issues reset pulses.
tTD is the maximum elapsed time between ST high-to-
low transitions (ST is activated by falling edges only),
which will keep the watchdog timer from forcing the
reset outputs active for a time of tRST. tTD is a function
of the voltage at the TD pin, as tabulated below:
TABLE 4-1: WATCHDOG TIMER
PERIODS
Figure 4-7 shows a block diagram for using the
TC1232 with a PICmicro® MCU and the Watchdog
input.
FIGURE 4-7: Watchdog Timer.
Figure 4-8 shows the expected reset output pin wave-
forms depending on the period of the ST pin falling
edge and the state of the TD input pin.
FIGURE 4-8: Strobe Input.
4.4 Supply Monitor Noise Sensitivity
The TC1 232 is op timized for fa st resp onse to ne gative-
going changes in VDD. Systems with an inordinate
amount of electrical noise on VDD (such as systems
using relays) may require a 0.01 µF or 0.1 µF bypass
capacitor to reduce detection sensitivity. This capacitor
should b e installed as cl ose to the TC1232 as po ss ible
to keep the capacitor lead length short.
Condition
tTD
Min Typ Max
TD pin = 0V 62.5 ms 150 ms 250 ms
TD pin = Open 250 ms 600 ms 1000 ms
TD pin = VCC 500 ms 1200 ms 2000 ms
VCC
TOL GND
RST
ST
RESET
+5V
TC1232
TD
0.1
10 k
I/O
PICmicro®
3-Terminal
Regulator
+5V
µF MCU
(example:
MCP1700)
tST
ST tTD
RST (when tTD tTD (min)) “H”
RST
(when tTD(min) tTD tTD(max))
(when tTD tTD(max))
RST
RST (when tTD tTD(min)) “L”
RST
(when tTD(min) tTD tTD(max))
(when tTD tTD(max))
RST
TC1232
DS21370D-page 10 Preliminary 2002-2012 Microchip Technology Inc.
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Examples:
8-Lead SOIC (150 mil) Examples:
XXXXXXXX
XXXXYYWW
NNN
TC1232
I/P256
0518
TC1232
COA0518
256
16-Lead SOIC (150 mil) Examples:
XXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXX TC1232COE
0518256
XXXXXXXXXX
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (las t 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanume ric trac eability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will
be carried over to the next line, thus limiting the number of available
characte rs for customer-specific information.
3
e
3
e
TC1232
CPA^^256
0518
TC1232E
OA^^0518
256
TC1232COE^^
0518256
XXXXXXXXXX
OR
OR
OR
3
e
3
e
3
e
2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 11
TC1232
8-Lead Plastic Dual In-line (PA) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
E
eB
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Pa ckag e Thickness A2 .115 .130 .145 2.92 3. 30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Pa ckag e Width E1 .240 .2 50 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top 51015 51015
Mold Draft Angle Bottom 51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
Note: For th e mo s t c urr e nt pac kag e d r awi n gs , plea se se e th e M ic roc hi p Pa c ka gi n g Speci f ic at i on lo c at e d
at http://www.microchip .com/packaging
TC1232
DS21370D-page 12 Preliminary 2002-2012 Microchip Technology Inc.
8-Lead Plastic Small Outline (OA) – Narrow, 150 mil (SOIC)
Foot Angle 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Package Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Package Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Number of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
c
45
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com /p a ck agi ng
2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 13
TC1232
16-Lead Plastic Small Outline (OE) – Wide, 300 mil (SOIC)
Foot Angle 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 10.4910.3010.10.413.406.398DOverall Length 7.597.497.39.299.295.291E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 1616
n
Number of Pins MAXNOMMINMAXNOMMIND im en sion Li mits MILLIMETERSINCHES*Units
L
c
h
45
1
2
D
p
n
B
E1
E
A2
A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-102
§ Significant Characteristic
Note: For the most cu rr e nt pac ka ge dr aw i ngs, p le ase se e t he Mi c ro c hi p Pa ck ag ing Specifica t i on lo ca t ed
at http://www.microchip.com/packaging
TC1232
DS21370D-page 14 Preliminary 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 15
TC1232
APPENDIX A: REVIS ION HISTORY
Revision D (November 2012)
• Added a note to the package outline drawing.
Revision C (June 2005)
The following is the list of modifi cations:
1. Since no data is given in Section 2.0 “Typical
Performance Curves”, “Preliminary” was
added to the bottom of this document.
2. Corrected Operating Voltage in the Electrical
Specifications
3. Gener al Data Shee t Enhancements
4. A dded Revision History Appendix Section
Revision B (March 2003)
• Not logged
Revision A (March 2002)
• Original Release of this Document .
TC1232
DS21370D-page 16 lPreliminary 2002-2012 Mic rochip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. Preliminary DS21370D-page 17
TC1232
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
TC1232
DS21370D-page 18 Preliminary 2002-2012 Microchip Technology Inc.
NOTES:
2002-2012 Microchip Technology Inc. Preliminary DS21370C-page 19
Information contained in this publication regarding device
applications a nd the lik e is provided only f or yo ur convenience
and may be supers ed ed by u pda t es . It is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTA RT, PIC 32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Contro l Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In-Circuit Serial
Programm ing, ICSP, Mindi, MiWi, MPAS M, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total E ndurance, T SHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2002-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620767467
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of t he most secure famili es of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal m et hods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS21370C-page 20 Preliminary 2002-2012 Microchip Technology Inc.
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Worldwide Sales and Service
10/26/12