DAC088S085CIMT/NOPB - NATIONAL SEMICONDUCTOR

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

DAC088S085 8-Bit Micro Power OCTAL Digital-to-Analog Converter With Rail-to-Rail

Outputs

1 Features

1• Ensured Monotonicity

• Low Power Operation

• Rail-to-Rail Voltage Output

• Daisy Chain Capability

• Power-On Reset to 0 V

• Simultaneous Output Updating

• Individual Channel Power Down Capability

• Wide Power Supply Range (2.7 V to 5.5 V)

• Dual Reference Voltages With Range of 0.5 V to

• Operating Temperature Range of –40°C to 125°C

• Industry's Smallest Package

• Key Specifications

– Resolution: 8 Bits

– INL: ±0.5 LSB (Maximum)

– DNL: 0.15 / –0.1 LSB (Maximum)

– Settling Time: 4.5 µs (Maximum)

– Zero Code Error: 15 mV (Maximum)

– Full-Scale Error: –0.75 %FSR (Maximum)

– Supply Power :

– Normal: 1.95 mW (3 V) / 4.85 mW (5 V)

Typical

– Power Down: 0.3 µW (3 V) / 1 µW (5 V)

Typical

2 Applications

• Battery-Powered Instruments

• Digital Gain and Offset Adjustment

• Programmable Voltage and Current Sources

• Programmable Attenuators

• Voltage Reference for ADCs

• Sensor Supply Voltage

• Range Detectors

3 Description

The DAC088S085 is a full-featured, general-purpose,

OCTAL, 8-bit, voltage-output, digital-to-analog

converter (DAC) that can operate from a single 2.7 V

to 5.5 V supply and consumes 1.95 mW at 3 V and

4.85 mW at 5 V. The DAC088S085 is packaged in a

16-pin WQFN package and a 16-pin TSSOP

package. The WQFN package makes the

DAC088S085 the smallest OCTAL DAC in its class.

The on-chip output amplifiers allow rail-to-rail output

swing and the three-wire serial interface operates at

clock rates up to 40 MHz over the entire supply

voltage range. Competitive devices are limited to

25‑MHz clock rates at supply voltages in the range of

2.7 V to 3.6 V. The serial interface is compatible with

standard SPI™, QSPI, MICROWIRE, and DSP

interfaces. The DAC088S085 also offers daisy chain

operation where an unlimited number of devices can

be updated simultaneously using a single serial

interface.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DAC088S085 TSSOP (16) 5.00 mm × 4.40 mm

WQFN (16) 4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

DNL vs Code

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

www.ti.com

Product Folder Links: DAC088S085

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 3

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 6

7.6 AC and Timing Requirements................................... 8

7.7 Typical Characteristics.............................................. 9

8 Detailed Description............................................ 14

8.1 Overview................................................................. 14

8.2 Functional Block Diagram....................................... 14

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 16

8.5 Programming........................................................... 17

9 Application and Implementation ........................ 20

9.1 Application Information............................................ 20

9.2 Typical Applications ................................................ 25

9.3 Do's and Don'ts....................................................... 27

10 Power Supply Recommendations ..................... 27

10.1 Using References as Power Supplies................... 27

11 Layout................................................................... 29

11.1 Layout Guidelines ................................................. 29

11.2 Layout Example .................................................... 30

12 Device and Documentation Support................. 31

12.1 Device Support...................................................... 31

12.2 Community Resources.......................................... 32

12.3 Trademarks........................................................... 32

12.4 Electrostatic Discharge Caution............................ 32

12.5 Glossary................................................................ 32

13 Mechanical, Packaging, and Orderable

Information........................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (March 2013) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 29

PAD

16 DOUT!

VA!

1VOUTA! 12 VOUTE!

15 DIN!

VREF1!

2VOUTB! 11 VOUTF!

14 SCLK

VREF2!

3VOUTC! 10 VOUTG!

GND

4VOUTD! 9 VOUTH!

SYNC

1DIN! 16 SCLK

2DOUT! SYNC

3VOUTA! 14 VOUTE!

4VOUTB! 13 VOUTF!

5VOUTC! 12 VOUTG!

6VOUTD! 11 VOUTH!

7VA! 10 GND

8VREF1! 9 VREF2!

DAC088S085

www.ti.com

SNAS424D –AUGUST 2007–REVISED APRIL 2016

Product Folder Links: DAC088S085

5 Description (continued)

There are two references for the DAC088S085. One reference input serves channels A through D, while the

other reference serves channels E through H. Each reference can be set independently between 0.5 V and VA,

providing the widest possible output dynamic range. The DAC088S085 has a 16-bit input shift register that

controls the mode of operation, the power-down condition, and the DAC channels' register and output value. All

eight DAC outputs can be updated simultaneously or individually.

A power-on reset circuit ensures that the DAC outputs power up to 0 V and remain there until there is a valid

write to the device. The power-down feature of the DAC088S085 allows each DAC to be independently powered

with three different termination options. With all the DAC channels powered down, power consumption reduces

to less than 0.3 µW at 3 V and less than 1 µW at 5 V. The low power consumption and small packages of the

DAC088S085 make it an excellent choice for use in battery-operated equipment.

The DAC088S085 is one of a family of pin-compatible DACs, including the 10-bit DAC108S085 and the 12-bit

DAC128S085. All three parts are offered with the same pinout, allowing system designers to select a resolution

appropriate for their application without redesigning their printed-circuit board. The DAC088S085 operates over

the extended industrial temperature range of –40°C to 125°C.

6 Pin Configuration and Functions

RGH Package

16-Pin WQFN

Top View PW Package

16-Pin TSSOP

Top View

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

www.ti.com

Product Folder Links: DAC088S085

(1) WQFN only

Pin Functions

TYPE DESCRIPTION

NAME NO.

WQFN TSSOP

DIN 15 1 Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of

SCLK after the fall of SYNC.

DOUT 16 2 Digital Output Serial Data Output. DOUT is used in daisy chain operation and is connected directly to a

DIN pin on another DAC088S085. Data is not available at DOUT unless SYNC remains

low for more than 16 SCLK cycles.

GND 8 10 Ground Ground reference for all on-chip circuitry.

SCLK 14 16 Digital Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of

this pin.

SYNC 13 15 Digital Input

Frame Synchronization Input. When this pin goes low, data is written into the DAC's

input shift register on the falling edges of SCLK. After the 16th falling edge of SCLK, a

rising edge of SYNC causes the DAC to be updated. If SYNC is brought high before

the 15th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the

write sequence is ignored by the DAC.

VA5 7 Supply Power supply input. Must be decoupled to GND.

VOUTA 1 3 Analog Output Channel A Analog Output Voltage.

VOUTB 2 4 Analog Output Channel B Analog Output Voltage.

VOUTC 3 5 Analog Output Channel C Analog Output Voltage.

VOUTD 4 6 Analog Output Channel D Analog Output Voltage.

VOUTE 12 14 Analog Output Channel E Analog Output Voltage.

VOUTF 11 13 Analog Output Channel F Analog Output Voltage.

VOUTG 10 12 Analog Output Channel G Analog Output Voltage.

VOUTH 9 11 Analog Output Channel H Analog Output Voltage.

VREF1 6 8 Analog Input Unbuffered reference voltage shared by Channels A, B, C, and D. Must be decoupled

to GND.

VREF2 7 9 Analog Input Unbuffered reference voltage shared by Channels E, F, G, and H. Must be decoupled

to GND.

PAD(1) — — Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad

to the PCB offers optimal thermal performance and enhances package self-alignment

during reflow.

I/O

GND

TO INTERNAL

CIRCUITRY

DAC088S085

www.ti.com

SNAS424D –AUGUST 2007–REVISED APRIL 2016

Product Folder Links: DAC088S085

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin must be limited to 10 mA. The 30-mA

maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10

mA to three.

(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula

PDMAX = (TJmax – TA) / RθJA. The values for maximum power dissipation is reached only when the device is operated in a severe fault

condition (for example, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

Such conditions must always be avoided.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)

MIN MAX UNIT

Supply voltage, VA6.5 V

Voltage on any input pin –0.3 6.5 V

Input current at any pin(4) 10 mA

Package input current(4) 30 mA

Power Consumption at TA= 25°C See(5)

Junction temperature, TJ150 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

Machine model (MM) ±250

(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(2) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, does not cause errors in the

conversion result. For example, if VAis 3 V, the digital input pins can be driven with a 5 V logic device.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Operating temperature, TA–40 125 °C

Supply voltage, VA2.7 5.5 V

Reference voltage, VREF1,2 0.5 VAV

Digital input voltage(2) 0 5.5 V

Output load 0 1500 pF

SCLK frequency 40 MHz

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

www.ti.com

Product Folder Links: DAC088S085

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Soldering process must comply with Texas Instruments' Reflow Temperature Profile specifications. See http://www.ti.com/packaging.

Reflow temperature profiles are different for lead-free packages.

7.4 Thermal Information

THERMAL METRIC(1)(2) DAC088S085

UNITPW (TSSOP) RGH (WQFN)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 130 38 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 32 21 °C/W

RθJB Junction-to-board thermal resistance 44.2 9.8 °C/W

ψJT Junction-to-top characterization parameter 2 0.2 °C/W

ψJB Junction-to-board characterization parameter 43.5 9.8 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — 2.4 °C/W

(1) This parameter is specified by design or characterization and is not tested in production.

7.5 Electrical Characteristics

The following specifications apply for VA= 2.7 V to 5.5 V, VREF1 = VREF2 = VA, CL= 200 pF to GND, fSCLK = 30 MHz, input

code range 3 to 252. Typical values apply for TA= 25°C; minimum and maximum limits apply for TA= –40°C to 125°C, unless

otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STATIC PERFORMANCE

Resolution 8 Bits

Monotonicity 8 Bits

INL Integral non‑linearity ±0.12 ±0.5 LSB

DNL Differential non‑linearity 0.03 0.15 LSB

–0.1 –0.02

ZE Zero code error IOUT = 0 5 15 mV

FSE Full-scale error IOUT = 0 –0.1 –0.75 %FSR

GE Gain error –0.2 –1 %FSR

ZCED Zero code error drift –20 µV/°C

TC GE Gain error tempco –1 ppm/°C

OUTPUT CHARACTERISTICS

Output voltage range 0 VREF1,2 V

IOZ High-impedance output

leakage current(1) ±1 µA

ZCO Zero code output

VA= 3 V, IOUT = 200 µA 10

VA= 3 V, IOUT = 1 mA 45

VA= 5 V, IOUT = 200 µA 8

VA= 5 V, IOUT = 1 mA 34

FSO Full scale output

VA= 3 V, IOUT = 200 µA 2.984

VA= 3 V, IOUT = 1 mA 2.933

VA= 5 V, IOUT = 200 µA 4.987

VA= 5 V, IOUT = 1 mA 4.955

IOS Output short circuit current

(source) VA= 3 V, VOUT = 0 V, Input Code = FFh –50 mA

VA= 5 V, VOUT = 0 V, Input Code = FFh –60

IOS Output short circuit current

(sink) VA= 3 V, VOUT = 3 V, Input Code = 00h 50 mA

VA= 5 V, VOUT = 5 V, Input Code = 00h 70

IOContinuous output current

per channel(1) TA= 105°C 10 mA

TA= 125°C 6.5

DAC088S085

www.ti.com

SNAS424D –AUGUST 2007–REVISED APRIL 2016

Product Folder Links: DAC088S085

Electrical Characteristics (continued)

The following specifications apply for VA= 2.7 V to 5.5 V, VREF1 = VREF2 = VA, CL= 200 pF to GND, fSCLK = 30 MHz, input

code range 3 to 252. Typical values apply for TA= 25°C; minimum and maximum limits apply for TA= –40°C to 125°C, unless

otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CLMaximum load capacitance RL=∞1500 pF

RL= 2 kΩ1500

ZOUT DC output impedance 8 Ω

REFERENCE INPUT CHARACTERISTICS

VREF1,2 input range 2.7 0.5 VAV

Input impedance 30 kΩ

LOGIC INPUT CHARACTERISTICS

IIN Input Current(1) ±1 µA

VIL Input low voltage VA= 2.7 V to 3.6 V 1 0.6 V

VA= 4.5 V to 5.5 V 1.1 0.8

VIH Input high voltage VA= 2.7 V to 3.6 V 2.1 1.4 V

VA= 4.5 V to 5.5 V 2.4 2

CIN Input Capacitance(1) 3 pF

POWER REQUIREMENTS

VASupply voltage 2.7 5.5 V

Normal supply current for

supply pin VAfSCLK = 30 MHz, output unloaded VA= 2.7 V to 3.6 V 460 575

µA

VA= 4.5 V to 5.5 V 650 840

Normal supply current for

VREF1 or VREF2 fSCLK = 30 MHz, output unloaded VA= 2.7 V to 3.6 V 95 135

VA= 4.5 V to 5.5 V 160 225

IST

Static supply current for

supply pin VAfSCLK = 0, output unloaded VA= 2.7 V to 3.6 V 370

µA

VA= 4.5 V to 5.5 V 440

Static supply current for

VREF1 or VREF2 fSCLK = 0, output unloaded VA= 2.7 V to 3.6 V 95

VA= 4.5 V to 5.5 V 160

IPD Total power down supply

current for all PD Modes(1)

fSCLK = 30 MHz, SYNC = VA, and

DIN = 0 V after PD mode loaded VA= 2.7 V to 3.6 V 0.2 1.5

µA

VA= 4.5 V to 5.5 V 0.5 3

fSCLK = 0, SYNC = VA, and

DIN = 0 V after PD mode loaded VA= 2.7 V to 3.6 V 0.1 1

VA= 4.5 V to 5.5 V 0.2 2

PNTotal power consumption

(output unloaded)

fSCLK = 30 MHz, output unloaded VA= 2.7 V to 3.6 V 1.95 3

VA= 4.5 V to 5.5 V 4.85 7.1

fSCLK = 0, output unloaded VA= 2.7 V to 3.6 V 1.68

VA= 4.5 V to 5.5 V 3.8

PPD Total power consumption in

all PD Modes(1)

fSCLK = 30 MHz, SYNC = VA, and

DIN = 0 V after PD mode loaded VA= 2.7 V to 3.6 V 0.6 5.4

µW

VA= 4.5 V to 5.5 V 2.5 16.5

fSCLK = 0, SYNC = VA, and

DIN = 0 V after PD mode loaded VA= 2.7 V to 3.6 V 0.3 3.6

VA= 4.5 V to 5.5 V 1 11

DB15 DB0

SCLK

DIN

SYNC

tSYNC

tDS

tDH

tCL tCH

1 / fSCLK

tSH

1 2 13 14 15 16

tSS

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

www.ti.com

Product Folder Links: DAC088S085

(1) This parameter is specified by design or characterization and is not tested in production.

7.6 AC and Timing Requirements

Test limits are specified to AOQL (Average Outgoing Quality Level). Typical values apply for TA= 25°C; minimum and

maximum limits apply for TA= –40°C to 125°C, unless otherwise noted. MIN NOM MAX UNIT

fSCLK SCLK frequency 40 30 MHz

tsOutput voltage settling time(1) 40h to C0h code change,

RL= 2 kΩ, CL= 200 pF 3 4.5 µs

SR Output Slew Rate 1 V/µs

GI Glitch Impulse Code change from 80h to 7Fh 40 nV-sec

DF Digital Feedthrough 0.5 nV-sec

DC Digital Crosstalk 0.5 nV-sec

CROSS DAC-to-DAC crosstalk 1 nV-sec

MBW Multiplying bandwidth VREF1,2 = 2.5 V ± 2 VPP 360 kHz

ONSD Output noise spectral density DAC Code = 80h, 10 kHz 40 nV/√(Hz)

ON Output noise BW = 30 kHz 14 µV

tWU Wake-up time VA= 3 V 3 µs

VA= 5 V 20

1/fSCLK SCLK cycle time 33 25 ns

tCH SCLK high time 10 7 ns

tCL SCLK low time 10 7 ns

tSS SYNC set-up time before SCLK falling edge TA= 25°C 3 1/fSCLK – 3 ns

TA= –40°C to 125°C 10

tDS Data set-up time before SCLK falling edge 2.5 1 ns

tDH Data hold time after SCLK falling edge 2.5 1 ns

tSH SYNC hold time after the 16th

falling edge of SCLK TA= 25°C 0 1/fSCLK – 3 ns

TA= –40°C to 125°C 3

tSYNC SYNC high time 15 5 ns

Figure 1. Serial Timing Diagram

OUTPUT

VOLTAGE

DIGITAL INPUT CODE

00 255

FSE

GE = FSE - ZE

FSE = GE + ZE

255 x VA

256

DAC088S085

www.ti.com

SNAS424D –AUGUST 2007–REVISED APRIL 2016

Product Folder Links: DAC088S085

7.7 Typical Characteristics

VA= 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA= 25°C, unless otherwise stated

Figure 2. I/O Transfer Characteristic Figure 3. INL vs Code

Figure 4. DNL vs Code Figure 5. INL and DNL vs VREF

Figure 6. INL and DNL vs fSCLK Figure 7. INL and DNL vs VA

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

www.ti.com

Product Folder Links: DAC088S085

Typical Characteristics (continued)

VA= 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA= 25°C, unless otherwise stated

Figure 8. INL and DNL vs Temperature Figure 9. Zero Code Error vs VA

Figure 10. Zero Code Error vs VREF Figure 11. Zero Code Error vs fSCLK

Figure 12. Zero Code Error vs Temperature Figure 13. Full-Scale Error vs VA

DAC088S085

www.ti.com

SNAS424D –AUGUST 2007–REVISED APRIL 2016

Product Folder Links: DAC088S085

Typical Characteristics (continued)

VA= 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA= 25°C, unless otherwise stated

Figure 14. Full-Scale Error vs VREF Figure 15. Full-Scale Error vs fSCLK

Figure 16. Full-Scale Error vs Temperature Figure 17. IVA vs VA

Figure 18. IVA vs Temperature Figure 19. IVREF vs VREF

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

www.ti.com

Product Folder Links: DAC088S085

Typical Characteristics (continued)

VA= 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA= 25°C, unless otherwise stated

Figure 20. IVREF vs Temperature Figure 21. Settling Time

Figure 22. Glitch Response Figure 23. Wake-Up Time

Figure 24. DAC-to-DAC Crosstalk Figure 25. Power-On Reset

DAC088S085

www.ti.com

SNAS424D –AUGUST 2007–REVISED APRIL 2016

Product Folder Links: DAC088S085

Typical Characteristics (continued)

VA= 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA= 25°C, unless otherwise stated

Figure 26. Multiplying Bandwidth

POWER-ON

RESET

DAC

INPUT

CONTROL

LOGIC

POWER-DOWN

CONTROL

LOGIC

VOUTE

8 BIT DAC

REF

SCLK DIN

SYNC

BUFFER

VOUTF

VOUTG

VOUTH

2.5k 100k

8 BIT DAC

REF

8 BIT DAC

REF

8 BIT DAC

REF

VREF1

DAC088S085

VOUTA

8 BIT DAC

REF

BUFFER

VOUTB

VOUTC

VOUTD

2.5k 100k

8 BIT DAC

REF

8 BIT DAC

REF

8 BIT DAC

REF

VREF2

DOUT

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

www.ti.com

Product Folder Links: DAC088S085

8 Detailed Description

8.1 Overview

The DAC085S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor

strings that are followed by an output buffer.

8.2 Functional Block Diagram

VOUT

8 BIT DAC

REF

8BUFFER

DAC

VREF

VOUT

S2 n

S2 n-1

S2 n-2

DAC088S085

www.ti.com

SNAS424D –AUGUST 2007–REVISED APRIL 2016

Product Folder Links: DAC088S085

8.3 Feature Description

8.3.1 DAC Architecture

The DAC088S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor

strings that are followed by an output buffer. The reference voltages are externally applied at VREF1 for DAC

channels A through D and VREF2 for DAC channels E through H.

For simplicity, a single resistor string is shown in Figure 27. This string consists of 256 equal valued resistors

with a switch at each junction of two resistors, plus a switch-to-ground. The code loaded into the DAC register

determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight

binary with an ideal output voltage of:

VOUTA,B,C,D = VREF1 × (D / 256) (1)

VOUTE,F,G,H = VREF2 × (D / 256)

where

• D is the decimal equivalent of the binary code that is loaded into the DAC register. (2)

D can take on any value between 0 and 255. This configuration ensures that the DAC is monotonic.

Figure 27. DAC Resistor String

Because all eight DAC channels of the DAC088S085 can be controlled independently, each channel consists of

a DAC register and a 8-bit DAC. Figure 28 is a simple block diagram of an individual channel in the

DAC088S085. Depending on the mode of operation, data written into a DAC register causes the 8-bit DAC

output to be updated or an additional command is required to update the DAC output. Further description of the

modes of operation can be found in Serial Interface.

Figure 28. Single-Channel Block Diagram

DAC088S085

SNAS424D –AUGUST 2007–REVISED APRIL 2016

www.ti.com

Product Folder Links: DAC088S085

Feature Description (continued)

8.3.2 Output Amplifiers

The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to VAwhen the reference is VA. All

amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA,

in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the

reference is less than VA, there is only a loss in linearity in the lowest codes.

The output amplifiers are capable of driving a load of 2 kΩin parallel with 1500 pF to ground or to VA. The zero-

code and full-scale outputs for given load currents are available in Electrical Characteristics.

8.3.3 Reference Voltage

The DAC088S085 uses dual external references, VREF1 and VREF2, that are shared by channels A, B, C, D and

channels E, F, G, H respectively. The reference pins are not buffered and have an input impedance of 30 kΩ. TI

recommends that VREF1 and VREF2 be driven by voltage sources with low output impedance. The reference

voltage range is 0.5 V to VA, providing the widest possible output dynamic range.

8.4 Device Functional Modes

8.4.1 Power-On Reset

The power-on reset circuit controls the output voltages of the eight DACs during power up. Upon application of

power, the DAC registers are filled with zeros and the output voltages are set to 0 V. The outputs remain at 0 V

until a valid write sequence is made.

8.4.2 Power-Down Modes

The DAC088S085 has three power-down modes where different output terminations can be selected (see

Table 1). With all channels powered down, the supply current drops to 0.1 µA at 3 V and 0.2 µA at 5 V. By

selecting the channels to be powered down in DB[7:0] with a 1, individual channels can be powered down

separately or multiple channels can be powered down simultaneously. The three different output terminations

include high output impedance, 100 kΩto GND, and 2.5 kΩto GND.

The output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down

modes. The bias generator, however, is only shut down if all the channels are placed in power down mode. The

contents of the DAC registers are unaffected when in power down. Therefore, each DAC register maintains its

value before the DAC088S085 being powered down unless it is changed during the write sequence which

instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with

SYNC idled high, DIN idled low, and SCLK disabled. The time to exit power-down (Wake-Up Time) is typically 3

µs at 3 V and 20 µs at 5 V.

Table 1. Power-Down Modes

DB[15:12] DB[11:8] 7 6 5 4 3 2 1 0 OUTPUT IMPEDANCE

1 1 0 1 X X X X H G F E D C B A High-Z outputs

1 1 1 0 X X X X H G F E D C B A 100-kΩoutputs

1 1 1 1 X X X X H G F E D C B A 2.5-kΩoutputs

DAC 1

SCLK

DIN

SYNC

DOUT

DAC 2

SCLK

DIN

SYNC

DOUT

DAC 3

SCLK

DIN

SYNC

DOUT

SCLK

DIN

SYNC

SCLK

SYNC

tSS

117

tSH

1615

DAC088S085

www.ti.com

SNAS424D –AUGUST 2007–REVISED APRIL 2016

Product Folder Links: DAC088S085

8.5 Programming

8.5.1 Serial Interface

The three-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs and operates at

clock rates up to 40 MHz. A valid serial frame contains 16 falling edges of SCLK. See Figure 1 for information on

a write sequence.

A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked

into the 16-bit serial input register on the falling edges of SCLK. To avoid mis-clocking data into the shift register,

it is critical that SYNC not be brought low on a falling edge of SCLK (see minimum and maximum setup times for

SYNC in Figure 1 and Figure 29). On the 16th falling edge of SCLK, the last data bit is clocked into the register.

The write sequence is concluded by bringing the SYNC line high. Once SYNC is high, the programmed function