TPS7A69xx-Q1
81
5
6
2
V(reg)
4
V(bat)
7
Vout
GND
PG
SO
Vin
SI
CT
V(reg)
GND
CT
TPS7A66xx-Q1
8
1
6
2
V(bat) Vout
PG
Vin
EN
4 5
Product
Folder
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Technical
Documents
Tools &
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Support &
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TPS7A6xxx-Q1 High-Voltage Ultralow-I
(q)
Low-Dropout Regulator
1 Features 2 Applications
1• Qualified for Automotive Applications • Infotainment Systems With Sleep Mode
• AEC-Q100 Qualified With the Following Results: • Body Control Modules
• Always-On Battery Applications
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range – Gateway Applications
– Device HBM ESD Classification Level H2 – Remote Keyless Entry Systems
– Device CDM ESD Classification Level C4 – Immobilizers
• 4-V to 40-V Wide Vin Input Voltage Range With 3 Description
up to 45-V Transient The TPS7A66xx-Q1 and TPS7A69xx-Q1 are low-
• Output Current 150 mA dropout linear regulators designed for up to 40-V Vin
• Low Quiescent Current, I(q):operations. With only 12-µA quiescent current at no
– 2 µA when EN = Low (Shutdown Mode) load, they are quite suitable for standby
microprocessor control-unit systems, especially in
– 12 µA Typical at Light Loads automotive applications.
• Low ESR Ceramic Output Stability Capacitor
(2.2 µF–100 µF) The devices feature integrated short-circuit and
overcurrent protection. The devices implement reset
• 300-mV Dropout Voltage at 150 mA delay on power up to indicate the output voltage is
(Typical, V(Vin) = 4 V) stable and in regulation. One can program the delay
• Fixed (3.3-V and 5-V) and Adjustable with an external capacitor. A low-voltage tracking
(1.5-V to 5-V) Output Voltages feature allows for a smaller input capacitor and can
(Adjustable for TPS7A66xx-Q1 Only) possibly eliminate the need of using a boost
• Low Input Voltage Tracking converter during cold-crank conditions.
• Integrated Power-On Reset The devices operate in the –40°C to 125°C
temperature range. These features suit the devices
– Programmable Reset-Pulse Delay well for power supplies in various automotive
– Open-Drain Reset Output applications.
• Integrated Fault Protection
– Thermal Shutdown Device Information(1)
DEVICE NUMBER PACKAGE BODY SIZE (NOM)
– Short-Circuit Protection TPS7A6601-Q1
• Input Voltage Sense Comparator TPS7A6633-Q1 MSOP (8) 3.00 mm × 3.00 mm
(TPS7A69xx-Q1 Only) TPS7A6650-Q1
• Packages TPS7A6933-Q1
– 8-Pin SOIC-D for TPS7A69xx-Q1 SOIC (8) 4.90 mm × 3.91 mm
TPS7A6950-Q1
– 8-Pin MSOP-DGN for TPS7A66xx-Q1 (1) For all available packages, see the orderable addendum at
the end of the datasheet.
Hardware-Enable Option Input-Voltage-Sensing Option
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.3 Feature Description................................................. 11
1 Features.................................................................. 17.4 Device Functional Modes........................................ 15
2 Applications ........................................................... 18 Application and Implementation ........................ 16
3 Description............................................................. 18.1 Application Information............................................ 16
4 Revision History..................................................... 28.2 Typical Applications ................................................ 16
5 Pin Configuration and Functions......................... 49 Power Supply Recommendations...................... 19
6 Specifications......................................................... 410 Layout................................................................... 19
6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 19
6.2 Handling Ratings....................................................... 510.2 Layout Examples................................................... 19
6.3 Recommended Operating Conditions....................... 510.3 Power Dissipation and Thermal Considerations... 20
6.4 Thermal Information.................................................. 511 Device and Documentation Support................. 21
6.5 Electrical Characteristics........................................... 611.1 Related Links ........................................................ 21
6.6 Switching Characteristics.......................................... 711.2 Trademarks........................................................... 21
6.7 Typical Characteristics.............................................. 711.3 Electrostatic Discharge Caution............................ 21
7 Detailed Description............................................ 10 11.4 Glossary................................................................ 21
7.1 Overview................................................................. 10 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagrams ..................................... 10 Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2014) to Revision E Page
• Corrected voltage unit in Handling Ratings table from V to kV ............................................................................................. 5
Changes from Revision C (December 2013) to Revision D Page
• Changed CDM ESC classification level ................................................................................................................................ 1
• Changed FB/NC pin to FB/NU in Pin Functions table. Added NC and NU notes to pinout drawings .................................. 4
• Removed ESD and Tstg specifications from the Absolute Maximum Ratings table ............................................................... 4
• Added Handling Ratings table ............................................................................................................................................... 5
• Numerous changes throughout the Electrical Characteristics table ...................................................................................... 6
• Added Switching Characterisitcs table................................................................................................................................... 7
• Moved an oscilloscope trace to the Applications Information section ................................................................................... 9
• Changed de-glitch time in Power-On Reset (PG) section ................................................................................................... 12
• Changed reset delay timer default delay to 290 µs from 150 µs ........................................................................................ 12
• Changed voltage at which Power-on reset initializes to 91.6% of V(Vout) ............................................................................ 12
• Changed selectable output voltage range and calculation for FB resistor divideer............................................................. 13
Changes from Revision B (August 2013) to Revision C Page
• Corrected part number in the Description section by adding -Q1.......................................................................................... 1
• Changed Operating ambient temperature to Operating junction temperature....................................................................... 4
• Added PSRR graph to Typical Characteristics....................................................................................................................... 8
• Deleted a paragraph from the Thermal Protection section................................................................................................... 14
Changes from Revision A (March 2013) to Revision B Page
• Added two conditions to Vdropout in the Electrical Characteristics table .................................................................................. 6
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Changes from Original (December 2012) to Revision A Page
• Deleted the ORDERING INFORMATION table...................................................................................................................... 4
• Changed From: TAOperating ambient temperature range –40 to 125°C To: TJOperating ambient temperature
range –40 to 150°C ................................................................................................................................................................ 4
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1
2
3
4
8
7
6
5
Vin
EN
NC
CT
Vout
FB/NU
PG
GND
NC - No internal connection
NU - Make no external connection
Vin
SI
NC
CT
Vout
SO
PG
GND
1
2
3
4
8
7
6
5
NC - No internal connection
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5 Pin Configuration and Functions
8-Pin SOIC (TPS7A69xx-Q1) 8-Pin MSOP (TPS7A66xx-Q1)
D Package DGN Package
(Top View) (Top View)
Pin Functions
PIN NO.
PIN TYPE DESCRIPTION
NAME SOIC-D MSOP-DGN
CT 4 4 O Reset-pulse delay adjustment. Connecting this pin via a capacitor to GND
Enable pin. The device enters the standby state when the enable pin becomes lower
EN 2 I than the threshold.
Feedback pin when using external resistor divider or NU pin when using internal resistor
FB/NU 7 I divider
GND 5 5 G Ground reference
NC 3 3 — Not-connected pin
Output ready. This open-drain pin must connect to Vout via an external resistor. The
PG 6 6 O output voltage going below threshold pulls it down.
Sense input pin to supervise input voltage. Connect via an external voltage divider to Vin
SI 2 I and GND
Sense output. This open-drain pin must connect to Vout via an external resistor. The SI
SO 7 O voltage becoming lower than the threshold pulls it down.
Vin 1 1 P Input power-supply voltage
Vout 8 8 O Output voltage
— — Thermal pad for MSOP-DGN package
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Vin, EN Unregulated input(2) (3) –0.3 45 V
Vout Regulated output –0.3 7 V
SI See (2) –0.3 Vin V
CT –0.3 25 V
FB, SO, PG –0.3 Vout V
TJOperating junction temperature range –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND
(3) Absolute maximum voltage, withstand 45 V for 200 ms
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6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per AEC Q100-002(1) 0 4
Corner pins (1, 4, 5, 0 1
V(ESD) Electrostatic discharge kV
Charged device model (CDM), per and 8)
AEC Q100-011 Other pins 0 1
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
spacer
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Vin Unregulated input 4 40 V
EN, SI 0 40 V
CT 0 20 V
Vout 1.5 5.5 V
PG, SO, FB Low voltage (I/O) 0 5.5 V
TJOperating junction temperature –40 150 °C
6.4 Thermal Information TPS7A66xx-Q1 TPS7A69xx-Q1
THERMAL METRIC(1) UNIT
MSOP (8 PINS) SOIC (8 PINS)
RθJA Junction-to-ambient thermal resistance 63.4 113.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.0 59.6 °C/W
RθJB Junction-to-board thermal resistance(2) 37.4 59.57 °C/W
ψJT Junction-to-top characterization parameter 3.7 12.8 °C/W
ψJB Junction-to-board characterization parameter 37.1 52.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 13.5 NA °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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6.5 Electrical Characteristics
V(Vin) = 14 V, 1 mΩ< ESR < 2 Ω, TJ= –40°C to 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (Vin)
Fixed 5-V output, IO= 1 mA 5.5 40 V
V(Vin) Input voltage Fixed 3.3-V output, IO= 1 mA 4 40 V
I(q) Quiescent current V(Vin) = 5.5 V to 40 V, EN = ON, IO= 0.2 mA 12 20 µA
I(Sleep) Input sleep current No load current and EN = OFF 4 µA
I(EN) EN pin current V(EN) = 40 V 1 µA
V(bg) Band gap Reference voltage for FB 1.199 1.223 1.247 V
V(VinUVLO) Undervoltage detection Ramp V(Vin) down until output turns OFF 2.6 V
V(UVLOhys) Undervoltage hysteresis 1 V
ENABLE INPUT (EN)
VIL Logic input low level 0 0.4 V
VIH Logic input high level 1.7 V
REGULATED OUTPUT (Vout)
IO= 1 mA, TJ= 25°C –1% 1%
V(Vin) = 6 V to 40 V, IO= 1 mA to 150 mA, fixed 5-V version –2% 2%
V(Vout) Regulated output V(Vin) = 4 V to 40 V, IO= 1 mA to 150 mA, fixed 3.3-V version –2% 2%
V(Vin) = V(Vout) + 0.45 V and Vin ≥4 V, IO= 1 mA to 150 mA, –2% 2%
adjustable version(1)
V(line-reg) Line regulation V(Vin) = 5.5 V to 40 V, IO= 50 mA 5 mV
V(load-reg) Load regulation IO= 1 mA to 150 mA 20 mV
V(dropout) = V(Vin) – V(Vout), IOUT = 80 mA 180 240
V(Vin) – V(Vout), IOUT = 150 mA 300 450
V(dropout) Dropout voltage mV
V(Vin) = 3 V, V(dropout) = V(Vin) – V(Vout), IO= 5 mA 12 27.5 58
V(Vin) = 3 V, V(dropout) = V(Vin) – V(Vout), IO= 30 mA 44 80 145
IOOutput current V(Vout) in regulation 0 150 mA
I(lreg-CL) Output current limit V(Vout) short to ground 500 800 mA
V(Vin) = 12 V, IL= 10 mA, output capacitance = 2.2 µF
PSRR Power supply ripple rejection(2) Frequency = 100 Hz 60 dB
Frequency = 100 kHz 40 dB
VOLTAGE SENSING PRE-WARNING
VI(S-th) Sense low threshold V(SI) decreasing 1.089 1.123 1.157 V
VI(S-th,hys) Sense threshold hysteresis 50 100 150 mV
VOL(S) Sense output low voltage (V(SI) ≤1.06 V, V(Vin) ≥4 V, R(SO) = 10 kΩto V(Vout) 0.4 V
IOH(S) Sense output leakage (V(SO) = 5 V, V(SI) ≥1.5 V) 1 µA
II(S) Sense input current –1 0.1 1 µA
RESET (PG)
VOL Reset output, low voltage IOL = 0.5 mA 0.4 V
Ilkg Leakage current Reset pulled Vout through 10-kΩresistor 1 µA
V(TH-POR) Power-on-reset threshold V(Vout) increasing 89.6 91.6 93.6 % of Vout
V(Thres) Hysteresis 2 % of Vout
RESET DELAY (CT)
I(Chg) Delay-capacitor charging current V(CT) = 0 V 1.4 µA
V(th) Threshold to release PG high 1 V
OPERATING TEMPERATURE RANGE
TJJunction temperature –40 150 °C
T(shutdown) Junction shutdown temperature 175 °C
T(hyst) Hysteresis of thermal shutdown 20 °C
(1) Adjustable version with precision external feedback resistor with tolerance of less than ±1%.
(2) Design information – Not tested
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IGND (A)
Output Current (mA)
T = ±40C
T = 25C
T = 125C
C003
Quiescent Current (A)
Input Voltage (V)
T = ±40C
T = 25C
T = 125C
C004
Nominal Output Voltage (%)
Temperature (C)
PG Rising
PG Falling
C001
Nominal Output Voltage (%)
Input Voltage (V)
T = ±40C
T = 25C
T = 125C
C002
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(SDeglitch,rise) SI or SO rising deglitch time 50 260 µs
t(SDeglitch,drop) SI or SO falling deglitch time 30 240 µs
TIMING FOR RESET (PG)
Where C = delay capacitor value; capacitance
t(POR) 50 100 180 ms
C = 100 nF(1)
Power-on-reset delay
t(POR-fixed) No capacitor on pin 100 290 650 µs
t(Deglitch) Reset deglitch time 20 250 µs
(1) This information only is not tested in production and equation basis is (C × 1) / 1 × 10–6 = td(delay time).
Where C = Delay capacitor value. Capacitance C range = 100 pF to 100 nF.
6.7 Typical Characteristics
Figure 1. Power-Good Threshold Voltage vs Temperature Figure 2. Line Regulation (Vin = 14 V, IL= 1 mA)
(Vin = 14 V, No Load)
Figure 3. Ground Current vs Output Current (Vin = 14 V) Figure 4. Quiescent Current vs Input Voltage (IL= 0)
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10 100 1k 10k 100k 1M 10M 100M
±20
0
20
40
60
80
100
120
PSRR (dB)
Frequency (Hz)
C010
CLOAD (F)
ESR of Cout ()
C009
0.001
2.2
Stable Region
Output Voltage (V)
Supply Voltage (V)
C007
Output Voltage (V)
Supply Voltage (V)
C008
Nominal Output Voltage (%)
Output Current (mA)
T = ±40C
T = 25C
T = 125C
C005
Dropout Voltage (mV)
Output Current (mA)
T = ±40C
T = 25C
T = 125C
C006
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Typical Characteristics (continued)
Figure 5. Load Regulation (Vin = 14 V) Figure 6. Dropout Voltage vs Output Current (Vin = 4 V)
Figure 7. Output Voltage vs Supply Voltage (Fixed 5-V Figure 8. Output Voltage vs Supply Voltage (Fixed 3.3-V
Version, IL= 0) Version, IL= 0)
Figure 9. Load Capacitance vs ESR Stability Figure 10. Power-Supply Rejection Ratio vs Frequency
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Typical Characteristics (continued)
All oscilloscope waveforms were taken at room temperature.
Figure 11. Load Transient Response, 10 ms/div Figure 12. Load Transient Response, 10 ms/div
Figure 13. Line Transient Response, IL= 1 mA, 1 V/µs Figure 14. Line Transient Response, IL= 10 mA, 1 V/µs
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8 V(reg)
4.7 Fμ
GND
CT
Band Gap
+
+
Vref(1)
Vref1
Vref(3)
6
10 kΩ
1V(bat)
22 μF 0.1 Fμ
PG
Vout
Vin
2EN
Reset
Control
Regulator
Control
Overcurrent
Detection
UVLO
Comp
Thermal
Shutdown
Logic
Control
5
4
V(reg)
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7 Detailed Description
7.1 Overview
This product is a combination of a low-dropout linear regulator with reset function. The power-on reset initializes
once the Vout output exceeds 91.6% of the target value. The power-on-reset delay is a function of the value set
by an external capacitor on the CT pin before releasing the PG pin high.
7.2 Functional Block Diagrams
Figure 15. TPS7A66xx-Q1 Functional Block Diagram
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8 V(reg)
4.7 Fμ
GND
CT
Band Gap
+
+
+
Vref(1)
Vref3
6
10 kΩ
V(reg)
1 V(bat)
22 μF 0.1 Fμ
PG
Vout
Vin
Reset
Control
Regulator
Control
Overcurrent
Detection
UVLO
Comp
Thermal
Shutdown
Logic
Control
5
4
7
10 kΩ
SO
2
SI
V(reg)
Vref(1)
Vref(1)
V(bat)
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Functional Block Diagrams (continued)
Figure 16. TPS7A69xx-Q1 Functional Block Diagram
7.3 Feature Description
7.3.1 Enable (EN)
This is a high-voltage-tolerant pin; high input activates the device and turns the regulator ON. One can connect
this input to the Vin pin for self-bias applications.
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V(Thres)
VTH(POR)
t < t(Deglitch)
Vin
Vout
PG
CT
t(Deglitch)
Vth)(
t(POR)
t(Deglitch)
t(POR)
V(th)
(CT)
(POR)
C 1 V
t1 A
´
=
m
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Feature Description (continued)
7.3.2 Regulated Output (Vout)
This is the regulated output based on the required voltage. The output has current limitation. During initial power
up, the regulator has a soft start incorporated to control initial current through the pass element and the output
capacitor.
In the event the regulator drops out of regulation, the output tracks the input minus a drop based on the load
current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage
recovers above the minimum start-up level.
7.3.3 Power-On Reset (PG)
This is an output with an external pullup resistor to the regulated supply. The output remains low until the
regulated Vout has exceeded approximately 90% of the set value and the power-on-reset delay has expired. The
on-chip oscillator presets the delay. The regulated output falling below the 90% level asserts this output low after
a short de-glitch time of approximately 250 µs (typical).
7.3.4 Reset Delay Timer (CT)
An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output
current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this
pin is open, the default delay time is 290 µs (typ). After releasing the PG pin high, the capacitor on this pin
discharges, thus allowing the capacitor to charge from approximately 0.2 V for the next power-on-reset delay-
timer function.
An external capacitor, CT, defines the reset-pulse delay time, t(POR), with the charge time of:
(1)
The power-on reset initializes once the output V(Vout) exceeds 91.6% of the programmed value. The power-on-
reset delay is a function of the value set by an external capacitor on the CT pin before the releasing of the PG
pin high.
Figure 17. Conditions for Activation of Reset
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(Vout) (FB)
R1
V V 1 R2
æ ö
= ´ +
ç ÷
è ø
t(POR)
0.9 × V(th)
V(th)
Vin
Vout
CT
PG
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SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
Feature Description (continued)
Figure 18. External Programmable Reset Delay
7.3.5 Sense Comparator (SI and SO for TPS7A69xx-Q1)
The sense comparator compares the input signal with an internal voltage reference of 1.223 V for rising and
1.123 V for falling threshold. The use of an external voltage divider makes this comparator very flexible in the
application.
The device can supervise the input voltage either before or after the protection diode and give additional
information to the microprocessor, like low-voltage warnings.
The regulator operates in low-power mode when the output load is below 2 mA (typical, 1-mA to 10-mA range).
In this mode, the regulator output tolerance is approximately V(Vout) ± 1%.
7.3.6 Adjustable Output Voltage (FB for TPS7A6601-Q1)
One can select an output voltage between 1.5 V and 5 V by using an external resistor divider. Calculate the
output voltage using the following equation, where V(FB) = 1.223 V. The recommendation for R1 and R2 is that
both be less than 100 kΩ.
(2)
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
TPS7A6601-Q1
81
5
6
2
V(reg)
C2
R3
4
V(bat)
7
R1
R2
C1
C3
Vout
GND
PG
FB/NU
Vin
EN
CT
TPS7A6601-Q1
,
TPS7A6633-Q1
TPS7A6650-Q1
,
TPS7A6933-Q1
,
TPS7A6950-Q1
SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
www.ti.com
Feature Description (continued)
Figure 19. External Feedback Resistor Divider
7.3.7 Undervoltage Shutdown
There is an internally fixed undervoltage shutdown threshold. Undervoltage shutdown activates when the input
voltage on Vin drops below V(VinUVLO). This ensures the regulator is not latched into an unknown state during low
input supply voltage. If the input voltage has a negative transient which drops below the UVLO threshold and
recovers, the regulator shuts down and powers up with a normal power-up sequence once the input voltage is
above the required levels.
7.3.8 Low-Voltage Tracking
At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage
based on the load current (IO) and switch resistance (R(SW)). This allows for a smaller input capacitor and can
possibly eliminate the need of using a boost convertor during cold-crank conditions.
7.3.9 Thermal Shutdown
These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point, the
output turns on again.
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. Cooling of the junction temperature to approximately 150°C enables the output circuitry.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
The purpose of the design of the internal protection circuitry of the TPS7A66/69xx-Q1 is for protection against
overload conditions, not as a replacement for proper heat-sinking. Continuously running the TPS7A66xx-Q1 or
TPS7A69xx-Q1 into thermal shutdown degrades device reliability.
14 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
TPS7A6601-Q1
,
TPS7A6633-Q1
TPS7A6650-Q1
,
TPS7A6933-Q1
,
TPS7A6950-Q1
www.ti.com
SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
7.4 Device Functional Modes
7.4.1 Operation With V(VIN) < 4 V
The devices operate with input voltages above 4 V. The maximum UVLO voltage is 2.6 V, and the devices
operate at an input voltage above 4 V. The devices can also operate at lower input voltages; no minimum UVLO
voltage is specified. At input voltages below the actual UVLO voltage, the devices do not operate.
7.4.2 Operation With EN Control (TPS7A66xx-Q1)
The enable rising edge threshold voltage is 1.7 V (maximum). With the EN pin held above that voltage and the
input voltage above 4 V, the device becomes active. The enable falling edge is 0.4 V (minimum). Holding the EN
pin below that voltage disables the device, thus reducing the IC quiescent current.
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
TPS7A66xx-Q1
81
5
6
2
V(reg)
2.2 μF
10 kΩ
4
V(bat)
1 μF
1 nF
Vout
GND
PG
Vin
EN
CT
TPS7A6601-Q1
,
TPS7A6633-Q1
TPS7A6650-Q1
,
TPS7A6933-Q1
,
TPS7A6950-Q1
SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A66xx-Q1 and TPS7A69xx-Q1 devices are 150-mA low-dropout linear regulators designed for up to
40-V Vin operation with only 12 µA quiescent current at no load. One can use the Pspice transient model, which
is downloadable from the product folder (see Related Links), for evaluating the base function of the devices. in
addition, there are specific EVMs designed for these devices. Both the EVM and its user guide are available on
the product folder as well.
8.2 Typical Applications
Figure 20 and Figure 22 show typical application circuits for the TPS7A66xx-Q1 and TPS7A69xx-Q1,
respectively. One may use different values of external components, depending on the end application. An
application may require a larger output capacitor during fast load steps in order to prevent reset from occurring.
TI recommends a low-ESR ceramic capacitor with dielectric of type X5R or X7R.
8.2.1 TPS7A66xx-Q1 Typical Application
Figure 20. Typical Application Schematic for TPS7A66xx-Q1
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the design parameters.
Table 1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 4 V to 40 V
Output voltage 3.3 V
Output current rating 150 mA
Output capacitor range 2.2 µF to 100 µF
Output capacitor ESR range 1 mΩto 2 Ω
CT capacitor range 100 pF to 100 nF
16 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
TPS7A69xx-Q1
81
5
6
2
V(reg)
2.2 μF
10 kΩ
4
V(bat)
7
10 kΩ
1 μF
1 nF
Vout
GND
PG
SO
Vin
SI
CT
2.2 μF
R3
R4
TPS7A6601-Q1
,
TPS7A6633-Q1
TPS7A6650-Q1
,
TPS7A6933-Q1
,
TPS7A6950-Q1
www.ti.com
SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
8.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
• Output voltage
• Output current rating
• Input capacitor
• Output capacitor
• Power-up-reset delay time
8.2.1.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 10 µF. The voltage rating must be greater than the maximum
input voltage.
8.2.1.2.2 Output Capacitor
The device requires an output capacitor to stablize the output voltage. The capacitor value should be between
2.2 µF and 100 µF. The ESR range should be between 1 mΩand 2 Ω. TI recommends to selecting a ceramic
capacitor with low ESR to improve the load transient response.
8.2.1.3 Application Performance Plots
Figure 21. Power Up (5 V), 20 ms/div, IL= 20 mA
8.2.2 TPS7A69xx-Q1 Typical Application
Figure 22. Typical Application Schematic for TPS7A69xx-Q1
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
(LT)
V
R3 1
R4 1.223
= -
TPS7A6601-Q1
,
TPS7A6633-Q1
TPS7A6650-Q1
,
TPS7A6933-Q1
,
TPS7A6950-Q1
SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
www.ti.com
8.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 4 V to 40 V
Output voltage 3.3 V
Output current rating 150 mA
Output capacitor range 2.2 µF to 100 µF
Output capacitor ESR range 1 mΩto 2 Ω
CT capacitor range 100 pF to 100 nF
Low-voltage tracking threshold 6 V to 9 V
8.2.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
• Output voltage
• Output current rating
• Input capacitor
• Output capacitor
• Power-up-reset delay time
• Low-voltage tracking threshold
8.2.2.2.1 Low-Voltage Tracking Threshold
After determining the low-voltage tracking threshold, calculate the ratio of the resistor divider connected to Vin,
SI, and GND by the following equation:
(3)
TI recommends that the values of both R3 and R4 be less than 100 kΩ.
8.2.2.3 Application Performance Plots
Figure 23. Power Up (5 V), 20 ms/div, IL= 20 mA
18 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
Power Ground
Vin
EN
NC
CT
Vout
FB/NU
PG
GND
TPS7A6601-Q1
,
TPS7A6633-Q1
TPS7A6650-Q1
,
TPS7A6933-Q1
,
TPS7A6950-Q1
www.ti.com
SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
9 Power Supply Recommendations
Design of the device is for operation from an input voltage supply with a range between 4 V and 28 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7A66xx-Q1 or
TPS7A69xx-Q1 device, TI recommends adding an electrolytic capacitor with a value of 22 µF and a ceramic
bypass capacitor at the input.
10 Layout
10.1 Layout Guidelines
The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple
undesirable signals from nearby components (especially from logic and digital ICs, such as microcontrollers and
microprocessors); these capacitive-coupled signals may produce undesirable output voltage transients. In these
cases, TI recommends the use of a fixed-voltage version of the TPS7A66xx-Q1, or isolation of the FB node by
flooding the local PCB area with ground-plane copper to minimize any undesirable signal coupling.
10.1.1 Package Mounting
Solder pad footprint recommendations for the TPS7A66xx-Q1 and TPS7A69xx-Q1 are available at the end of
this product data sheet and at www.ti.com.
10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
For the layout of TPS7A66xx-Q1 and TPS7A69xx-Q1, place the input and output capacitors close to the devices
as shown in Figure 24 and Figure 25, respectively. In order to enhance the thermal performance, TI recommends
surrounding the device with some vias.
To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for Vin and Vout, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of
the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place every capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces because they may impact system performance negatively
and even cause instability.
If possible, and to ensure the maximum performance specified in this product data sheet, use the same layout
pattern used for the TPS7A66xx-Q1 and TPS7A69xx-Q1 evaluation board, available at www.ti.com.
10.2 Layout Examples
Figure 24. TPS7A66xx-Q1 Board Layout Diagram
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
J A JA D)
T T T (R P )
q
D = - = ´
J A JA D)
T T (R P )
q
= + ´
D O (Vin) (Vout) (q) (Vin)
P I (V V ) I V= ´ - + ´
Power Ground
Vin
SI
NC
CT
Vout
SO
PG
GND
TPS7A6601-Q1
,
TPS7A6633-Q1
TPS7A6650-Q1
,
TPS7A6933-Q1
,
TPS7A6950-Q1
SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
www.ti.com
Layout Examples (continued)
Figure 25. TPS7A69xx-Q1 Board Layout Diagram
10.3 Power Dissipation and Thermal Considerations
Calculate power dissipated in the device using Equation 4.
space
(4)
where:
PD= continuous power dissipation
IO= output current
V(Vin) = input voltage
V(Vout) = output voltage
As I(q) << IO, therefore ignore the term I(q) × V(Vin) in Equation 4.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ)
using Equation 5.
space
(5)
where:
RθJA = junction-to-ambient air thermal impedance
space
(6)
20 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
TPS7A6601-Q1
,
TPS7A6633-Q1
TPS7A6650-Q1
,
TPS7A6933-Q1
,
TPS7A6950-Q1
www.ti.com
SLVSBL0E –DECEMBER 2012–REVISED NOVEMBER 2014
11 Device and Documentation Support
11.1 Related Links
The table below lists quick-access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
TECHNICAL TOOLS & SUPPORT &
PART PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TPS7A6601-Q1 Click here Click here Click here Click here Click here
TPS7A6633-Q1 Click here Click here Click here Click here Click here
TPS7A6650-Q1 Click here Click here Click here Click here Click here
TPS7A6933-Q1 Click here Click here Click here Click here Click here
TPS7A6950-Q1 Click here Click here Click here Click here Click here
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 7-Nov-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS7A6601QDGNRQ1 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA4Q
TPS7A6633QDGNRQ1 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA2Q
TPS7A6650QDGNRQ1 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA1Q
TPS7A6933QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 6933
TPS7A6950QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 6950
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Nov-2014
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS7A6601QDGNRQ1 MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS7A6633QDGNRQ1 MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS7A6650QDGNRQ1 MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS7A6933QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7A6950QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Nov-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A6601QDGNRQ1 MSOP-PowerPAD DGN 8 2500 366.0 364.0 50.0
TPS7A6633QDGNRQ1 MSOP-PowerPAD DGN 8 2500 366.0 364.0 50.0
TPS7A6650QDGNRQ1 MSOP-PowerPAD DGN 8 2500 366.0 364.0 50.0
TPS7A6933QDRQ1 SOIC D 8 2500 367.0 367.0 35.0
TPS7A6950QDRQ1 SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Nov-2014
Pack Materials-Page 2
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