Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 TPS7A6xxx-Q1 High-Voltage Ultralow-I(q) Low-Dropout Regulator 1 Features 2 Applications * * * * * 1 * * * * * * * * * * * Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature Range - Device HBM ESD Classification Level H2 - Device CDM ESD Classification Level C4 4-V to 40-V Wide Vin Input Voltage Range With up to 45-V Transient Output Current 150 mA Low Quiescent Current, I(q): - 2 A when EN = Low (Shutdown Mode) - 12 A Typical at Light Loads Low ESR Ceramic Output Stability Capacitor (2.2 F-100 F) 300-mV Dropout Voltage at 150 mA (Typical, V(Vin) = 4 V) Fixed (3.3-V and 5-V) and Adjustable (1.5-V to 5-V) Output Voltages (Adjustable for TPS7A66xx-Q1 Only) Low Input Voltage Tracking Integrated Power-On Reset - Programmable Reset-Pulse Delay - Open-Drain Reset Output Integrated Fault Protection - Thermal Shutdown - Short-Circuit Protection Input Voltage Sense Comparator (TPS7A69xx-Q1 Only) Packages - 8-Pin SOIC-D for TPS7A69xx-Q1 - 8-Pin MSOP-DGN for TPS7A66xx-Q1 Infotainment Systems With Sleep Mode Body Control Modules Always-On Battery Applications - Gateway Applications - Remote Keyless Entry Systems - Immobilizers 3 Description The TPS7A66xx-Q1 and TPS7A69xx-Q1 are lowdropout linear regulators designed for up to 40-V Vin operations. With only 12-A quiescent current at no load, they are quite suitable for standby microprocessor control-unit systems, especially in automotive applications. The devices feature integrated short-circuit and overcurrent protection. The devices implement reset delay on power up to indicate the output voltage is stable and in regulation. One can program the delay with an external capacitor. A low-voltage tracking feature allows for a smaller input capacitor and can possibly eliminate the need of using a boost converter during cold-crank conditions. The devices operate in the -40C to 125C temperature range. These features suit the devices well for power supplies in various automotive applications. Device Information (1) DEVICE NUMBER TPS7A6633-Q1 BODY SIZE (NOM) MSOP (8) 3.00 mm x 3.00 mm SOIC (8) 4.90 mm x 3.91 mm TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 (1) For all available packages, see the orderable addendum at the end of the datasheet. Hardware-Enable Option V(bat) PACKAGE TPS7A6601-Q1 Input-Voltage-Sensing Option TPS7A66xx-Q1 1 Vin Vout 8 2 EN PG 6 4 CT GND 5 V(reg) V(bat) TPS7A69xx-Q1 1 Vin 2 SI 4 CT Vout 8 SO 7 PG 6 GND 5 V(reg) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 5 5 5 6 7 7 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagrams ..................................... 10 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Applications ................................................ 16 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 19 10.1 Layout Guidelines ................................................. 19 10.2 Layout Examples................................................... 19 10.3 Power Dissipation and Thermal Considerations ... 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2014) to Revision E * Page Corrected voltage unit in Handling Ratings table from V to kV ............................................................................................. 5 Changes from Revision C (December 2013) to Revision D Page * Changed CDM ESC classification level ................................................................................................................................ 1 * Changed FB/NC pin to FB/NU in Pin Functions table. Added NC and NU notes to pinout drawings .................................. 4 * Removed ESD and Tstg specifications from the Absolute Maximum Ratings table ............................................................... 4 * Added Handling Ratings table ............................................................................................................................................... 5 * Numerous changes throughout the Electrical Characteristics table ...................................................................................... 6 * Added Switching Characterisitcs table ................................................................................................................................... 7 * Moved an oscilloscope trace to the Applications Information section ................................................................................... 9 * Changed de-glitch time in Power-On Reset (PG) section ................................................................................................... 12 * Changed reset delay timer default delay to 290 s from 150 s ........................................................................................ 12 * Changed voltage at which Power-on reset initializes to 91.6% of V(Vout) ............................................................................ 12 * Changed selectable output voltage range and calculation for FB resistor divideer ............................................................. 13 Changes from Revision B (August 2013) to Revision C Page * Corrected part number in the Description section by adding -Q1 .......................................................................................... 1 * Changed Operating ambient temperature to Operating junction temperature ....................................................................... 4 * Added PSRR graph to Typical Characteristics....................................................................................................................... 8 * Deleted a paragraph from the Thermal Protection section................................................................................................... 14 Changes from Revision A (March 2013) to Revision B * 2 Page Added two conditions to Vdropout in the Electrical Characteristics table .................................................................................. 6 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 Changes from Original (December 2012) to Revision A Page * Deleted the ORDERING INFORMATION table...................................................................................................................... 4 * Changed From: TA Operating ambient temperature range -40 to 125C To: TJ Operating ambient temperature range -40 to 150C ................................................................................................................................................................ 4 Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 3 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com 5 Pin Configuration and Functions 8-Pin SOIC (TPS7A69xx-Q1) D Package (Top View) 8-Pin MSOP (TPS7A66xx-Q1) DGN Package (Top View) Vin 1 8 Vout Vin 1 8 Vout SI 2 7 SO EN 2 7 FB/NU PG NC 3 6 PG CT 4 5 GND NC 3 CT 6 5 4 GND NC - No internal connection NU - Make no external connection NC - No internal connection Pin Functions PIN NO. PIN NAME SOIC-D MSOP-DGN CT 4 4 O Reset-pulse delay adjustment. Connecting this pin via a capacitor to GND EN 2 I Enable pin. The device enters the standby state when the enable pin becomes lower than the threshold. FB/NU 7 I Feedback pin when using external resistor divider or NU pin when using internal resistor divider TYPE DESCRIPTION GND 5 5 G Ground reference NC 3 3 -- Not-connected pin PG 6 6 O Output ready. This open-drain pin must connect to Vout via an external resistor. The output voltage going below threshold pulls it down. SI 2 I Sense input pin to supervise input voltage. Connect via an external voltage divider to Vin and GND SO 7 O Sense output. This open-drain pin must connect to Vout via an external resistor. The SI voltage becoming lower than the threshold pulls it down. Vin 1 1 P Input power-supply voltage Vout 8 8 O Output voltage -- -- Thermal pad for MSOP-DGN package 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Vin, EN Unregulated input (2) Vout Regulated output SI (2) MIN MAX -0.3 45 UNIT V -0.3 7 V -0.3 Vin V CT -0.3 25 V FB, SO, PG -0.3 Vout V -40 150 C TJ (1) (2) (3) 4 See (3) (1) Operating junction temperature range Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND Absolute maximum voltage, withstand 45 V for 200 ms Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 6.2 Handling Ratings Tstg MIN MAX UNIT -65 150 C 0 4 Corner pins (1, 4, 5, and 8) 0 1 Other pins 0 1 Storage temperature range Human body model (HBM), per AEC Q100-002 (1) V(ESD) (1) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 kV AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. spacer 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX 4 40 V EN, SI 0 40 V CT 0 20 V 1.5 5.5 V Vin Unregulated input Vout PG, SO, FB Low voltage (I/O) TJ Operating junction temperature UNIT 0 5.5 V -40 150 C 6.4 Thermal Information THERMAL METRIC (1) TPS7A66xx-Q1 TPS7A69xx-Q1 MSOP (8 PINS) SOIC (8 PINS) 113.2 C/W UNIT RJA Junction-to-ambient thermal resistance 63.4 RJC(top) Junction-to-case (top) thermal resistance 53.0 59.6 C/W RJB Junction-to-board thermal resistance (2) 37.4 59.57 C/W JT Junction-to-top characterization parameter 3.7 12.8 C/W JB Junction-to-board characterization parameter 37.1 52.9 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 13.5 NA C/W (1) (2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 5 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com 6.5 Electrical Characteristics V(Vin) = 14 V, 1 m < ESR < 2 , TJ = -40C to 150C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND CURRENT (Vin) Fixed 5-V output, IO = 1 mA 5.5 40 4 40 V 20 A No load current and EN = OFF 4 A V(EN) = 40 V 1 A 1.247 V 2.6 V V(Vin) Input voltage I(q) Quiescent current V(Vin) = 5.5 V to 40 V, EN = ON, IO = 0.2 mA I(Sleep) Input sleep current I(EN) EN pin current V(bg) Band gap Reference voltage for FB V(VinUVLO) Undervoltage detection Ramp V(Vin) down until output turns OFF V(UVLOhys) Undervoltage hysteresis Fixed 3.3-V output, IO = 1 mA 12 1.199 1.223 1 V V ENABLE INPUT (EN) VIL Logic input low level VIH Logic input high level 0 0.4 1.7 V V REGULATED OUTPUT (Vout) V(Vout) Regulated output IO = 1 mA, TJ = 25C -1% 1% V(Vin) = 6 V to 40 V, IO = 1 mA to 150 mA, fixed 5-V version -2% 2% V(Vin) = 4 V to 40 V, IO = 1 mA to 150 mA, fixed 3.3-V version -2% 2% V(Vin) = V(Vout) + 0.45 V and Vin 4 V, IO = 1 mA to 150 mA, adjustable version (1) -2% 2% V(line-reg) Line regulation V(Vin) = 5.5 V to 40 V, IO = 50 mA V(load-reg) Load regulation IO = 1 mA to 150 mA V(dropout) = V(Vin) - V(Vout), IOUT = 80 mA V(Vin) - V(Vout), IOUT = 150 mA 5 mV 20 mV 180 240 300 450 V(Vin) = 3 V, V(dropout) = V(Vin) - V(Vout), IO = 5 mA 12 27.5 58 V(Vin) = 3 V, V(dropout) = V(Vin) - V(Vout), IO = 30 mA 44 80 145 V(dropout) Dropout voltage IO Output current V(Vout) in regulation I(lreg-CL) Output current limit V(Vout) short to ground 0 500 mV 150 mA 800 mA V(Vin) = 12 V, IL = 10 mA, output capacitance = 2.2 F Power supply ripple rejection (2) PSRR Frequency = 100 Hz 60 dB Frequency = 100 kHz 40 dB VOLTAGE SENSING PRE-WARNING VI(S-th) Sense low threshold V(SI) decreasing VI(S-th,hys) Sense threshold hysteresis VOL(S) Sense output low voltage (V(SI) 1.06 V, V(Vin) 4 V, R(SO) = 10 k to V(Vout) IOH(S) Sense output leakage (V(SO) = 5 V, V(SI) 1.5 V) II(S) Sense input current 1.089 1.123 1.157 50 100 150 -1 0.1 V mV 0.4 V 1 A 1 A RESET (PG) VOL Reset output, low voltage IOL = 0.5 mA Ilkg Leakage current Reset pulled Vout through 10-k resistor V(TH-POR) Power-on-reset threshold V(Vout) increasing V(Thres) Hysteresis 89.6 91.6 0.4 V 1 A 93.6 2 % of Vout % of Vout RESET DELAY (CT) I(Chg) Delay-capacitor charging current V(th) Threshold to release PG high V(CT) = 0 V 1.4 A 1 V OPERATING TEMPERATURE RANGE TJ Junction temperature T(shutdown) Junction shutdown temperature 175 C T(hyst) Hysteresis of thermal shutdown 20 C (1) (2) 6 -40 150 C Adjustable version with precision external feedback resistor with tolerance of less than 1%. Design information - Not tested Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(SDeglitch,rise) SI or SO rising deglitch time 50 260 s t(SDeglitch,drop) SI or SO falling deglitch time 30 240 s TIMING FOR RESET (PG) t(POR) Where C = delay capacitor value; capacitance C = 100 nF (1) Power-on-reset delay t(POR-fixed) No capacitor on pin t(Deglitch) (1) Reset deglitch time 50 100 180 ms 100 290 650 s 20 250 s This information only is not tested in production and equation basis is (C x 1) / 1 x 10-6 = td (delay time). Where C = Delay capacitor value. Capacitance C range = 100 pF to 100 nF. 6.7 Typical Characteristics 1.0 PG Rising PG Falling 91.5 91.0 90.5 90.0 89.5 89.0 T = 25C 0.6 T = 125C 0.4 0.2 0.0 0.2 0.4 0.6 0.8 1.0 88.5 40 25 10 5 20 35 50 65 80 95 Temperature (C) 110 125 0 120 5 15 20 25 30 35 40 Input Voltage (V) 45 C002 Figure 2. Line Regulation (Vin = 14 V, IL = 1 mA) 25 T = 40C T = 40C T = 25C 100 10 C001 Figure 1. Power-Good Threshold Voltage vs Temperature (Vin = 14 V, No Load) T = 25C Quiescent Current (A) T = 125C 80 IGND (A) T = 40C 0.8 Nominal Output Voltage (%) Nominal Output Voltage (%) 92.0 60 40 20 0 20 T = 125C 15 10 5 0 0 20 40 60 Output Current (mA) 80 100 C003 Figure 3. Ground Current vs Output Current (Vin = 14 V) Copyright (c) 2012-2014, Texas Instruments Incorporated 0 5 10 15 20 25 30 35 40 Input Voltage (V) 45 C004 Figure 4. Quiescent Current vs Input Voltage (IL = 0) Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 7 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com Typical Characteristics (continued) 2.0 1.5 T = 25C T = 125C 1.0 0.5 0.0 0.5 1.0 T = 25C T = 125C 250 200 150 100 50 1.5 2.0 0 0 10 20 30 40 50 60 70 80 90 Output Current (mA) 0 100 10 20 30 40 50 60 70 80 90 Output Current (mA) C005 Figure 5. Load Regulation (Vin = 14 V) 100 C006 Figure 6. Dropout Voltage vs Output Current (Vin = 4 V) 6 3.5 5 3.0 Output Voltage (V) Output Voltage (V) T = 40C 300 Dropout Voltage (mV) Nominal Output Voltage (%) 350 T = 40C 4 3 2 1 2.5 2.0 1.5 1.0 0.5 0 0.0 0 5 10 15 20 25 30 35 Supply Voltage (V) 40 0 5 10 15 20 25 30 35 Supply Voltage (V) C007 Figure 7. Output Voltage vs Supply Voltage (Fixed 5-V Version, IL = 0) 40 C008 Figure 8. Output Voltage vs Supply Voltage (Fixed 3.3-V Version, IL = 0) 100.0 120 100 80.0 PSRR (dB) CLOAD (F) 80 60.0 Stable Region 40.0 60 40 20 20.0 0 2.2 0.0 0.001 0.0 20 0.5 1.0 1.5 ESR of Cout ( ) Figure 9. Load Capacitance vs ESR Stability 8 Submit Documentation Feedback 2.0 C009 10 100 1k 10k 100k 1M Frequency (Hz) 10M 100M C010 Figure 10. Power-Supply Rejection Ratio vs Frequency Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 Typical Characteristics (continued) All oscilloscope waveforms were taken at room temperature. Figure 11. Load Transient Response, 10 ms/div Figure 12. Load Transient Response, 10 ms/div Figure 13. Line Transient Response, IL = 1 mA, 1 V/s Figure 14. Line Transient Response, IL = 10 mA, 1 V/s Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 9 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com 7 Detailed Description 7.1 Overview This product is a combination of a low-dropout linear regulator with reset function. The power-on reset initializes once the Vout output exceeds 91.6% of the target value. The power-on-reset delay is a function of the value set by an external capacitor on the CT pin before releasing the PG pin high. 7.2 Functional Block Diagrams TPS7A66xx-Q1 UVLO Comp Vref(3) + Band Gap 1 Vin V(bat) 22 F 0.1 F Vref1 Overcurrent Detection EN 2 Logic Control Thermal Shutdown Regulator Control 8 + GND Vout V(reg) 4.7 F Vref(1) V(reg) 5 10 k 6 CT PG Reset Control 4 Figure 15. TPS7A66xx-Q1 Functional Block Diagram 10 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 Functional Block Diagrams (continued) TPS7A69xx-Q1 UVLO Comp Vref3 + Band Gap 1 Vin V(bat) 22 F 0.1 F Vref(1) Overcurrent Detection Logic Control Thermal Shutdown Regulator Control 8 + GND Vout V(reg) 4.7 F Vref(1) V(reg) 5 10 k 6 CT PG Reset Control 4 V(reg) V(bat) 10 k 7 SO SI 2 + Vref(1) Figure 16. TPS7A69xx-Q1 Functional Block Diagram 7.3 Feature Description 7.3.1 Enable (EN) This is a high-voltage-tolerant pin; high input activates the device and turns the regulator ON. One can connect this input to the Vin pin for self-bias applications. Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 11 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com Feature Description (continued) 7.3.2 Regulated Output (Vout) This is the regulated output based on the required voltage. The output has current limitation. During initial power up, the regulator has a soft start incorporated to control initial current through the pass element and the output capacitor. In the event the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage recovers above the minimum start-up level. 7.3.3 Power-On Reset (PG) This is an output with an external pullup resistor to the regulated supply. The output remains low until the regulated Vout has exceeded approximately 90% of the set value and the power-on-reset delay has expired. The on-chip oscillator presets the delay. The regulated output falling below the 90% level asserts this output low after a short de-glitch time of approximately 250 s (typical). 7.3.4 Reset Delay Timer (CT) An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this pin is open, the default delay time is 290 s (typ). After releasing the PG pin high, the capacitor on this pin discharges, thus allowing the capacitor to charge from approximately 0.2 V for the next power-on-reset delaytimer function. An external capacitor, CT, defines the reset-pulse delay time, t(POR), with the charge time of: C(CT) 1 V t (POR) = 1 mA (1) The power-on reset initializes once the output V(Vout) exceeds 91.6% of the programmed value. The power-onreset delay is a function of the value set by an external capacitor on the CT pin before the releasing of the PG pin high. Vin t < t(Deglitch) VTH(POR) V(Thres) Vout V(th) V(th) CT t(POR) t(POR) t(Deglitch) PG t(Deglitch) Figure 17. Conditions for Activation of Reset 12 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 Feature Description (continued) Vin 0.9 x V (th) Vout CT V(th) t(POR) PG Figure 18. External Programmable Reset Delay 7.3.5 Sense Comparator (SI and SO for TPS7A69xx-Q1) The sense comparator compares the input signal with an internal voltage reference of 1.223 V for rising and 1.123 V for falling threshold. The use of an external voltage divider makes this comparator very flexible in the application. The device can supervise the input voltage either before or after the protection diode and give additional information to the microprocessor, like low-voltage warnings. The regulator operates in low-power mode when the output load is below 2 mA (typical, 1-mA to 10-mA range). In this mode, the regulator output tolerance is approximately V(Vout) 1%. 7.3.6 Adjustable Output Voltage (FB for TPS7A6601-Q1) One can select an output voltage between 1.5 V and 5 V by using an external resistor divider. Calculate the output voltage using the following equation, where V(FB) = 1.223 V. The recommendation for R1 and R2 is that both be less than 100 k. R1 o ae V(Vout) = V(FB) c 1 + R2 /o e (2) Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 13 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com Feature Description (continued) TPS7A6601-Q1 V(bat) 1 Vin Vout 8 V(reg) C2 C1 R1 2 EN FB/NU 7 R3 R2 4 CT PG 6 GND 5 C3 Figure 19. External Feedback Resistor Divider 7.3.7 Undervoltage Shutdown There is an internally fixed undervoltage shutdown threshold. Undervoltage shutdown activates when the input voltage on Vin drops below V(VinUVLO). This ensures the regulator is not latched into an unknown state during low input supply voltage. If the input voltage has a negative transient which drops below the UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up sequence once the input voltage is above the required levels. 7.3.8 Low-Voltage Tracking At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage based on the load current (IO) and switch resistance (R(SW)). This allows for a smaller input capacitor and can possibly eliminate the need of using a boost convertor during cold-crank conditions. 7.3.9 Thermal Shutdown These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point, the output turns on again. Thermal protection disables the output when the junction temperature rises to approximately 170C, allowing the device to cool. Cooling of the junction temperature to approximately 150C enables the output circuitry. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. The purpose of the design of the internal protection circuitry of the TPS7A66/69xx-Q1 is for protection against overload conditions, not as a replacement for proper heat-sinking. Continuously running the TPS7A66xx-Q1 or TPS7A69xx-Q1 into thermal shutdown degrades device reliability. 14 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 7.4 Device Functional Modes 7.4.1 Operation With V(VIN) < 4 V The devices operate with input voltages above 4 V. The maximum UVLO voltage is 2.6 V, and the devices operate at an input voltage above 4 V. The devices can also operate at lower input voltages; no minimum UVLO voltage is specified. At input voltages below the actual UVLO voltage, the devices do not operate. 7.4.2 Operation With EN Control (TPS7A66xx-Q1) The enable rising edge threshold voltage is 1.7 V (maximum). With the EN pin held above that voltage and the input voltage above 4 V, the device becomes active. The enable falling edge is 0.4 V (minimum). Holding the EN pin below that voltage disables the device, thus reducing the IC quiescent current. Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 15 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS7A66xx-Q1 and TPS7A69xx-Q1 devices are 150-mA low-dropout linear regulators designed for up to 40-V Vin operation with only 12 A quiescent current at no load. One can use the Pspice transient model, which is downloadable from the product folder (see Related Links), for evaluating the base function of the devices. in addition, there are specific EVMs designed for these devices. Both the EVM and its user guide are available on the product folder as well. 8.2 Typical Applications Figure 20 and Figure 22 show typical application circuits for the TPS7A66xx-Q1 and TPS7A69xx-Q1, respectively. One may use different values of external components, depending on the end application. An application may require a larger output capacitor during fast load steps in order to prevent reset from occurring. TI recommends a low-ESR ceramic capacitor with dielectric of type X5R or X7R. 8.2.1 TPS7A66xx-Q1 Typical Application TPS7A66xx-Q1 V(bat) 1 Vin Vout 8 V(reg) 2.2 F 1 F 10 k 2 4 1 nF EN PG 6 GND 5 CT Figure 20. Typical Application Schematic for TPS7A66xx-Q1 8.2.1.1 Design Requirements For this design example, use the parameters listed in Table 1 as the design parameters. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 4 V to 40 V Output voltage 3.3 V Output current rating 150 mA Output capacitor range 2.2 F to 100 F Output capacitor ESR range 1 m to 2 CT capacitor range 100 pF to 100 nF 16 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 8.2.1.2 Detailed Design Procedure To * * * * * * begin the design process, determine the following: Input voltage range Output voltage Output current rating Input capacitor Output capacitor Power-up-reset delay time 8.2.1.2.1 Input Capacitor The device requires an input decoupling capacitor, the value of which depends on the application. The typical recommended value for the decoupling capacitor is 10 F. The voltage rating must be greater than the maximum input voltage. 8.2.1.2.2 Output Capacitor The device requires an output capacitor to stablize the output voltage. The capacitor value should be between 2.2 F and 100 F. The ESR range should be between 1 m and 2 . TI recommends to selecting a ceramic capacitor with low ESR to improve the load transient response. 8.2.1.3 Application Performance Plots Figure 21. Power Up (5 V), 20 ms/div, IL = 20 mA 8.2.2 TPS7A69xx-Q1 Typical Application TPS7A69xx-Q1 V(bat) 1 Vin Vout 8 1 F V(reg) 2.2 F 10 k R3 2 SI SO 7 PG 6 GND 5 10 k 2.2 F R4 4 CT 1 nF Figure 22. Typical Application Schematic for TPS7A69xx-Q1 Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 17 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com 8.2.2.1 Design Requirements For this design example, use the parameters listed in Table 1 as the input parameters. Table 2. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 4 V to 40 V Output voltage 3.3 V Output current rating 150 mA Output capacitor range 2.2 F to 100 F Output capacitor ESR range 1 m to 2 CT capacitor range 100 pF to 100 nF Low-voltage tracking threshold 6 V to 9 V 8.2.2.2 Detailed Design Procedure To * * * * * * * begin the design process, determine the following: Input voltage range Output voltage Output current rating Input capacitor Output capacitor Power-up-reset delay time Low-voltage tracking threshold 8.2.2.2.1 Low-Voltage Tracking Threshold After determining the low-voltage tracking threshold, calculate the ratio of the resistor divider connected to Vin, SI, and GND by the following equation: R3 V(LT) = -1 R4 1.223 (3) TI recommends that the values of both R3 and R4 be less than 100 k. 8.2.2.3 Application Performance Plots Figure 23. Power Up (5 V), 20 ms/div, IL = 20 mA 18 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 9 Power Supply Recommendations Design of the device is for operation from an input voltage supply with a range between 4 V and 28 V. This input supply must be well regulated. If the input supply is located more than a few inches from the TPS7A66xx-Q1 or TPS7A69xx-Q1 device, TI recommends adding an electrolytic capacitor with a value of 22 F and a ceramic bypass capacitor at the input. 10 Layout 10.1 Layout Guidelines The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple undesirable signals from nearby components (especially from logic and digital ICs, such as microcontrollers and microprocessors); these capacitive-coupled signals may produce undesirable output voltage transients. In these cases, TI recommends the use of a fixed-voltage version of the TPS7A66xx-Q1, or isolation of the FB node by flooding the local PCB area with ground-plane copper to minimize any undesirable signal coupling. 10.1.1 Package Mounting Solder pad footprint recommendations for the TPS7A66xx-Q1 and TPS7A69xx-Q1 are available at the end of this product data sheet and at www.ti.com. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance For the layout of TPS7A66xx-Q1 and TPS7A69xx-Q1, place the input and output capacitors close to the devices as shown in Figure 24 and Figure 25, respectively. In order to enhance the thermal performance, TI recommends surrounding the device with some vias. To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board design with separate ground planes for Vin and Vout, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability. Place every capacitor as close as possible to the device and on the same side of the PCB as the regulator itself. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI strongly discourages the use of vias and long traces because they may impact system performance negatively and even cause instability. If possible, and to ensure the maximum performance specified in this product data sheet, use the same layout pattern used for the TPS7A66xx-Q1 and TPS7A69xx-Q1 evaluation board, available at www.ti.com. 10.2 Layout Examples Vin Vout EN FB/NU NC PG CT GND Power Ground Figure 24. TPS7A66xx-Q1 Board Layout Diagram Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 19 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 www.ti.com Layout Examples (continued) Vin Vout SI SO NC PG CT GND Power Ground Figure 25. TPS7A69xx-Q1 Board Layout Diagram 10.3 Power Dissipation and Thermal Considerations Calculate power dissipated in the device using Equation 4. space PD = I O (V(Vin) - V(Vout) ) + I (q) V(Vin) (4) where: PD = continuous power dissipation IO = output current V(Vin) = input voltage V(Vout) = output voltage As I(q) << IO, therefore ignore the term I(q) x V(Vin) in Equation 4. For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) using Equation 5. space T J = TA + (R qJA PD) ) (5) where: RJA = junction-to-ambient air thermal impedance space DT = TJ - TA = (R qJA PD) ) 20 Submit Documentation Feedback (6) Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1 www.ti.com SLVSBL0E - DECEMBER 2012 - REVISED NOVEMBER 2014 11 Device and Documentation Support 11.1 Related Links The table below lists quick-access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PART PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS7A6601-Q1 Click here Click here Click here Click here Click here TPS7A6633-Q1 Click here Click here Click here Click here Click here TPS7A6650-Q1 Click here Click here Click here Click here Click here TPS7A6933-Q1 Click here Click here Click here Click here Click here TPS7A6950-Q1 Click here Click here Click here Click here Click here 11.2 Trademarks All trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2012-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 21 PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS7A6601QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA4Q TPS7A6633QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA2Q TPS7A6650QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA1Q TPS7A6933QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 6933 TPS7A6950QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 6950 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS7A6601QDGNRQ1 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS7A6633QDGNRQ1 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS7A6650QDGNRQ1 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS7A6933QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS7A6950QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A6601QDGNRQ1 MSOP-PowerPAD DGN 8 2500 366.0 364.0 50.0 TPS7A6633QDGNRQ1 MSOP-PowerPAD DGN 8 2500 366.0 364.0 50.0 TPS7A6650QDGNRQ1 MSOP-PowerPAD DGN 8 2500 366.0 364.0 50.0 TPS7A6933QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 TPS7A6950QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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