Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
1
Smart Quad Low-Side Switch
Features Product Summary
• Short circuit protection
• Overtemperature protection
• Overvoltage protection
• 8 bit serial data input and diag-
nostic output (SPI protocol)
• Direct parallel control of four
channels for PWM applications
• Cascadable with other quad
switches
• Low quiescent current
• µC compatible input
• Electostatic discharge (ESD) protection
Application
• µC compatible power switch for 12 V and 24 V applications
• Switch for automotive and industrial system
• Solenoids, relays and resistive loads
• Injectors
• Robotic controls
General Description
Quad Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and
four open drain DMOS output stages. The TLE 6220 GP is protected by embedded protection func-
tions and designed for automotive and industrial applications. The output stages can be controlled di-
rect in parallel f or PWM applications ( injector coils) , or thr ough serial cont rol via the SPI. T herefor e the
TLE 6220 GP is particularly suitable for engine management and powertrain systems.
Block Diagram
Supply voltage
V
S 4.5 – 5.5 V
Drain source voltage
V
DS(AZ)max 60 V
On resistance (
T
J = 25 °C)
R
ON(max) 0.4 Ω
Output current (all outp. ON equal)
I
D(NOM) 1A
(individually) 3 A
(total max. all channels) 4 A
P-DSO-20-10
Ordering Code:
Q67006-A9315 C701
FAULTRESET
CS
Output S tage
Output Cont rol
Buffer
Serial Interface
SPI
LOGIC
SCLK
SI 84
GND
VS
SO
14
IN1
IN2
IN3
IN4 OUT1
OUT4
PRG
VBB
VS
as Ch. 1
as Ch. 1
as Ch. 1
8
GND
normal function
SCB / overload
open load
short to
g
round
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
2
Pin Description Pin Configuration (Top view)
Pin Symbol Function
1 GND Ground
2 IN2 Input Channel 2
3 OUT1 Power Output Channel 1
4 VS Supply Voltage
5RESET Reset
6CS Chip Select
7 PRG Program (inputs high or low active)
8 OUT2 Power Output Channel 2
9 IN1 Input Channel 1
10 GND Ground
11 GND Ground
12 IN4 Input Channel 4
13 OUT3 Power Output Channel 3
14 FAULT General Fault Flag
15 SO Serial Data Output
16 SCLK Serial Clock
17 SI Serial Data Input
18 OUT4 Power Output Channel 4
19 IN3 Input Channel 3
20 GND Ground
Heat slug internally connected to ground pins
GND 1•20 GND
IN2 2 19 IN3
OUT1 3 18 OUT4
VS 4 17 SI
RESET 5 16 SCLK
CS 615SO
PRG 7 14 FAULT
OUT2 8 13 OUT3
IN1 9 12 IN4
GND 10 11 GND
Power SO-20
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
3
Maximum Ratings for
T
j = – 40°C to 150°C
Parameter Symbol Values Unit
Supply Voltage
V
S-0.3 ... +7 V
Continuous Drain Source Voltage (OUT1...OUT8)
V
DS 45 V
Input Voltage, All Inputs and Data Lines
V
IN - 0.3 ... + 7 V
Load Dump Protection
V
Load Dump =
U
P+
U
S;
U
P=13.5 V
With Automotive Injector Valve
R
L = 14 Ω
R
I1)=2 Ω;
t
d=400ms; IN = low or high
With
R
L= 6.8 Ω (
I
D = 2A)
R
I=2 Ω;
t
d=400ms; IN = low or high
V
Load Dump2)
62
52
V
Output Current per Channel
I
D(lim) self limited A
Output per Channel @
T
A = 25°C
(All 4 Channels ON; Mounted on PCB ) 3)
I
D1A
Output Clamping Energy
I
D = 1A
E
AS 50 mJ
Power Dissipation (DC, mounted on PCB) @
T
A = 25°C
P
tot 3W
Electrostatic Discharge Voltage (human body model)
according to MIL STD 883D, method 3015.7 and EOS/ESD
assn. standard S5.1 - 1993
V
ESD 2000 V
DIN Humidity Category, DIN 40 040 -- E --
IEC Climatic Category, DIN IEC 68-1 -- 40/150/56 --
Thermal resistance
junction - case
junction - ambient @ min. footprint
junction - ambient @ 6 cm2 cooling area
R
thJC
R
thJA
5
50
40
K/W
Test board for
6 cm2 cooling area min. footprint
1)
R
I=internal resistance of the load dump test pulse generator LD200
2)
V
LoadDump is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839.
3) Output current rating so long as maximum junction temperature is not exceeded. At
T
A = 125 °C the output cur-
rent has to be calculated using
R
thJA according mounting conditions.
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
4
Electrical Characteristics
Parameter and Conditions Symbol Values Unit
V
S = 4.5 to 5.5 V ;
T
j
= - 40 °C to + 150 °C
(unless otherwise specified) min typ max
1. Power Supply
Supply Voltage
V
S4.5 -- 5.5 V
Supply Current
I
S(ON) -- 12mA
Supply Current in Standby Mode (RESET = L)
I
S(stby) -- -- 50 µA
2. Power Outputs
ON Resistance
V
S = 5 V;
I
D = 1 A
T
J = 25°C
T
J = 150°C
R
DS(ON) --
-- --
-- 0.4
0.75 Ω
Output Clamping Voltage output OFF
V
DS(AZ) 45 -- 60 V
Current Limit
I
D(lim) 346A
Output Leakage Current
V
RESET = L
I
D(lkg) -- -- 10 µA
Turn-On Time
I
D = 1 A, resistive load
t
ON -- 35µs
Turn-Off Time
I
D = 1 A, resistive load
t
OFF -- 25µs
3. Digital Inputs
Input Low Voltage
V
INL - 0.3 -- 1.0 V
Input High Voltage
V
INH 2.0 -- -- V
Input Voltage Hysteresis
V
INHys 50 100 -- mV
Input Pull Down/Up Current (IN1 ... IN4)
I
IN(1..4) 20 50 100 µA
PRG, RESET Pull Up Current
I
IN(PRG,Res) 20 50 100 µA
Input Pull Down Current (SI, SCLK)
I
IN(SI,SCLK) 10 20 50 µA
Input Pull Up Current (CS)
I
IN(CS) 10 20 50 µA
4. Digital Outputs (SO,FAULT )
SO High State Output Voltage ISOH = 1 mA
V
SOH
V
S-1V -- -- V
SO Low State Output Voltage ISOL = 1.6 mA
V
SOL -- -- 0.4 V
Output Tri-state Leakage Current CS= H, 0 ≤
V
SO ≤
V
S
I
SOlkg -10 0 10 µA
FAULTOutput Low Voltage
I
FAULT = 1.6 mA
V
FAULTL -- -- 0.4 V
5. Diagnostic Functions
Open Load Detection Voltage
V
DS(OL) -- 3-- V
Output Pull Down Current
I
PD(OL) 50 90 150 µA
Fault Delay Time
t
d(fault) 50 110 200 µs
Short to Ground Detection Voltage
V
DS(SHG) -- 2-- V
Short to Ground Detection Current
I
SHG -50 -100 -150 µA
Current Limitation; Overload Threshold Current
I
D(lim) 1...4 346A
Overtemperature Shutdown Threshold
Hysteresis
T
th(sd)
T
hys
170
-- --
10 200
-- °C
K
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
5
Electrical Characteristics cont.
Parameter and Conditions Symbol Values Unit
V
S = 4.5 to 5.5 V ;
T
j
= - 40 °C to + 150 °C
(unless otherwise specified) min typ max
6. SPI-Timing
Serial Clock Frequency
f
SCK DC -- 5 MHz
Serial Clock Period (1/fclk)
t
p(SCK) 200 -- -- ns
Serial Clock High Time
t
SCKH 50 -- -- ns
Serial Clock Llow Time
t
SCKL 50 -- -- ns
Enable Lead Time (falling edge of CS to rising edge of CLK)
t
lead 250 -- -- ns
Enable Lag Time (falling edge of CLK to rising edge of CS )
t
lag 250 -- -- ns
Data Setup Time (required time SI to falling of CLK)
t
SU -- 25 -- ns
Data Hold Time (falling edge of CLK to SI)
t
H-- 25 -- ns
SO Rise Time (CL=200 pF)
t
rso -- -- 50 ns
SO Fall Time (CL=200 pF)
t
fso -- -- 50 ns
SI, CS, SCLK Rise Time (SPI inputs)
t
rSI -- -- 50 ns
SI, CS, SCLK Fall Time (SPI inputs)
t
fSI -- -- 50 ns
Enable Time
t
EN 250 -- -- ns
Disable Time
t
DIS 250 -- -- ns
Data Valid Time
t
valid -- 50 -- ns
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
6
Functional Description
The TLE 6220 GP is an quad-low-side power switch which provides a serial peripheral inter-
face (SPI) to control the 4 power DMOS switches, as well as diagnostic feedback. The power
transistors are protected against short to
V
BB, overload, overtemperature and against over-
voltage by an active zener clamp.
The diagnostic logic recognises a f ault condition which can be read out via the serial diagnos-
tic output (SO).
Circuit Description
Power Transistor Protection Functions
Each of the four output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 3 A. The continuous current for each channel is 1.25 A
(all channels ON).
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protection
level (about 170 °C) will change the output into a low duty cycle PWM (selective therm al shut-
down with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6220 GP by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition: - Diagnostic status information is transferred from the power
outputs into the shift register.
- Serial input data can be clocked in from then on.
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits.
CS Low to High transition: - Transfer of SI bits from shift register into output buffers
- Reset of diagnosis register.
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6220 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
7
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-
mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of one byte, made up of four control bits and four data bits. The con-
trol word is used to program the device, to operate it in a certain mode as well as providing
diagnostic information (see page 11). The four data bits contain the input information for the
four channels, and are high active.
SO - Serial Output. Diagnostic data bits are shif ted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the
CS
pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
Output Stage Control
The four outputs of the T LE 6220 GP can either be controlled in parallel (IN1...IN4), or via the
Serial Peripheral Interface (SPI).
Parallel Control
A Boolean operation (either AND or OR) is performed on each of the parallel inputs and re-
spective SPI data bits, in order to determine the states of the respective outputs. The type of
Boolean operation performed is programmed via the serial interface.
The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins
are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4
are switched OFF. PRG pin itself is internally pulled up when it is not connected.
PRG - Program pin. PRG = High (
V
S): Parallel inputs Channel 1 to 4 are high active
PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active.
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
8
Serial Control of the Outputs: SPI protocol
Each output is independently controlled by an output latch and a common reset line, which
disables all four outputs. The Serial Input (SI) is read on the f alling edge of the serial clock. A
logic high input ’data bit’ turns the respective output channel ON, a logic low ’data bit’ turns it
OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition
of CS transfers the serial data input bits to the output control buffer.
As mentioned above, the serial input byte consists of a 4 bit control word and a 4 bit data
word. Via the control word, the specific mode of the device is programmable.
MSB LSB
321321 Bits DataBits Control
DDDDCCCC : Serial input byte
Five specific control words are recognised, having the following functions:
No. Serial Input Byte Function
1 LLLL XXXX Only ’Full Diagnosis’ performed. No change to output states.
2 HHLL XXXX State of four parallel inputs and ’1-bit Diagnosis’ outputted.
3 HLHL XXXX Echo-function of SPI; SI direct connected to SO
4 LLHH DDDD IN1...4 and serial data bits ’OR’ed. ’Full Diagnosis’ performed.
5 HHHH DDDD IN1...4 and serial data bits ’AND’ed. ’Full Diagnosis’ performed.
Note: ’X’ means ’don’t care’, because this bit will be ignored
’D’ represents the data bit, either being H (=ON) or L (=OFF)
1. LLLL XXXX - Diagnosis only
By clocking in this control byte, it is possible to get pure diagnostic information (two bits per
channel) in accordance with Figure 1 (page 11). The data bits are ignored, so that the state of
the outputs are not influenced. This command is only active once unless the next control
command is again "Diagnosis only".
2. HHLL XXXX - Reading back of input, and ‘1-bit Diagnosis’
If the TLE 6220 GP is used as bare die in a hybrid application, it is necessary to know if proper
connections exist between the µC-port and parallel inputs. By entering ‘HHLL’ as the control
word, the first four bits of the SO give the state of the parallel inputs, depending on the µC
signals. By comparing the four IN-bits with the corresponding µC-port signal, the necessary
connection between the µC and the TLE 6220 can be verified - i.e. ‘read back of the inputs’.
The second 4-bit word fed out at the serial output contains ‘1-bit’ fault information of the out-
puts ( H = no fault, L = fault ). In the expression given below for the output byte, ‘FX’ is the
fault bit for channel X.
MSB LSB
IN4 IN3 IN2 IN1 F4 F3 F2 F1 : Serial Output byte
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
9
SI H H L L X X X X
SO H H H H H H H H
CS CS
SI H H H H L H H L
SO IN4 IN3 IN2 IN1 F4 F3 F2 F1
SI co mmand
: No change of the
output state; reading back of
inputs and 1bit diagnosis
SO diagnos is
: No fault, normal
function
CS
SI H H H H L L L L
SO H H H H H H H H
SI command
: AND-Operation;
Ch1 and 4 OFF, Ch2 and 3 ON.
SO diagnosis
: St ate of fou r parallel
inputs an d 1 bit diagnosi s performed
SI command
: AND-Operation and
all channels OFF.
SO diagnosis
: No fault, normal
function
3. HLHL XXXX - Echo-function of SPI
To check the proper function of the serial interface the TLE 6220 GP provides a "SPI Echo
Function". By entering HLHL as control word, SI and SO are connected during the next CS
period. By comparing the bits clocked in with the serial output bits, the proper function of the
SPI interface can be verified. This internal loop is only closed once (for one CS period).
SI H L H L X X X X
SO H H H H L H H H
CS CS
SI
SO
SI command
: No ch an ge of the
output st at es; Echo function of SP I
SO dia gnosis
: Open load condition
at chan nel 2, other channe ls ok.
CS
SI L L H H L L H L
SO H H H H L H H H
SI command
: OR-operation, channel
2 ON, others OFF
SO diagnosis
: Open load condition
at channel 2, other channels ok.
SI word
SO word
Echo-function of SPI, i.e. SI
dire ctly connected to SO.
Data bits will be ignored.
4. LLHH DDDD -OR operation, and ‘full diagnosis’
W ith LLHH as the control word, each of the input signals IN1...IN4 are 'OR'ed with the corre-
sponding data bits (DDDD).
≥ 1 Output
Driver
IN 1...4
Serial Input,
data bits 0...3
This OR operation enables the serial interf ace to switch the channel ON, even though the cor-
responding parallel input might be in the off state.
⇒ SPI Priority for ON-State
Also parallel control of the outputs is possible without an SPI input.
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
10
The OR-function is the default Boolean operation if the device restarts after a Reset, or when
the supply voltage is switched on for the first time.
If the OR operation is programmed it is latched until it is overwritten by the AND operation.
5. HHHH DDDD - AND operation, and ‘full diagnosis’
W ith HHHH as the control word, each of the input signals IN1...IN4 are 'AND'ed with the cor-
responding data bits (DDDD).
&Output
Driver
IN 1...4
Serial Input,
data bits 0...3
The AND operation implies that the output can be switched off by the SPI data bit input, even
if the corresponding parallel input is in the ON state.
⇒ SPI Priority for OFF-state
This also implies that the serial input data bit can only switch the output channel ON if the cor-
responding parallel input is in the ON state.
If the AND operation is programmed it is latched until it is overwritten by the OR operation.
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
11
Diagnostics
FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transi-
tion as soon as an error occurs for any one of the eight channels. This fault indication can be
used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called
after this fault indication. This saves processor time compared to a cyclic reading of the SO
information.
As soon as an error occurs, error information is latched into the diagnosis register. A new error
will over-write the old error report. Serial data out pin (SO) is in a high impedance state when
CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. The
rising edge of CS will reset all error registers.
Full Diagnosis
For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 1.
Normal function: The bit combination HH indicates that there is no f ault condition, i.e. normal
function.
Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current
limitation gets active, i.e. there is a overload, short to supply or overtemperature condition.
Open load: An open load condition is detected when the drain voltage decreases below 3 V
(typ.). LH bit combination is set.
Short Circuit to GND: If the drain source voltage falls below 2 V (typ.), short to ground is de-
tected by the LL bit combination.
A definite distinction between open load and short to ground is guaranteed by design.
The standard way of obtaining diagnostic information is as follows:
Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs to
settle. Clock in the identical serial information once again - during this process the data com-
ing out at SO contains the bit combinations representing the diagnosis conditions as described
in Figure 1.
Diagnostic Serial OUT (SO)
HH Normal function
HL Overload, Shor ted Load or Overtemperature
LH Open Load
LL Shorted to Ground
Ch.4 Ch.3 Ch.2 Ch.1
7 6 5 4 3 2 1 0
Figure 1: Two bits per channel diagnostic feedback
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
12
Timing Diagrams
Figure 2: Serial Interface
Figure 3: Input Timing Diagram
Figure 4:
SO Valid Time Waveforms Enable and Disable Time Waveforms
Data
Bits
674444 84444
ControlBits
674444 84444
CS
SCLK
SI
Outputs OLD NEW
7 6 5 4 3 2 1 0
SO 7 6 5 4 3 2 1 0
MSB LSB
tlead
tSCKH
0.2VS
tlag
tH
tfSI
tSCKL
0.2 VS
tSU
trSI
0.7VS
0.2VS
CS
SCLK
SI
tvali
SCLK
CS
SO
tDi
s
0.2 VS
tE
SO
0.7 VS
0.7 VS
0.2 VS
SO 0.7 VS
0.2 VS
t
rS
tfS
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
13
Figure 5: Power Outputs
Application Circuit
t
t
tON tOFF
80%
VDS
VIN
20%
OUT1
OUT2
OUT4
TLE
6220
GP
SI
SO
CLK
CS
VS
VS
RESET
GND
VBB
CLK
MTSR
MRST
P x
µC
e.g. C166
IN1
IN2
IN3
IN4
FAULT
PRG
10k
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
14
Parallel SPI Configuration
Engine Management Application
TLE 6230 GP in combination with TLE 6240 GP (16-fold switch) for relays and general purpose loads
and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous
loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16
can be controlled direct in parallel for PWM applications.
4
SI
CLK
SO
4
SI
CLK
SO
CS
CS
MTSR
MRST
CLK
P x.y
P x.1-4
P x.y
P x.1-4
µC
C167
4 PWM
Channels
4 PWM
Channels
CS
Injector 1
Injector 2
Injector 3
Injector 4
TLE
6220 GP
Quad
TLE
6230 GP
Octal
8
SI
CLK
SO
CS
8 PWM
Channels
TLE
6240 GP
16-fold
P x.y
P x.1-8
Preliminary Data Sheet TLE 6220 GP
Semiconductor Group Page 20. May 98
15
Package and Ordering Code
(all dimensions in mm)
P - DSO - 20 - 10 Ordering Code
TLE 6220 GP Q67006-A9315 C701
0.1
8°
1
3
1.2 -0.3
15.9+/-0.15
A
2.8 8° 8°
8°
6.3
11+/-0.151)
14.2+/-0.3
110
1120
PIN 1 INDEX MARKING
1 x
45°
13.7 -0.2
9 x =11.431.27
1.27 0.25 A
M
0.4 +0.13
3
2
+
/
0
1
5
9
+
/
0
1
15.74 +/- 0.1