Preliminary Data Sheet TLE 6220 GP Smart Quad Low-Side Switch Features Product Summary * Short circuit protection VS Supply voltage * Overtemperature protection Drain source voltage VDS(AZ)max * Overvoltage protection On resistance (TJ = 25 C) RON(max) * 8 bit serial data input and diagOutput current (all outp. ON equal) ID(NOM) nostic output (SPI protocol) * Direct parallel control of four (individually) channels for PWM applications (total max. all channels) * Cascadable with other quad switches * Low quiescent current * C compatible input * Electostatic discharge (ESD) protection Application * C compatible power switch for 12 V and 24 V applications * Switch for automotive and industrial system * Solenoids, relays and resistive loads * Injectors * Robotic controls 4.5 - 5.5 60 0.4 1 3 4 V V A A A P-DSO-20-10 Ordering Code: Q67006-A9315 C701 General Description Quad Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and four open drain DMOS output stages. The TLE 6220 GP is protected by embedded protection functions and designed for automotive and industrial applications. The output stages can be controlled direct in parallel for PWM applications (injector coils), or through serial control via the SPI. Therefore the TLE 6220 GP is particularly suitable for engine management and powertrain systems. Block Diagram PRG GND RESET FAULT VS VS normal function IN1 SCB / overload IN2 as Ch. 1 IN3 as Ch. 1 IN4 as Ch. 1 open load LOGIC short to ground Output Stage 8 SCLK SI CS VBB 1 8 Serial Interface SPI OUT1 4 4 Output Control Buffer OUT4 SO GND Semiconductor Group Page 1 20. May 98 Preliminary Data Sheet TLE 6220 GP Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol GND IN2 OUT1 VS RESET CS PRG OUT2 IN1 GND GND IN4 OUT3 FAULT SO SCLK SI OUT4 IN3 GND Pin Configuration (Top view) Function Ground Input Channel 2 Power Output Channel 1 Supply Voltage Reset GND IN2 OUT1 VS RESET CS Chip Select Program (inputs high or low active) Power Output Channel 2 Input Channel 1 Ground Ground Input Channel 4 Power Output Channel 3 General Fault Flag PRG OUT2 IN1 GND 1* 2 3 4 5 6 7 8 9 10 20 GND 19 IN3 18 OUT4 17 SI 16 SCLK 15 SO 14 FAULT 13 OUT3 12 IN4 11 GND Power SO-20 Serial Data Output Serial Clock Serial Data Input Power Output Channel 4 Input Channel 3 Ground Heat slug internally connected to ground pins Semiconductor Group Page 2 20. May 98 Preliminary Data Sheet TLE 6220 GP Maximum Ratings for Tj = - 40C to 150C Parameter Supply Voltage Symbol VS Continuous Drain Source Voltage (OUT1...OUT8) VDS VIN VLoad Dump2) Input Voltage, All Inputs and Data Lines Load Dump Protection VLoad Dump = UP+US; UP=13.5 V With Automotive Injector Valve RL = 14 RI1)=2 ; td=400ms; IN = low or high With RL= 6.8 (ID = 2A) RI=2 ; td=400ms; IN = low or high Values -0.3 ... +7 Unit V 45 V - 0.3 ... + 7 V V 62 52 ID(lim) ID Output Current per Channel Output per Channel @ TA = 25C (All 4 Channels ON; Mounted on PCB ) 3) self limited A 1 A Output Clamping Energy ID = 1A EAS 50 mJ Power Dissipation (DC, mounted on PCB) @ TA = 25C Ptot VESD 3 W 2000 V DIN Humidity Category, DIN 40 040 -- E -- IEC Climatic Category, DIN IEC 68-1 -- 40/150/56 -- Electrostatic Discharge Voltage (human body model) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993 K/W Thermal resistance junction - case junction - ambient @ min. footprint junction - ambient @ 6 cm2 cooling area RthJC RthJA 5 50 40 Test board for 6 cm2 cooling area min. footprint 1) RI=internal resistance of the load dump test pulse generator LD200 VLoadDump is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839. 3) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 C the output current has to be calculated using RthJA according mounting conditions. 2) Semiconductor Group Page 3 20. May 98 Preliminary Data Sheet TLE 6220 GP Electrical Characteristics Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 C to + 150 C (unless otherwise specified) Symbol Values min Unit typ max 1. Power Supply Supply Voltage VS 4.5 -- 5.5 V Supply Current IS(ON) -- 1 2 mA Supply Current in Standby Mode (RESET = L) IS(stby) -- -- 50 A TJ = 25C TJ = 150C RDS(ON) -- -- -- -- 0.4 0.75 output OFF VDS(AZ) 45 -- 60 V ID(lim) 3 4 6 A ID(lkg) -- -- 10 A 2. Power Outputs ON Resistance VS = 5 V; ID = 1 A Output Clamping Voltage Current Limit VRESET = L Output Leakage Current Turn-On Time ID = 1 A, resistive load tON -- 3 5 s Turn-Off Time ID = 1 A, resistive load tOFF -- 2 5 s Input Low Voltage VINL - 0.3 -- 1.0 V Input High Voltage VINH 2.0 -- -- V Input Voltage Hysteresis VINHys 50 100 -- mV Input Pull Down/Up Current (IN1 ... IN4) IIN(1..4) IIN(PRG,Res) IIN(SI,SCLK) IIN(CS) 20 50 100 A 20 50 100 A 10 20 50 A 10 20 50 A 3. Digital Inputs PRG, RESET Pull Up Current Input Pull Down Current (SI, SCLK) Input Pull Up Current ( CS ) 4. Digital Outputs (SO, FAULT ) SO High State Output Voltage ISOH = 1 mA VSOH VS-1V -- -- V SO Low State Output Voltage ISOL = 1.6 mA VSOL -- -- 0.4 V ISOlkg VFAULTL -10 0 10 A -- -- 0.4 V Open Load Detection Voltage VDS(OL) -- 3 -- V Output Pull Down Current IPD(OL) td(fault) VDS(SHG) 50 90 150 A 50 110 200 s -- 2 -- V ISHG ID(lim) 1...4 Tth(sd) Thys -50 -100 -150 A 3 4 6 A 170 -- -10 200 -- C K Output Tri-state Leakage Current CS = H, 0 VSO VS FAULT Output Low Voltage IFAULT = 1.6 mA 5. Diagnostic Functions Fault Delay Time Short to Ground Detection Voltage Short to Ground Detection Current Current Limitation; Overload Threshold Current Overtemperature Shutdown Threshold Hysteresis Semiconductor Group Page 4 20. May 98 Preliminary Data Sheet TLE 6220 GP Electrical Characteristics cont. Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 C to + 150 C (unless otherwise specified) Symbol Values min typ Unit max 6. SPI-Timing Serial Clock Frequency fSCK DC -- 5 MHz Serial Clock Period (1/fclk) tp(SCK) 200 -- -- ns Serial Clock High Time tSCKH 50 -- -- ns Serial Clock Llow Time tSCKL 50 -- -- ns Enable Lead Time (falling edge of CS to rising edge of CLK) tlead 250 -- -- ns Enable Lag Time (falling edge of CLK to rising edge of CS ) tlag 250 -- -- ns Data Setup Time (required time SI to falling of CLK) tSU -- 25 -- ns Data Hold Time (falling edge of CLK to SI) tH -- 25 -- ns SO Rise Time (CL=200 pF) trso -- -- 50 ns SO Fall Time (CL=200 pF) tfso -- -- 50 ns SI, CS , SCLK Rise Time (SPI inputs) trSI -- -- 50 ns SI, CS , SCLK Fall Time (SPI inputs) tfSI -- -- 50 ns Enable Time tEN 250 -- -- ns Disable Time tDIS 250 -- -- ns Data Valid Time tvalid -- 50 -- ns Semiconductor Group Page 5 20. May 98 Preliminary Data Sheet TLE 6220 GP Functional Description The TLE 6220 GP is an quad-low-side power switch which provides a serial peripheral interface (SPI) to control the 4 power DMOS switches, as well as diagnostic feedback. The power transistors are protected against short to VBB, overload, overtemperature and against overvoltage by an active zener clamp. The diagnostic logic recognises a fault condition which can be read out via the serial diagnostic output (SO). Circuit Description Power Transistor Protection Functions Each of the four output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. The outputs are provided with a current limitation set to a minimum of 3 A. The continuous current for each channel is 1.25 A (all channels ON). Each output is protected by embedded protection functions. In the event of an overload or short to supply, the current is internally limited and the corresponding bit combination is set (early warning). If this operation leads to an overtemperature condition, a second protection level (about 170 C) will change the output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures. SPI Signal Description CS - Chip Select. The system microcontroller selects the TLE 6220 GP by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the C and vice versa. CS High to Low transition: - Diagnostic status information is transferred from the power outputs into the shift register. - Serial input data can be clocked in from then on. - SO changes from high impedance state to logic high or low state corresponding to the SO bits. CS Low to High transition: - Transfer of SI bits from shift register into output buf fers - Reset of diagnosis register. To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition of CS . When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6220 GP. The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the Semiconductor Group Page 6 20. May 98 Preliminary Data Sheet TLE 6220 GP rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS makes any transition. SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the output stages. The input data consists of one byte, made up of four control bits and four data bits. The control word is used to program the device, to operate it in a certain mode as well as providing diagnostic information (see page 11). The four data bits contain the input information for the four channels, and are high active. SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge of SCLK. RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs OFF. An internal pull-up structure is provided on chip. Output Stage Control The four outputs of the TLE 6220 GP can either be controlled in parallel (IN1...IN4), or via the Serial Peripheral Interface (SPI). Parallel Control A Boolean operation (either AND or OR) is performed on each of the parallel inputs and respective SPI data bits, in order to determine the states of the respective outputs. The type of Boolean operation performed is programmed via the serial interface. The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4 are switched OFF. PRG pin itself is internally pulled up when it is not connected. PRG - Program pin. Semiconductor Group PRG = High (VS): Parallel inputs Channel 1 to 4 are high active PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active. Page 7 20. May 98 Preliminary Data Sheet TLE 6220 GP Serial Control of the Outputs: SPI protocol Each output is independently controlled by an output latch and a common reset line, which disables all four outputs. The Serial Input (SI) is read on the falling edge of the serial clock. A logic high input 'data bit' turns the respective output channel ON, a logic low 'data bit' turns it OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition of CS transfers the serial data input bits to the output control buffer. As mentioned above, the serial input byte consists of a 4 bit control word and a 4 bit data word. Via the control word, the specific mode of the device is programmable. MSB LSB CCCC DDDD : Serial input byte 123 123 Control Bits Data Bits Five specific control words are recognised, having the following functions: No. 1 2 3 4 5 Serial Input Byte LLLL XXXX HHLL XXXX HLHL XXXX LLHH DDDD HHHH DDDD Function Only 'Full Diagnosis' performed. No change to output states. State of four parallel inputs and '1-bit Diagnosis' outputted. Echo-function of SPI; SI direct connected to SO IN1...4 and serial data bits 'OR'ed. 'Full Diagnosis' performed. IN1...4 and serial data bits 'AND'ed. 'Full Diagnosis' performed. Note: 'X' means 'don't care', because this bit will be ignored 'D' represents the data bit, either being H (=ON) or L (=OFF) 1. LLLL XXXX - Diagnosis only By clocking in this control byte, it is possible to get pure diagnostic information (two bits per channel) in accordance with Figure 1 (page 11). The data bits are ignored, so that the state of the outputs are not influenced. This command is only active once unless the next control command is again "Diagnosis only". 2. HHLL XXXX - Reading back of input, and `1-bit Diagnosis' If the TLE 6220 GP is used as bare die in a hybrid application, it is necessary to know if proper connections exist between the C-port and parallel inputs. By entering `HHLL' as the control word, the first four bits of the SO give the state of the parallel inputs, depending on the C signals. By comparing the four IN-bits with the corresponding C-port signal, the necessary connection between the C and the TLE 6220 can be verified - i.e. `read back of the inputs'. The second 4-bit word fed out at the serial output contains `1-bit' fault information of the outputs ( H = no fault, L = fault ). In the expression given below for the output byte, `FX' is the fault bit for channel X. MSB LSB IN4 IN3 IN2 IN1 F4 F3 F2 F1 Semiconductor Group Page 8 : Serial Output byte 20. May 98 Preliminary Data Sheet TLE 6220 GP CS SI CS CS H H L L X X X X SI H H H H L H H L SO H H H H H H H H SO IN4 IN3 IN2 IN1 F4 F3 F2 F1 SI command: No change of the output state; reading back of inputs and 1bit diagnosis SO diagnosis: No fault, normal function SI command: AND-Operation; Ch1 and 4 OFF, Ch2 and 3 ON. SO diagnosis: State of four parallel inputs and 1 bit diagnosis performed SI H H H H L L L L SO H H H H H H H H SI command: AND-Operation and all channels OFF. SO diagnosis: No fault, normal function 3. HLHL XXXX - Echo-function of SPI To check the proper function of the serial interface the TLE 6220 GP provides a "SPI Echo Function". By entering HLHL as control word, SI and SO are connected during the next CS period. By comparing the bits clocked in with the serial output bits, the proper function of the SPI interface can be verified. This internal loop is only closed once (for one CS period). CS SI CS H L H L X X X X SO H H H H L H H H SI command: No change of the output states; Echo function of SPI SO diagnosis: Open load condition at channel 2, other channels ok. CS SI SI word SI SO SO word SO H H H H L H H H Echo-function of SPI, i.e. SI directly connected to SO. Data bits will be ignored. L L H H L L H L SI command: OR-operation, channel 2 ON, others OFF SO diagnosis: Open load condition at channel 2, other channels ok. 4. LLHH DDDD - OR operation, and `full diagnosis' With LLHH as the control word, each of the input signals IN1...IN4 are 'OR'ed with the corresponding data bits (DDDD). IN 1...4 1 Output Driver Serial Input, data bits 0...3 This OR operation enables the serial interface to switch the channel ON, even though the corresponding parallel input might be in the off state. SPI Priority for ON-State Also parallel control of the outputs is possible without an SPI input. Semiconductor Group Page 9 20. May 98 Preliminary Data Sheet TLE 6220 GP The OR-function is the default Boolean operation if the device restarts after a Reset, or when the supply voltage is switched on for the first time. If the OR operation is programmed it is latched until it is overwritten by the AND operation. 5. HHHH DDDD - AND operation, and `full diagnosis' With HHHH as the control word, each of the input signals IN1...IN4 are 'AND'ed with the corresponding data bits (DDDD). IN 1...4 & Output Driver Serial Input, data bits 0...3 The AND operation implies that the output can be switched off by the SPI data bit input, even if the corresponding parallel input is in the ON state. SPI Priority for OFF-state This also implies that the serial input data bit can only switch the output channel ON if the corresponding parallel input is in the ON state. If the AND operation is programmed it is latched until it is overwritten by the OR operation. Semiconductor Group Page 10 20. May 98 Preliminary Data Sheet TLE 6220 GP Diagnostics FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transi- tion as soon as an error occurs for any one of the eight channels. This fault indication can be used to generate a C interrupt. Therefore a `diagnosis' interrupt routine need only be called after this fault indication. This saves processor time compared to a cyclic reading of the SO information. As soon as an error occurs, error information is latched into the diagnosis register. A new error will over-write the old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. The rising edge of CS will reset all error registers. Full Diagnosis For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 1. Diagnostic Serial OUT (SO) 7 6 Ch.4 HH HL LH LL 5 4 Ch.3 3 2 Ch.2 1 0 Ch.1 Normal function Overload, Shorted Load or Overtemperature Open Load Shorted to Ground Figure 1: Two bits per channel diagnostic feedback Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function. Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. Open load: An open load condition is detected when the drain voltage decreases below 3 V (typ.). LH bit combination is set. Short Circuit to GND: If the drain source voltage falls below 2 V (typ.), short to ground is detected by the LL bit combination. A definite distinction between open load and short to ground is guaranteed by design. The standard way of obtaining diagnostic information is as follows: Clock in serial information into SI pin and wait approximately 150 s to allow the outputs to settle. Clock in the identical serial information once again - during this process the data coming out at SO contains the bit combinations representing the diagnosis conditions as described in Figure 1. Semiconductor Group Page 11 20. May 98 Preliminary Data Sheet TLE 6220 GP Timing Diagrams CS SCLK Control Bits Data Bits 64444744448 64444744448 SI 7 6 5 4 3 2 1 0 LSB MSB SO 7 6 5 Outputs 4 3 2 1 0 OLD NEW Figure 2: Serial Interface CS 0.2 VS tlag trSI tSCKH tlead SCLK 0.2VS tSCKL tSU tH tfSI 0.7VS SI 0.2VS Figure 3: Input Timing Diagram 0.7 V S SCLK CS 0.2 V S t vali tE SO SO 0.7 V S 0.2 V S t Dis SO t rS 0.7 V S 0.2 V S t fS Figure 4: SO Valid Time Waveforms Semiconductor Group Enable and Disable Time Waveforms Page 12 20. May 98 Preliminary Data Sheet TLE 6220 GP VIN t tOFF tON VDS 80% 20% t Figure 5: Power Outputs Application Circuit VBB VS 10k VS PRG OUT1 FAULT OUT2 RESET IN1 IN2 IN3 IN4 C e.g. C166 MTSR SI MRST SO CLK CLK P xy CS OUT4 TLE 6220 GP GND Semiconductor Group Page 13 20. May 98 Preliminary Data Sheet TLE 6220 GP Parallel SPI Configuration Engine Management Application TLE 6230 GP in combination with TLE 6240 GP (16-fold switch) for relays and general purpose loads and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16 can be controlled direct in parallel for PWM applications. Injector 1 4 P x.1-4 4 PWM Channels MTSR SI SO MRST CS 4 Injector 3 TLE 6220 GP Quad CLK CS CLK P x.y Injector 2 Injector 4 4 PWM Channels P x.1-4 C SI SO C167 CLK P x.y CS TLE 6230 GP Octal 8 8 PWM Channels P x.1-8 SI SO CLK P x.y Semiconductor Group CS TLE 6240 GP 16-fold Page 14 20. May 98 Preliminary Data Sheet TLE 6220 GP Package and Ordering Code (all dimensions in mm) P - DSO - 20 - 10 Ordering Code Q67006-A9315 C701 TLE 6220 GP 15.74 +/- 0.1 13.7 -0.2 9 x 1.27 = 11.43 0.4 1.27 20 +0.13 0.25 M A 11 1 0 /+ 2 3 1 1 0 /+ 9 5 10 1x 45 PIN 1 INDEX MARKING A 15.9 +/-0.15 1.2 -0.3 0.1 3 1 8 2.8 8 8 6.3 11 +/-0.15 8 1) 14.2 +/-0.3 Semiconductor Group Page 15 20. May 98