MSP430F122IRHBT - Texas Instruments

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DLow Supply Voltage Range 1.8 V to 3.6 V

DUltralow-Power Consumption:

− Active Mode: 200 μA at 1 MHz, 2.2 V

− Standby Mode: 0.7 μA

− Off Mode (RAM Retention): 0.1 μA

DFive Power Saving Modes

DWake-Up From Standby Mode in less

than 6 μs

D16-Bit RISC Architecture, 125 ns

Instruction Cycle Time

DBasic Clock Module Configurations:

− Various Internal Resistors

− Single External Resistor

− 32 kHz Crystal

− High Frequency Crystal

− Resonator

− External Clock Source

D16-Bit Timer_A With Three

Capture/Compare Registers

DOn-Chip Comparator for Analog Signal

Compare Function or Slope A/D

Conversion

DSerial Communication Interface (USART0)

Software-Selects Asynchronous UART or

Synchronous SPI

DSerial Onboard Programming,

No External Programming Voltage Needed

Programmable Code Protection by Security

Fuse

DFamily Members Include:

MSP430F122: 4KB + 256B Flash Memory

256B RAM

MSP430F123: 8KB + 256B Flash Memory

256B RAM

DAvailable in a 28-Pin Plastic Small-Outline

Wide Body (SOWB) Package, 28-Pin Plastic

Thin Shrink Small-Outline Package

(TSSOP) and 32-Pin QFN Package

DFor Complete Module Descriptions, See the

MSP430x1xx Family User’s Guide,

Literature Number SLAU049

description

The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs.

The MSP430F12x series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and

twenty-two I/O pins. The MSP430F12x series also has a built-in communication capability using asynchronous

(UART) and synchronous (SPI) protocols in addition to a versatile analog comparator.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another

area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors.

AVAILABLE OPTIONS

PACKAGED DEVICES

TAPLASTIC 28-PIN SOWB

(DW)

PLASTIC 28-PIN TSSOP

(PW)

PLASTIC 32-PIN QFN

(RHB)

40°Cto85°C

MSP430F122IDW MSP430F122IPW MSP430F122IRHB

−40°C to 85°C

MSP430F122IDW

MSP430F123IDW

MSP430F122IPW

MSP430F123IPW

MSP430F122IRHB

MSP430F123IRHB

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pin designation, MSP430x12x

TEST

VCC

P2.5/ROSC

VSS

XOUT

XIN

RST/NMI

P2.0/ACLK

P2.1/INCLK

P2.2/CAOUT/TA0

P3.0/STE0

P3.1/SIMO0

P3.2/SOMI0

P3.3/UCLK0

P1.7/TA2/TDO/TDI

P1.6/TA1/TDI/TCLK

P1.5/TA0/TMS

P1.4/SMCLK/TCK

P1.3/TA2

P1.2/TA1

P1.1/TA0

P1.0/TACLK

P2.4/CA1/TA2

P2.3/CA0/TA1

P3.7

P3.6

P3.5/URXD0

P3.4/UTXD0

DW OR PW PACKAGE

(TOP VIEW)

RHB PACKAGE

(TOP VIEW)

XIN

P2.5/ROSC

RST/NMI

VCC

P2.0/ACLK

TEST

P2.1/INCLK

P1.7/TA2/TDO/TDI

XOUT

P1.6/TA1/TDI/TCLK

P1.1/TA0

P1.0/TACLK

P2.4/CA1/TA2

P2.3/CA0/TA1

P1.2/TA1

10 11 12 13

272829

P3.0/STE0

P3.1/SIMO0

P3.2/SOMI0

P3.3/UCLK0

P3.4/UTXD0

P3.5/URXD0

P3.6 P1.5/TA0/TMS

3031

VSS P1.3/TA2

P2.2/CAOUT/TA0 NC

P3.7 P1.4/SMCLK/TCK

Note: NC pins not internally connected

Power Pad connection to VSS recommended

functional block diagram

Oscillator ACLK

SMCLK

CPU

Incl. 16 Reg.

Bus

Conv

MCB

XIN XOUT P3P2

MDB, 16 Bit

MAB, 16 Bit

MCLK

MAB,

4 Bit

VCC VSS RST/NMI

System

Clock

ROSC

8KB Flash

4KB Flash

256B RAM

Watchdog

Timer

15/16-Bit

Timer_A3

3 CC Reg

I/O Port 1

8 I/Os, with

Interrupt

Capability

I/O Port 2

6 I/Os, with

Interrupt

Capability

POR USART0

UART Mode

SPI Mode

I/O Port 3

8 I/Os

MDB, 16-Bit

MAB, 16-Bit

JTAG

TEST

Test

JTAG

Emulation

Module

8 6 8

Comparator

MDB, 8 Bit

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

DW, PW RHB I/O DESCRIPTION

NAME NO. NO.

I/O

DESCRIPTION

P1.0/TACLK 21 21 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input

P1.1/TA0 22 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL

transmit

P1.2/TA1 23 23 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output

P1.3/TA2 24 24 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output

P1.4/SMCLK/TCK 25 25 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device

programming and test

P1.5/TA0/TMS 26 26 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input

terminal for device programming and test

P1.6/TA1/TDI/TCLK 27 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal or

test clock input

P1.7/TA2/TDO/TDI†28 28 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or

data input during programming

P2.0/ACLK 8 6 I/O General-purpose digital I/O pin/ACLK output

P2.1/INCLK 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK

P2.2/CAOUT/TA0 10 8 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output/BSL

receive

P2.3/CA0/TA1 19 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input

P2.4/CA1/TA2 20 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input

P2.5/ROSC 3 32 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal

frequency

P3.0/STE0 11 9 I/O General-purpose digital I/O pin/slave transmit enable—USART0/SPI mode

P3.1/SIMO0 12 10 I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode

P3.2/SOMI0 13 11 I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode

P3.3/UCLK0 14 12 I/O General-purpose digital I/O pin/external clock input—USART0/UART or SPI mode, clock

output—USART0/SPI mode clock input

P3.4/UTXD0 15 13 I/O General-purpose digital I/O pin/transmit data out—USART0/UART mode

P3.5/URXD0 16 14 I/O General-purpose digital I/O pin/receive data in—USART0/UART mode

P3.6 17 15 I/O General-purpose digital I/O pin

P3.7 18 16 I/O General-purpose digital I/O pin

RST/NMI 7 5 I Reset or nonmaskable interrupt input

TEST 1 29 I Selects test mode for JTAG pins on Port1

VCC 2 30 Supply voltage

VSS 4 1 Ground reference

XIN 6 3 I Input terminal of crystal oscillator

XOUT 5 2 O Output terminal of crystal oscillator

NC 4, 17,

20, 31

No internal connection

QFN Pad NA Package

Pad

NA QFN package pad connection to VSS recommended.

†TDO or TDI is selected via JTAG instruction.

General-Purpose Register

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-Purpose Register

R10

R11

General-Purpose Register

R14

R15

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator respectively. The

remaining registers are general-purpose

registers.

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

instruction set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; the address modes are listed

in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5

Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC

Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)

Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)

Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)

Indirect DMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)

Indirect

autoincrement DMOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11

R10 + 2−−> R10

Immediate DMOV #X,TONI MOV #45,TONI #45 −−> M(TONI)

NOTE: S = source D = destination

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request and restore back to

the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

DActive mode AM;

− All clocks are active

DLow-power mode 0 (LPM0);

− CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

DLow-power mode 1 (LPM1);

− CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

DCO’s dc-generator is disabled if DCO not used in active mode

DLow-power mode 2 (LPM2);

− CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator remains enabled

ACLK remains active

DLow-power mode 3 (LPM3);

− CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

ACLK remains active

DLow-power mode 4 (LPM4);

− CPU is disabled

ACLK is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

Crystal oscillator is stopped

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh-0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up

External reset

Watchdog

Flash memory

WDTIFG (see Note1)

KEYV (see Note 1) Reset 0FFFEh 15, highest

NMI

Oscillator fault

Flash memory access violation

NMIIFG (see Notes 1 and 4)

OFIFG (see Notes 1 and 4)

ACCVIFG (see Notes 1 and 4)

(non)-maskable,

(non)-maskable

0FFFCh 14

0FFFAh 13

0FFF8h 12

Comparator_A CAIFG maskable 0FFF6h 11

Watchdog timer WDTIFG maskable 0FFF4h 10

Timer_A3 TACCR0 CCIFG (see Note 2) maskable 0FFF2h 9

Timer_A3

TACCR1 and TACCR2

CCIFGs, TAIFG

(see Notes 1 and 2)

maskable 0FFF0h 8

USART0 receive URXIFG0 maskable 0FFEEh 7

USART0 transmit UTXIFG0 maskable 0FFECh 6

0FFEAh 5

0FFE8h 4

I/O Port P2

(eight flags − see Note 3)

P2IFG.0 to P2IFG.7

(see Notes 1 and 2) maskable 0FFE6h 3

I/O Port P1

(eight flags)

P1IFG.0 to P1IFG.7

(see Notes 1 and 2) maskable 0FFE4h 2

0FFE2h 1

0FFE0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module

3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’12x devices.

4. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

that are not allocated to a functional purpose are not physically present in the device. Simple software access

is provided with this arrangement.

interrupt enable 1 and 2

7654 0

OFIE WDTIE

32 1

rw-0 rw-0 rw-0

Address

0h NMIIEACCVIE

rw-0

WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog

timer is configured in interval timer mode.

OFIE: Oscillator-fault-interrupt enable

NMIIE: Nonmaskable-interrupt enable

ACCVIE: Flash access violation interrupt enable

7654 032 1

Address

01h UTXIE0 URXIE0

rw-0

URXIE0: USART0: UART and SPI receive-interrupt enable

UTXIE0: USART0: UART and SPI transmit-interrupt enable

interrupt flag register 1 and 2

7654 0

OFIFG WDTIFG

32 1

rw-0 rw-1 rw-(0)

Address

02h NMIIFG

WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC

power up or a reset condition at the RST/NMI pin in reset mode.

OFIFG: Flag set on oscillator fault

NMIIFG: Set via RST/NMI pin

7654 032 1

Address

03h UTXIFG0 URXIFG0

rw-0

URXIFG0: USART0: UART and SPI receive flag

UTXIFG0: USART0: UART and SPI transmit flag

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

module enable registers 1 and 2

7654 032 1

Address

04h

7654 032 1

Address

05h UTXE0 URXE0

USPIE0

rw-0 rw-0

URXE0: USART0: UART receive enable

UTXE0: USART0: UART transmit enable

USPIE0: USART0: SPI (synchronous peripheral interface) transmit and receive enable

Legend rw:

rw-0,1:

Bit can be read and written.

Bit can be read and written. It is Reset or Set by PUC

SFR bit is not present in device.

rw-(0,1): Bit can be read and written. It is Reset or Set by POR

memory organization

MSP430F122 MSP430F123

Memory

Main: interrupt vector

Main: code memory

Size

Flash

4KB Flash

0FFFFh−0FFE0h

0FFFFh−0F000h

8KB Flash

0FFFFh−0FFE0h

0FFFFh−0E000h

Information memory Size

Flash

256 Byte

010FFh − 01000h

256 Byte

010FFh − 01000h

Boot memory Size

ROM

1KB

0FFFh − 0C00h

1KB

0FFFh − 0C00h

RAM Size 256 Byte

02FFh − 0200h

256 Byte

02FFh − 0200h

Peripherals 16-bit

8-bit

8-bit SFR

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial

interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete

description of the features of the BSL and its implementation, see the Application report Features of the MSP430

Bootstrap Loader, Literature Number SLAA089.

BSL Function DW & PW Package Pins RHB Package Pins

Data Transmit 22 - P1.1 22 - P1.1

Data Receive 10 - P2.2 8 - P2.2

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

DFlash memory has n segments of main memory and two segments of information memory (A and B) of 128

bytes each. Each segment in main memory is 512 bytes in size.

DSegments 0 to n may be erased in one step, or each segment may be individually erased.

DSegments A and B can be erased individually, or as a group with segments 0−n.

Segments A and B are also called information memory.

DNew devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory prior to the first use.

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using

all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number

SLAU049.

oscillator and system clock

The clock system in the MSP430x12x devices is supported by the basic clock module that includes support for

a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal

oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power

consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The basic

clock module provides the following clock signals:

DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.

DMain clock (MCLK), the system clock used by the CPU.

DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

digital I/O

There are three 8-bit I/O ports implemented—ports P1, P2, and P3 (only six port P2 I/O signals are available

on external pins):

DAll individual I/O bits are independently programmable.

DAny combination of input, output, and interrupt conditions is possible.

DEdge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2.

DRead/write access to port-control registers is supported by all instructions.

NOTE:

Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port

P2 are implemented. Port P3 has no interrupt capability.

watchdog timer

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

USART0

The MSP430x12x devices have one hardware universal synchronous/asynchronous receive transmit

(USART0) peripheral module that is used for serial data communication. The USART supports synchronous

SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive

channels.

timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A3 Signal Connections

Input Pin Number

Device Input Signal

Module Input Name

Module Block

Module Output Signal

Output Pin Number

DW, PW RHB Device Input Signal Module Input Name Module Block Module Output Signal DW, PW RHB

21 - P1.0 21 - P1.0 TACLK TACLK

ACLK ACLK

Timer

SMCLK SMCLK Timer NA

9 - P2.1 7 - P2.1 INCLK INCLK

22 - P1.1 22 - P1.1 TA0 CCI0A 22 - P1.1 22 - P1.1

10 - P2.2 8 - P2.2 TA0 CCI0B

CCR0

TA0

26 - P1.5 26 - P1.5

DVSS GND CCR0 TA0

DVCC VCC

23 - P1.2 23 - P1.2 TA1 CCI1A 19 - P2.3 18 - P2.3

CAOUT (internal) CCI1B

CCR1

TA1

23 - P1.2 23 - P1.2

DVSS GND CCR1 TA1 27 - P1.6 27 - P1.6

DVCC VCC

24 - P1.3 24 - P1.3 TA2 CCI2A 20 - P2.4 19 - P2.4

ACLK (internal) CCI2B

CCR2

TA2

24 - P1.3 24 - P1.3

DVSS GND CCR2 TA2 28 - P1.7 28 - P1.7

DVCC VCC

comparator_A

The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,

battery-voltage supervision, and monitoring of external analog signals.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripheral file map

PERIPHERALS WITH WORD ACCESS

Timer_A Reserved

Reserved

Capture/compare register

Timer_A register

Reserved

Capture/compare control

Timer_A control

Timer_A interrupt vector

TACCR2

TACCR1

TACCR0

TAR

TACCTL2

TACCTL1

TACCTL0

TACTL

TAIV

017Eh

017Ch

017Ah

0178h

0176h

0174h

0172h

0170h

016Eh

016Ch

016Ah

0168h

0166h

0164h

0162h

0160h

012Eh

Flash Memory Flash control 3

Flash control 2

Flash control 1

FCTL3

FCTL2

FCTL1

012Ch

012Ah

0128h

Watchdog Watchdog/timer control WDTCTL 0120h

PERIPHERALS WITH BYTE ACCESS

USART0 Transmit buffer

Receive buffer

Baud rate

Modulation control

Receive control

Transmit control

USART control

U0TXBUF

U0RXBUF

U0BR1

U0BR0

U0MCTL

U0RCTL

U0TCTL

U0CTL

077h

076h

075h

074h

073h

072h

071h

070h

Comparator_A Comparator_A port disable

Comparator_A control2

Comparator_A control1

CAPD

CACTL2

CACTL1

05Bh

05Ah

059h

Basic Clock Basic clock sys. control2

Basic clock sys. control1

DCO clock freq. control

BCSCTL2

BCSCTL1

DCOCTL

058h

057h

056h

Port P3 Port P3 selection

Port P3 direction

Port P3 output

Port P3 input

P3SEL

P3DIR

P3OUT

P3IN

01Bh

01Ah

019h

018h

Port P2 Port P2 selection

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

Port P2 direction

Port P2 output

Port P2 input

P2SEL

P2IE

P2IES

P2IFG

P2DIR

P2OUT

P2IN

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

Port P1 Port P1 selection

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

Port P1 output

Port P1 input

P1SEL

P1IE

P1IES

P1IFG

P1DIR

P1OUT

P1IN

026h

025h

024h

023h

022h

021h

020h

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Special Function Module enable2

Module enable1

SFR interrupt flag2

SFR interrupt flag1

SFR interrupt enable2

SFR interrupt enable1

ME2

ME1

IFG2

IFG1

IE2

IE1

005h

004h

003h

002h

001h

000h

absolute maximum ratings†

Voltage applied at VCC to VSS −0.3 V to 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any pin (see Note) −0.3 V to VCC+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode current at any device terminal ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, Tstg (unprogrammed device) −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, Tstg (programmed device) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied

to the TEST pin when blowing the JTAG fuse.

recommended operating conditions

MIN NOM MAX UNITS

Supply voltage during program execution V (see Note 1)

Supply voltage during program execution, VCC (see Note 1) 1.8 3.6 V

Supply voltage during program/erase flash memory, VCC 2.7 3.6 V

Supply voltage, VSS 0 V

Operating free-air temperature range, TA−40 85 °C

LFXT1 t l f f

LF mode selected, XTS=0 Watch crystal 32768 Hz

LFXT1 crystal frequency, f(LFXT1)

(see Note 2)

XT1 selected mode XTS 1

Ceramic resonator 450 8000

kHz

(

see

XT1 selected mode, XTS=1 Crystal 1000 8000 kHz

Processor frequency f (MCLK signal)

VCC = 1.8 V dc 4.15

MHz

Processor frequency f(system) (MCLK signal) VCC = 3.6 V dc 8 MHz

NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC <2.5 V. The LFXT1 oscillator in

XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC ≥ 2.2 V. The LFXT1 oscillator in XT1-mode accepts

a ceramic resonator or a crystal frequency of 8 MHz at VCC ≥ 2.8 V.

2. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or crystal.

1.8 V 3.6 V2.7 V 3 V

ÎÎÎÎ

4.15 MHz

8.0 MHz

Supply Voltage − V

Supply voltage range, ’F12x,

during flash memory programming

Supply voltage range,

’F12x, during

program execution

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.7 V.

f(system) (MHz)

Figure 1. Frequency vs Supply Voltage, MSP430F12x

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

supply current (into VCC) excluding external current

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TA = −40°C +85°C,

MCLK

= f

(SMCLK)

= 1 MHz, VCC = 2.2 V 200 250

μA

(

)

Active mode

fMCLK

f(SMCLK)

MHz

f(ACLK) = 32,768 Hz,

Program executes in Flash VCC = 3 V 300 350

μA

I(AM)

Active

mode

TA = −40°C +85°C,

f f f 4096 Hz

VCC = 2.2 V 3 5

μA

f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz,

Program executes in Flash VCC = 3 V 11 18

μA

I(C Off)

Low power mode (LPM0)

TA = −40°C +85°C,

f0f 1 MHz

VCC = 2.2 V 32 45

μA

I(CPUOff) Low-power mode, (LPM0) f(MCLK) = 0, f(SMCLK) = 1 MHz,

(

ACLK

)

= 32,768 Hz VCC = 3 V 55 70

μA

I()

Low power mode (LPM2)

TA = −40°C +85°C,

f f 0 MHz

VCC = 2.2 V 11 14

μA

I(LPM2) Low-power mode, (LPM2) f(MCLK) = f(SMCLK) = 0 MHz,

(

ACLK

)

= 32,768 Hz, SCG0 = 0 VCC = 3 V 17 22

μA

TA = −40°C 0.8 1.2

TA = 25°CVCC = 2.2 V 0.7 1 μA

I()

Low power mode (LPM3)

TA = 85°C

1.6 2.3

I(LPM3) Low-power mode, (LPM3) TA = −40°C 1.8 2.2

TA = 25°CVCC = 3 V 1.6 1.9 μA

TA = 85°C

2.3 3.4

TA = −40°C 0.1 0.5

I(LPM4) Low-power mode, (LPM4) TA = 25°CVCC = 2.2 V/3 V 0.1 0.5 μA

(LPM4)

p,()

TA = 85°C

0.8 1.9

NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.

current consumption of active mode versus system frequency

IAM = IAM[1 MHz] × fsystem [MHz]

current consumption of active mode versus supply voltage

IAM = IAM[3 V] + 120 μA/V × (VCC−3 V)

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs Port P1 to Port P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7

PARAMETER VCC MIN TYP MAX UNIT

Positive going input threshold voltage

2.2 V 1.1 1.5

VIT+ Positive-going input threshold voltage 3 V 1.5 1.9 V

Negative going input threshold voltage

2.2 V 0.4 0.9

VIT− Negative-going input threshold voltage 3 V 0.9 1.3 V

Input voltage hysteresis (V V )

2.2 V 0.3 1.1

Vhys Input voltage hysteresis, (VIT+ − VIT−)3 V 0.5 1 V

standard inputs − RST/NMI, TEST; JTAG: TCK, TMS, TDI/TCLK

PARAMETER VCC MIN TYP MAX UNIT

VIL Low-level input voltage

2 2 V/3 V

VSS VSS+0.6 V

VIH High-level input voltage 2.2 V/3 V 0.8×VCC VCC V

inputs Px.x, TAx

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Port P1, P2: P1.x to P2.x, External

2.2 V/3 V 1.5 cycle

t(int) External interrupt timing

Port

P2:

External

trigger signal for the interrupt flag,

()

2.2 V 62

(int)

gg g p g,

(see Note 1) 3 V 50 ns

Timer A capture timing

TA0 TA1 TA2

2.2 V 62

t(cap) Timer_A, capture timing TA0, TA1, TA2 3 V 50 ns

Timer_A clock frequenc

TACLK INCLK t =t

2.2 V 8

MHz

f(TAext)

Timer

clock

frequency

externally applied to pin TACLK, INCLK t(H) = t(L) 3 V 10 MHz

Timer A clock frequency

SMCLK or ACLK signal selected

2.2 V 8

MHz

f(TAint) Timer_A clock frequency SMCLK or ACLK signal selected 3 V 10 MHz

NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with

trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in

MCLK cycles.

leakage current (see Notes 1 and 2)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

High impedance leakage current

Port P1: P1.x, 0 ≤ ×≤ 7 2.2 V/3 V ±50

Ilkg(Px.x) High-impedance leakage current Port P2: P2.x, 0 ≤ ×≤ 5 2.2 V/3 V ±50 nA

NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional

pullup or pulldown resistor.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

outputs Port 1 to Port 3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I(OHmax) = −1.5 mA

V22V

See Note 1 VCC−0.25 VCC

High level output voltage

I(OHmax) = −6 mA VCC = 2.2 V See Note 2 VCC−0.6 VCC

VOH High-level output voltage I(OHmax) = −1.5 mA

V3V

See Note 1 VCC−0.25 VCC

I(OHmax) = −6 mA VCC = 3 V See Note 2 VCC−0.6 VCC

I(OLmax) = 1.5 mA

V22V

See Note 1 VSS VSS+0.25

Low level output voltage

I(OLmax) = 6 mA VCC = 2.2 V See Note 2 VSS VSS+0.6

VOL Low-level output voltage I(OLmax) = 1.5 mA

VCC =3V

See Note 1 VSS VSS+0.25 V

I(OLmax) = 6 mA VCC = 3 V See Note 2 VSS VSS+0.6

NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage

drop specified.

2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage

drop specified.

outputs P1.x, P2.x, P3.x, TAx

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

f(P20) P2.0/ACLK; CL = 20 pF 2.2 V/3 V fSystem

f(TAx)

Output frequency TA0, TA1, TA2; CL = 20 pF,

Internal clock source, SMCLK signal applied (see Note 1) 2.2 V/3 V dc fSystem

MHz

fSMCLK = fLFXT1 = fXT1 40% 60%

P1 4/SMCLK

fSMCLK = fLFXT1 = fLF

2 2 V/3 V

35% 65%

P1.4/SMCLK,

CL = 20 pF fSMCLK = fLFXT1/n

V/3

50%−

15 ns 50% 50%+

15 ns

t(Xdc) Duty cycle of O/P

frequency fSMCLK = fDCOCLK 2.2 V/3 V 50%−

15 ns 50% 50%+

15 ns

frequency

P2 0/ACLK

fP20 = fLFXT1 = fXT1 40% 60%

P2.0/ACLK,

20 pF

fP20 = fLFXT1 = fLF 2.2 V/3 V 30% 70%

L =

fP20 = fLFXT1/n 50%

t(TAdc) TA0, TA1, TA2; CL = 20 pF, Duty cycle = 50% 2.2 V/3 V 0±50 ns

NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

outputs − Ports P1, P2, and P3

Figure 2

VOL − Low-Level Output Voltage − V

0.0 0.5 1.0 1.5 2.0 2.5

VCC = 2.2 V

P1.0 TA = 25°C

TA = 85°C

I − Typical Low-Level Output Current − mA

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

Figure 3

VOL − Low-Level Output Voltage − V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VCC = 3 V

P1.0 TA = 25°C

TA = 85°C

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

I − Typical Low-Level Output Current − mA

Figure 4

VOH − High-Level Output Voltage − V

−28

−24

−20

−16

−12

−8

−4

0.0 0.5 1.0 1.5 2.0 2.5

VCC = 2.2 V

P1.0

TA = 25°C

TA = 85°C

I − Typical High-Level Output Current − mA

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

Figure 5

VOH − High-Level Output Voltage − V

−60

−50

−40

−30

−20

−10

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VCC = 3 V

P1.0

TA = 25°C

TA = 85°C

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

I − Typical High-Level Output Current − mA

NOTE: Only one output is loaded at a time.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

USART (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t( )

USART: deglitch time

VCC = 2.2 V 200 430 800

t(τ)USART: deglitch time VCC = 3 V 150 280 500 ns

NOTE 1: The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(τ) to ensure that the URXS

flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to

set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the

URXD line.

wake-up from lower power modes (LPMx)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t(LPM0) VCC = 2.2 V/3 V 100

t(LPM2) VCC = 2.2 V/3 V 100 ns

f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6

t(LPM3)

Delay time (see Note 1)

f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6μs

(LPM3)

Delay time (see Note 1) f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6

f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6

t(LPM4) f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6μs

(LPM4)

f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6

NOTE 1: Parameter applicable only if DCOCLK is used for MCLK.

RAM

PARAMETER MIN NOM MAX UNIT

V(RAMh) CPU halted (see Note 1) 1.6 V

NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program

execution should happen during this supply voltage condition.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Comparator_A (see Note 1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

I()

CAON=1 CARSEL=0 CAREF=0

2.2 V 25 40

μA

I(DD) CAON=1, CARSEL=0, CAREF=0 3 V 45 60 μA

(

Refladder

CAON=1, CARSEL=0,

CAREF 1/2/3 No load at

2.2 V 30 50

μA

I(Refladder/

RefDiode) CAREF=1/2/3, No load at

P2.3/CA0/TA1 and P2.4/CA1/TA2 3 V 45 71 μA

V(IC) Common-mode input voltage CAON =1 2.2 V/3 V 0 VCC−1 V

V(Ref025) Voltage at 0.25 VCC node

VCC

PCA0=1, CARSEL=1, CAREF=1,

No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2

2.2 V/3 V 0.23 0.24 0.25

V(Ref050)

Voltage at 0.5VCC node

VCC

PCA0=1, CARSEL=1, CAREF=2,

No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2

2.2 V/3 V 0.47 0.48 0.5

(see Figure 6 and Figure 7)

PCA0=1, CARSEL=1, CAREF=3,

No load at P2 3/CA0/TA1 and

2.2 V 390 480 540

V(RefVT) (see Figure 6 and Figure 7) No load at P2.3/CA0/TA1 and

P2.4/CA1/TA2, TA = 85°C3 V 400 490 550 mV

V(offset) Offset voltage See Note 2 2.2 V/3 V −30 30 mV

Vhys Input hysteresis CAON=1 2.2 V/3 V 0 0.7 1.4 mV

TA = 25°C, Overdrive 10 mV, 2.2 V 160 210 300

25 C

Overdrive

Without filter: CAF=0 3 V 80 150 240 ns

t(response LH) TA = 25°C, Overdrive 10 mV, 2.2 V 1.4 1.9 3.4

μs

25 C

Overdrive

With filter: CAF=1 3 V 0.9 1.5 2.6 μs

TA = 25°C, 2.2 V 130 210 300

25 C

Overdrive 10 mV, without filter: CAF=0 3 V 80 150 240 ns

t(response HL) TA = 25°C, 2.2 V 1.4 1.9 3.4

μs

25 C

Overdrive 10 mV, with filter: CAF=1 3 V 0.9 1.5 2.6 μs

NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.

The two successive measurements are then summed together.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

TA − Free-Air Temperature − °C

400

450

500

550

600

650

−45 −25 −5 15 35 55 75 95

VCC = 3 V

Figure 6. V

(

RefVT

)

vs Temperature, VCC = 3 V

V(REFVT) − Reference Volts −mV

Typical

Figure 7. V

(

RefVT

)

vs Temperature, VCC = 2.2 V

TA − Free-Air Temperature − °C

400

450

500

550

600

650

−45 −25 −5 15 35 55 75 95

VCC = 2.2 V

V(REFVT) − Reference Volts −mV

Typical

CAON

V+ 0

CAF

Low Pass Filter

τ ≈ 2.0 μs

To Internal

Modules

Set CAIFG

Flag

CAOUT

V−

VCC

0 V

Figure 8. Block Diagram of Comparator_A Module

Overdrive VCAOUT

t(response)

V+

V−

400 mV

Figure 9. Overdrive Definition

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

PUC/POR

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t(POR_Delay) Internal time delay to release POR 150 250 μs

VCC threshold at which POR

TA = −40°C 1.4 1.8 V

VPOR

threshold

which

POR

release delay time begins TA = 25°C 1.1 1.5 V

VPOR

release

delay

time

begins

(see Note 1) TA = 85°CVCC = 2.2 V/3 V 0.8 1.2 V

V(min)

VCC threshold required to

generate a POR (see Note 2) VCC |dV/dt| ≥ 1V/ms 0.2 V

t(reset) RST/NMI low time for PUC/POR Reset is accepted internally 2μs

NOTES: 1. VCC rise time dV/dt ≥ 1V/ms.

2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less

than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms.

VCC

POR

VPOR

(min)

POR

No POR

Figure 10. Power-On Reset (POR) vs Supply Voltage

0.2

0.6

1.0

1.2

1.8

2.0

−40 −20 0 20 40 60 80

Temperature [°C]

V [V]

1.6

1.4

0.8

0.4

1.2

1.5

1.8

0.8

1.1

1.4

25°C

Max

Min

POR

Figure 11. VPOR vs Temperature

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

DCO

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

R 0 DCO 3 MOD 0 DCOR 0 T 25°C

2.2 V 0.08 0.12 0.15

MHz

f(DCO03) Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.08 0.13 0.16 MHz

R 1 DCO 3 MOD 0 DCOR 0 T 25°C

2.2 V 0.14 0.19 0.23

MHz

f(DCO13) Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.14 0.18 0.22 MHz

f(CO )

R=2 DCO=3 MOD=0 DCOR=0 T =25

2.2 V 0.22 0.30 0.36

MHz

f(DCO23) Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C 3 V 0.22 0.28 0.34 MHz

f(CO )

R=3 DCO=3 MOD=0 DCOR=0 T =25

2.2 V 0.37 0.49 0.59

MHz

f(DCO33) Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.37 0.47 0.56 MHz

f(CO )

R=4 DCO=3 MOD=0 DCOR=0 T =25

2.2 V 0.61 0.77 0.93

MHz

f(DCO43) Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.61 0.75 0.9 MHz

f(CO )

R=5 DCO=3 MOD=0 DCOR=0 T =25

2.2 V 1 1.2 1.5

MHz

f(DCO53) Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 1 1.3 1.5 MHz

f(CO )

R=6 DCO=3 MOD=0 DCOR=0 T =25

2.2 V 1.6 1.9 2.2

MHz

f(DCO63) Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 1.69 2 2.29 MHz

f(CO )

R=7 DCO=3 MOD=0 DCOR=0 T =25

2.2 V 2.4 2.9 3.4

MHz

f(DCO73) Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 2.7 3.2 3.65 MHz

f(CO )

R=7 DCO=7 MOD=0 DCOR=0 T =25

2.2 V 4 4.5 4.9

MHz

f(DCO77) Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C3 V 4.4 4.9 5.4 MHz

f(CO )

R=4 DCO=7 MOD=0 DCOR=0 T =25

2 2 V/3 V

MHz

f(DCO47) Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C2.2 V/3 V

FDCO40

x1.7

FDCO40

x2.1

FDCO40

x2.5 MHz

S(Rsel) SR = fRsel+1/fRsel 2.2 V/3 V 1.35 1.65 2

ratio

S(DCO) SDCO = fDCO+1/fDCO 2.2 V/3 V 1.07 1.12 1.16 ratio

Temperature drift R = 4 DCO = 3 MOD = 0 (see Note 1)

2.2 V −0.31 −0.36 −0.40

DtTemperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) 3 V −0.33 −0.38 −0.43 %/°C

Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0

(see Note 1) 2.2 V/3 V 0 5 10 %/V

NOTES: 1. These parameters are not production tested.

ÎÎÎÎÎ

2.2 V 3 V

VCC

Max

Min

Max

Min

f(DCOx7)

f(DCOx0)

Frequency Variance

012 34567

DCO Steps

fDCOCLK

Figure 12. DCO Characteristics

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

main DCO characteristics

DIndividual devices have a minimum and maximum operation frequency. The specified parameters for

f(DCOx0) to f(DCOx7) are valid for all devices.

DAll ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.

DDCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.

DModulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK

cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to:

faverage +32 f(DCO) f(DCO)1)

MOD f(DCO))(32*MOD) f(DCO)1)

DCO when using ROSC (see Note 1)

PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT

f DCO output frequency

l = 4, DCO = 3, MOD = 0, DCOR = 1, 2.2 V 1.8±15% MHz

fDCO, DCO output frequency

Rsel

DCO

MOD

DCOR

TA = 25°C3 V 1.95±15% MHz

Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V ±0.1 %/°C

Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V 10 %/V

NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.

crystal oscillator, LFXT1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input capacitance

XTS=0; LF mode selected.

VCC = 2.2 V / 3 V 12

CXIN Input capacitance XTS=1; XT1 mode selected.

VCC = 2.2 V / 3 V (see Note 1) 2

Output capacitance

XTS=0; LF mode selected.

VCC = 2.2 V / 3 V 12

CXOUT Output capacitance XTS=1; XT1 mode selected.

VCC = 2.2 V / 3 V (see Note 1) 2

VIL

Input levels at XIN

VCC = 2 2 V/3 V (see Note 2)

VSS 0.2×VCC

VIH

Input levels at XIN VCC = 2.2 V/3 V (see Note 2) 0.8×VCC VCC

NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Flash Memory

PARAMETER TEST

CONDITIONS VCC MIN NOM MAX UNIT

VCC(PGM/

ERASE) Program and Erase supply voltage 2.7 3.6 V

fFTG Flash Timing Generator frequency 257 476 kHz

IPGM Supply current from VCC during program 2.7 V/ 3.6 V 3 5 mA

IERASE Supply current from VCC during erase 2.7 V/ 3.6 V 3 7 mA

tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 4 ms

tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms

Program/Erase endurance 104105cycles

tRetention Data retention duration TJ = 25°C 100 years

tWord Word or byte program time 35

tBlock, 0Block program time for 1st byte or word 30

tBlock, 1-63 Block program time for each additional byte or word

see Note 3

tBlock, End Block program end-sequence wait time see Note 3 6tFTG

tMass Erase Mass erase time 5297

tSeg Erase Segment erase time 4819

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To

achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.

(A worst case minimum of 19 cycles are required).

3. These values are hardwired into the Flash Controller’s state machine; tFTG = 1/fFTG.

JTAG Interface

PARAMETER TEST

CONDITIONS VCC MIN NOM MAX UNIT

TCK input frequency

see Note 1

2.2 V 0 5 MHz

fTCK TCK input frequency see Note 1 3 V 0 10 MHz

RInternal Internal pull-down resistance on TEST see Note 2 2.2 V/ 3 V 25 60 90 kΩ

NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.

2. TEST pull-down resistor implemented in all versions.

JTAG Fuse (see Note 1)

PARAMETER TEST

CONDITIONS VCC MIN NOM MAX UNIT

VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V

VFB Voltage level on TEST for fuse-blow 6 7 V

IFB Supply current into TEST during fuse blow 100 mA

tFB Time to blow fuse 1 ms

NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched

to bypass mode.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic

Port P1, P1.0 to P1.3, input/output with Schmitt-trigger

P1.0/TACLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

Interrupt

Edge

Select

Set

P1IE.x

P1IFG.x

P1IRQ.x

Interrupt

Flag P1IES.x

P1SEL.x

Module X IN

P1IN.x

P1OUT.x

Module X OUT

Direction Control

From Module

P1DIR.x

P1SEL.x

Pad Logic

NOTE: x = Bit/identifier, 0 to 3 for port P1

P1Sel.0 P1DIR.0 P1DIR.0 P1OUT.0 VSS P1IN.0 TACLK†P1IE.0 P1IFG.0 P1IES.0

P1Sel.1 P1DIR.1 P1DIR.1 P1OUT.1 Out0 signal†P1IN.1 CCI0A†P1IE.1 P1IFG.1 P1IES.1

P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 signal†P1IN.2 CCI1A†P1IE.2 P1IFG.2 P1IES.2

P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 Out2 signal†P1IN.3 CCI2A†P1IE.3 P1IFG.3 P1IES.3

†Signal from or to Timer_A

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features

P1.4−P1.7

Interrupt

Edge

Select

Set

P1IE.x

P1IFG.x

P1IRQ.x

Interrupt

Flag P1IES.x

P1SEL.x

Module X IN

P1IN.x

P1OUT.x

Module X OUT

Direction Control

From Module

P1DIR.x

P1SEL.x

Pad Logic

Bus Keeper

60 kΩ

Control by

JTAG

TDO

Controlled By JTAG

P1.x

TDI/TCLK P1.x

TST

TMS

TST

TCK

TST

Controlled by JTAG

TST

P1.x

NOTE: The test pin should be protected from potential EMI

and ESD voltage spikes. This may require a smaller

external pulldown resistor in some applications.

x = Bit identifier, 4 to 7 for port P1

During programming activity and during blowing

the fuse, the pin TDO/TDI is used to apply the test

input for JTAG circuitry.

P1.7/TA2/TDO/TDI

P1.6/TA1/TDI/TCLK

P1.5/TA0/TMS

P1.4/SMCLK/TCK

Typical

TEST

Bum

and

Test Fuse

DVCC

P1Sel.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4

P1Sel.5 P1DIR.5 P1DIR.5 P1OUT.5 Out0 signal†P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5

P1Sel.6 P1DIR.6 P1DIR.6 P1OUT.6 Out1 signal†P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6

P1Sel.7 P1DIR.7 P1DIR.7 P1OUT.7 Out2 signal†P1IN.7 unused P1IE.7 P1IFG.7 P1IES.7

†Signal from or to Timer_A

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, P2.0 to P2.2, input/output with Schmitt-trigger

P2.0/ACLK

P2.1/INCLK

P2.2/CAOUT/TA0

Interrupt

Edge

Select

Set

P2IE.x

P2IFG.x

P2IRQ.x

Interrupt

Flag P2IES.x

P2SEL.x

Module X IN

P2IN.x

P2OUT.x

Module X OUT

Direction Control

From Module

P2DIR.x

P2SEL.x

Pad Logic

NOTE: x = Bit identifier, 0 to 2 for port P2

0: Input

1: Output

Bus Keeper

CAPD.X

PnSel.x PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x

P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 unused P2IE.0 P2IFG.0 P1IES.0

P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 VSS P2IN.1 INCLK†P2IE.1 P2IFG.1 P1IES.1

P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 CAOUT P2IN.2 CCI0B†P2IE.2 P2IFG.2 P1IES.2

†Signal from or to Timer_A

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, P2.3 to P2.4, input/output with Schmitt-trigger

P2.3/CA0/TA1

Interrupt

Edge

Select

Set

P2IE.3

P2IFG.3

P2IRQ.3

Interrupt

Flag P2IES.3 P2SEL.3

Module X IN

P2IN.3

P2OUT.3

Module X

OUT

Direction Control

From Module

P2DIR.3

P2SEL.3

Pad Logic

0: Input

1: Output

Bus Keeper

CAPD.3

P2.4/CA1/TA2

Interrupt

Edge

Select

Set

P2IE.4

P2IFG.4

P2IRQ.4

Interrupt

Flag

P2IES.4 P2SEL.4

Module X IN

P2IN.4

P2OUT.4

Module X OUT

Direction Control

From Module

P2DIR.4

P2SEL.4

Pad Logic

0: Input

1: Output

Bus Keeper

CAPD.4

Comparator_A

Reference BlockCAREF

CAREF CAEXP2CA

CAF

CCI1B

0 V

PnSel.x PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x

P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal†P2IN.3 unused P2IE.3 P2IFG.3 P1IES.3

P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal†P2IN.4 unused P2IE.4 P2IFG.4 P1IES.4

†Signal from Timer_A

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module

P2.5/ROSC

Interrupt

Edge

Select

Set

P2IE.5

P2IFG.5

P2IRQ.5

Interrupt

Flag P2IES.5

P2SEL.5

Module X IN

P2IN.5

P2OUT.5

Module X OUT

Direction Control

From Module

P2DIR.5

P2SEL.5 Pad Logic

NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad

Bus Keeper

VCC

Internal to

Basic Clock

Module

DCOR DC

Generator

0: Input

1: Output

CAPD.5

PnSel.x PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x

P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 VSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, unbonded bits P2.6 and P2.7

Interrupt

Edge

Select

Set

P2IE.x

P2IFG.x

P2IRQ.x

Interrupt

Flag P2IES.x

P2SEL.x

Module X IN

P2IN.x

P2OUT.x

Module X OUT

Direction Control

From Module

P2DIR.x

P2SEL.x

Bus Keeper

0: Input

1: Output

Node Is Reset With PUC

PUC

NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins

P2Sel.x P2DIR.x

DIRECTION-

CONTROL

FROM MODULE

P2OUT.x MODULE X OUT P2IN.x MODULE X IN P2IE.x P2IFG.x P2IES.x

P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 VSS P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6

P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 VSS P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7

NOTE: Unbonded bits 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software

interrupts.

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger

P3.0/STE0

P3IN.x

Module X IN

Pad Logic

P3OUT.x

P3DIR.x

P3SEL.x

Module X OUT

Direction Control

From Module

1P3.4/UTXD0

P3.5/URXD0

0: Input

1: Output

x: Bit Identifier, 0 and 4 to 7 for Port P3

P3.6

P3.7

PnSel.x PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x MODULE X OUT PnIN.x MODULE X IN

P3Sel.0 P3DIR.0 VSS P3OUT.0 VSS P3IN.0 STE0

P3Sel.4 P3DIR.4 VCC P3OUT.4 UTXD0†P3IN.4 Unused

P3Sel.5 P3DIR.5 VSS P3OUT.5 VSS P3IN.5 URXD0‡

P3Sel.6 P3DIR.6 VSS P3OUT.6 VSS P3IN.6 Unused

P3Sel.7 P3DIR.7 VSS P3OUT.7 VSS P3IN.7 Unused

†Output from USART0 module

‡Input to USART0 module

port P3, P3.1, input/output with Schmitt-trigger

P3.1/SIMO0

P3IN.1

Pad Logic

P3OUT1

P3DIR.1

P3SEL.1

(SI)MO0

DCM_SIMO

SYNC

STE

STC

From USART0

SI(MO)0

To USART0

0: Input

1: Output

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.2, input/output with Schmitt-trigger

P3.2/SOMI0

P3IN.2

Pad Logic

P3OUT.2

P3DIR.2

P3SEL.2

DCM_SOMI

SYNC

STE

STC

SO(MI)0

From USART0

(SO)MI0

To USART0

0: Input

1: Output

port P3, P3.3, input/output with Schmitt-trigger

P3.3/UCLK0

P3IN.3

Pad Logic

P3OUT.3

P3DIR.3

P3SEL.3

UCLK.0

DCM_UCLK

SYNC

STE

STC

From USART0

UCLK0

To USART0

0: Input

1: Output

NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always

an input.

SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out.

SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).

MSP430x12x

MIXED SIGNAL MICROCONTROLLER

SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

JTAG fuse check mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of

the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check

current, a fuse check current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from from the TEST pin to ground if

the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing

overall system power consumption.

When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense

currents are terminated.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the

TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check

mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the

fuse check mode has the potential to be activated.

The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see

Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default

condition).

Time TMS Goes Low After POR

TMS

ITF

ITEST

Figure 13. Fuse Check Mode Current, MSP430F12x

NOTE:

The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader

access key is used. Also see the bootstrap loader section for more information.

PACKAGE OPTION ADDENDUM

www.ti.com 13-Apr-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430F122IDW ACTIVE SOIC DW 28 20 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F122IDWR ACTIVE SOIC DW 28 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F122IPW ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F122IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F122IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F122IRHBT ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F123CY ACTIVE DIESALE Y 0 Green (RoHS

& no Sb/Br) Call TI N / A for Pkg Type

MSP430F123IDW ACTIVE SOIC DW 28 20 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F123IDWR ACTIVE SOIC DW 28 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F123IPW ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F123IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430F123IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430F123IRHBT ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com 13-Apr-2012

Addendum-Page 2

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

MSP430F122IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1

MSP430F122IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

MSP430F123IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1

MSP430F123IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430F122IDWR SOIC DW 28 1000 367.0 367.0 55.0

MSP430F122IPWR TSSOP PW 28 2000 367.0 367.0 38.0

MSP430F123IDWR SOIC DW 28 1000 367.0 367.0 55.0

MSP430F123IPWR TSSOP PW 28 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

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