24LCS21A-I/P - Microchip Technology

 2003 Microchip Technology Inc. DS21161F-page 1

24LCS21A

Features

• Single supply with operation down to 2.5V

• Completely implements DDC1™/DDC2™

interface for monitor identification, including

recovery to DDC1

• Low-power CMOS technology

- 1 mA typical active current

-10 µA standby current typical at 5.5V

• 2-wire serial interface bus, I2C™ compatible

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Hardware write-protect pin

• Page write buffer for up to eight bytes

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• ESD Protection > 4000V

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges

- Commercial (C): 0°C to +70°C

- Industrial (I): -40°C to +70°C

Description

The Microchip Technology Inc. 24LCS21A is a

128 x 8-bit dual-mode Electrically Erasable PROM.

This device is designed for use in applications

requiring storage and serial transmission of configura-

tion and control informati on. Two modes of operat ion

have been implemented: Transmit-only mode and

Bidirectional mode. Upon power-up, the device will be

in the Transmit-only mode, sending a serial bit stream

of the memo ry array from 00h to 7F h, clocked b y the

VCLK pin. A valid high-to-low transition on the SCL

pin will cause the device to enter the transition mode,

and look for a valid control byte on the I2C bus. If it

detects a valid control byte from the master, it will

switch into Bidirectional mode, with byte selectable

read/w rite capability o f the memory ar ray using SCL.

If no cont rol byte i s received, the device wi ll rever t to

the Transmit-on ly mode a fter i t receiv es 128 c onsec-

utive VCLK pulses while the SCL pin is idle. The

24LCS2 1A also en ables the u ser to write- protect t he

entire memory array using its write-protect pin. The

24LCS2 1A is availa ble in a standard 8-pin PDIP and

SOIC package in both commercial and industrial

temperature ranges.

Package Types

Block Diagram

Pin Function Table

Name Function

WP Write-Protect (active low)

VSS Ground

SDA Serial Address/Data I/O

SCL Serial Clock (Bidirectional mode)

VCLK Serial Clock (Transmit-only mode)

VCC +2.5V to 5.5V Power Supply

NC No Connection

PDIP

SOIC

24LCS21A

Vss

Vcc

VCLK

SCL

SDA

24LCS21A

Vss

Vcc

VCLK

SCL

SDA

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense AMP

R/W Control

Memory

Control

Logic

I/O

Control

Logic

SDA SCL

VCC

VSS

VCLK

1K 2.5V Dual Mode I2C™ Serial EEPROM

DDC is a trademark of the Video Electronics S tandards Assoc.

I2C is a trademark of Philips Corporation.

24LCS21A

DS21161F-page 2  2003 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-65°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to maxim um rating

conditions for extended periods may affect device reliability.

DC CHARACTERISTICS VCC = +2.5V to 5.5V

Commercial (C): TA = 0×C to +70×C

Industrial (I): TA = -40×C to +85×C

Parameter Symbol Min Max Units Conditions

SCL and SDA pins:

High-level in put voltage

Low-level input voltage VIH

VIL 0.7 VCC

——

0.3 VCC V

Input levels on VCLK pin:

High-level in put voltage

Low-level input voltage VIH

VIL 2.0

——

0.2 VCC V

VVCC ≥ 2.7V (Note)

VCC < 2.7V (Note)

Hysteresis of Schmitt Trigger inputs VHYS .05 VCC —V(Note)

Low-level output voltage VOL1—0.4VIOL = 3 mA, VCC = 2.5V (Note)

Low-level output voltage VOL2—0.6VIOL = 6 mA, VCC = 2.5V

Input leakage current ILI —±1µAVIN = 0.1V to VCC

Output lea kage curre nt ILO —±1µAVOUT = 0.1V to VCC

Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note)

TA = 25°C, FCLK = 1 MHz

Operati ng current ICC Write

ICC Read —

—3

1mA

mA VCC = 5.5V

VCC = 5.5V, SCL = 400 kHz

Standby current ICCS —

—30

100 µA

µAVCC = 3.0V, SDA = SCL = VCC

VCC = 5.5V, SDA = SCL = VCC

VCLK = VSS

Note: This parameter is periodically sampled and not 100% tested.

 2003 Microchip Technology Inc. DS21161F-page 3

24LCS21A

TABLE 1-2: AC CHARACTERISTICS

Parameter Symbol Vcc= 2.5 - 4.5V

Standard Mode Vcc= 4.5 - 5.5V

Fast Mod e Units Remarks

Min Max Min Max

Clock frequency FCLK — 100 — 400 kHz

Clock high time THIGH 4000 — 600 — ns

Clock low time TLOW 4700 — 1300 — ns

SDA and SCL rise time TR— 1000 — 300 ns (Note 1)

SDA and SCL fall time TF— 300 — 300 ns (Note 1)

Start condition hold time THD:STA 4000 — 600 — ns After this period the first

clock pulse is generated

Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated

Start condition

Data input hold time THD:DAT 0—0—ns(Note 2)

Data input setup time TSU:DAT 250 — 100 — ns

Stop condition setup time TSU:STO 4000 — 600 — ns

Output valid from clock TAA — 3500 — 900 ns (Note 2)

Bus free time TBUF 4700 — 1300 — ns Time the bus must be free

before a new transmission

can st a rt

Output fall time from VIH

minimum to VIL maximum TOF — 250 20 + 0.1

CB250 ns (Note 1), CB ≤ 100 pF

Input filter spike suppression

(SDA and SCL pins) TSP — 50 — 50 ns (Note 3)

Write cycle time TWR — 10 — 10 ms Byte or Page mo de

Transmit-only Mode Parameters

Output valid from VCLK TVAA — 2000 — 1000 ns

VCLK high time TVHIGH 4000 — 600 — ns

VCLK low time TVLOW 4700 — 1300 — ns

VCLK setup time TVHST 0—0—ns

VCLK hold time TSPVL 4000 — 600 — ns

Mode transition time TVHZ — 1000 — 500 ns

Trans mit -onl y powe r-up tim e TVPU 0—0—ns

Input filter spike suppression

(VCLK pin) TSPV — 100 — 100 ns

Endurance — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block

mode (Note 4)

Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and

spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tes ted but ensured by characteriza tion. For endurance estima tes in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site.

24LCS21A

DS21161F-page 4  2003 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

The 24LCS21A is designed to comply to the DDC

Standard proposed by VESA (Figure 3-3) with the

except ion that it is not Acces s.b us capable. I t ope rate s

in two modes, the Transmit-only mode and the

Bidirect ional m ode. T here is a sep ara te 2-w ire prot ocol

to support each mode, each having a separate clock

input but sharing a common data line (SDA). The

device enters the Transmit-only mode upon power-up.

In this mode, the dev ice t ransm its dat a bit s o n the SD A

pin in response to a clock signal on the VCLK pin. The

device will remain in this mode until a valid high-to-low

transition is placed on the SCL input. When a valid

transition on SCL is recognized, the device will switch

into the Bidirectional mode and look for its control byte

to be sent by the master. If it detects its control byte, it

will stay in the Bidirectional mode. Otherwise, it will

revert to the Transmit-only mode after it sees 128

VCLK pulses.

2.1 Transmit-only Mode

The device will power up in the Transmit-only mode at

address 00H. This mode supports a unidirectional

2-wire protocol for continuous transmission of the

content s of th e memory a rray. This dev ice requi res that

it be initialized prior to valid data being sent in the

Transmit-only mode (Section 2.2 “Initialization Pro-

cedure”). In this mode, data is transmitted on the SDA

pin in 8-bit bytes, with each byte followed by a ninth,

null bit (Fig ure 2-1). The cl ock source for the Transmit-

only mode is provided on the VCLK pin, and a data bit

is output on the rising e dge on this pi n. The eight bi ts in

each byte are transmitted Most Significant bit first.

Each byte within the memory array will be output in

sequence. After address 7Fh in the memory array is

transmitted, the internal address pointers will wrap

aroun d to the first memory location (00h) and c ontinue.

The Bidirectional mode Clock (SCL) pin must be held

high for the device to remain in the Transmit-only

mode.

2.2 Initialization Procedure

After VCC has stabilized, the device will be in the

T ransmit-only mode. Nine clock cycles on the VCLK pin

must be given to the device for it to perform internal

sychronization. During this period, the SDA pin will be

in a high-impedance state. On the rising edge of the

tenth clock cycle, the device will output the first valid

data bit which will be the Most Significant bit in address

00h. (Figure 2-2).

FIGURE 2-1: TRAN SMIT-ONLY MODE

FIGURE 2-2: DEVICE INITIALIZATION

SCL

SDA

VCLK

Tvaa Tvaa

Bit 1 (LSB) Null Bit Bit 1 (MSB) Bit 7

TvlowTvhigh

Tvaa Tvaa

Bit 8 Bit 7High-impedance for 9 clock cycles

Tvpu

12 891011

SCL

SDA

VCLK

Vcc

 2003 Microchip Technology Inc. DS21161F-page 5

24LCS21A

3.0 BIDIRECTIO NAL MO DE

Before the 24LCS21A can be switched into the

Bidirectional mode (Figure 3-1), it must enter the

transiti on mode, which is don e by applying a vali d high-

to-low transition on the Bidirectional mode Clock (SCL).

As soon it en ters the transiti on mode, it looks for a con-

trol byte 1010 000X on the I2C™ bus, and starts to

count pulses on VCLK. Any high-to-low transition on

the SCL line will reset the c ount. If it sees a p ulse cou nt

of 128 on VCLK while the SCL line is idle, it will revert

back to the Transmit-only mode, and transmit its con-

tents starting with the Most Significant bit in address

00h. H owever, if it detec ts the c ontrol byte on the I2C™

bus, (Figure 3-2) it will swit ch to the in th e Bidirectional

mode. Once the device has made the transition to the

Bidirectional mode, the only way to switch the device

back to the Transmit-only mode is to remove power

from the device. The mode transition process is shown

in detail in Figure 3-3.

Once the device has switched into the Bidirectional

mode, the VCLK input is disregarded, with the

exception that a logic high level is required to enable

write capability. This mode supports a two-wire

Bidirectional data transmission protocol (I2C™). In this

protoc ol, a dev ice that sends d ata on the bus is def ined

to be the transmitter, and a device that receives data

from the bus is defined to be the receiver . The bus must

be controlled by a master device that generates the

Bidirecti onal m od e Clo ck (SCL), co ntro ls acces s to th e

bus and generat es the Star t an d Stop condi tio ns, while

the 24LCS21A acts as the slave. Both master and

slave can operate as transmitter or receiver, but the

master device determines which mode is activated. In

the Bidirectional mode, the 24LCS21A only responds

to commands for device 1010 000X.

FIGURE 3-1: MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE

FIGURE 3-2: SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE

TVHZ

SCL

SDA

VCLK

Transmit

Only

MODE Bidirectional Recovery to Transmit-only Mode

Bit8

(MSB of data in 00h)

VCLK count = 1 2 3 4 127 128

Transition Mode with possibility to return to Transmit-only Mode Bidirectional

permanently

SCL

SDAVCLK count = 1 2 n 0

VCLK

Transmit

Only Mode

MODE

S1 0 1 0 0000 ACK

n < 128

24LCS21A

DS21161F-page 6  2003 Microchip Technology Inc.

FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA

Communication

is idle

Is Vsync

present? No

Send EDID continuously

using Vsync as clock

High-to-low

transition on

SCL? No

Yes

Stop sending EDID.

Switch to DDC2 mode.

Display has

transition state

optional

Set Vsync counter = 0

Change on

VCLK lines?

SCL, SDA or

Yes

High - low

transition on SCL

Reset Vsync counter = 0

Yes

Valid

received?

DDC2 address

No VCLK

cycle?

Yes

Increment VCLK counter

Yes

Switch back to DDC1

mode.

DDC2 communication

idle. Display waiting for

address byte.

DDC2B

address

received?

Yes

Receive DDC2B

command

Respond to DDC2B

command

Is display

Access.busTM

Yes

Valid Access.bus

address? No

Yes

See Access.bus

specification to determine

correct procedure.

Yes

The 24LCS21A was designed to

Display Power-on

DDC Circuit Powered

from +5 volts

or start timer

Reset counter or timer

(if appropriate)

Counter=128 or

timer expired?

High-to-low

transition on

SCL?

Yes

comply to the port ion of flowcha rt inside dash box

Note 1: The base flow cha rt is copyri ght  1993, 19 94, 1995 V ideo Elect ronic Standard Associati on (VESA) from

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash box and text “The 24LCS21A and... inside dash box.” are added by Microchip Technology Inc.

3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS21A.

capable?

 2003 Microchip Technology Inc. DS21161F-page 7

24LCS21A

3.1 Bidirectional Mode Bus

Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figur e 3-4).

3.1.1 BUS NOT BUSY (A)

Both data and clock lines remain high.

3.1.2 START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.1.3 STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.1.4 DATA VALID (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of t he cl oc k sig na l. Ther e is one cloc k puls e per

bit of data.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited, although only the last eight will

be stored when doing a write operation. When an

overwri te d oes oc c ur it will repl ac e da t a i n a firs t in firs t

out fashion.

3.1.5 ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The mast er device mus t ge nera te a n ext ra c lock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line du ring the Acknow ledge cl ock pulse in s uch a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by no t g ene rati ng an Acknow led ge bi t o n th e las t

byte that has been clocked out of the slave. In this

case, the slave must leave the data line high to enable

the master to generate the Stop condition.

FIGURE 3-4: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: Onc e switch ed into Bi direction al mode , the

24LCS21A will remain in that mode until

powe r is r e mo ved. Re mo vi ng po we r i s the

only way to reset the 24LCS21A into the

Transmit-only mode.

Note: The 24LCS21A does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

(A) (B) (D) (D) (A)(C)

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL

SDA

24LCS21A

DS21161F-page 8  2003 Microchip Technology Inc.

FIGURE 3-5: BUS TIMING START/STOP

FIGURE 3-6: BUS TIMING DATA

3.1.6 SLAVE ADDRESS

After generating a Start condition, the bus master

transmi ts t he slav e addre ss co nsis ting of a 7 -bit dev ice

code (1010000) for the 24LCS21A.

The eigh th bit of s lave address determin es whether th e

master device wants to read or write to the 24LCS21A

(Figure 3-7).

The 24LCS21A monitors the bus for its corresponding

slave address continuously. It generates an

Ackno w l edg e bi t if the sl av e ad d r es s was tru e an d i t is

not in a programming mode.

FIGURE 3-7: CONTROL BYTE

ALLOCATION

SCL

SDA

START STOP

VHYS TSU:STO

THD:STA

TSU:STA

SCL

SDA

OUT

TSU:STA

TSP

TAA

TLOW

THIGH

THD:STA THD:DAT TSU:DAT TSU:STO

TBUF

TAA

Operation Slave Address R/W

Write 1010000 0

R/W A

1010000

READ/WRITE

START

SLAVE ADDRESS

 2003 Microchip Technology Inc. DS21161F-page 9

24LCS21A

4.0 WRITE OPERATION

4.1 Byte Write

Following the Start signal from the master, the slave

address (fo ur bits), three zero bits (000) and the R/W bit

which is a logic low are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow after it has gener ated an Ackno wledge bit durin g

the ninth clock cycle. Therefore, the next byte

tran smit ted by the ma ster is the word add res s and wi ll

be written into the address pointer of the 24LCS21A.

After receiving another Acknowledge signal from the

24LCS21A the master device will transmit the data

word to be wr itten into the addressed mem ory locatio n.

The 24LCS21A acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle, and during this time the 24LCS21A will not

generate Acknowledge signals (Figure 4-1).

It is required that VCLK be held at a logic high level

during command and data transfer in order to program

the device. This applies to both byte write and page

write operation. Note, however, that the VCLK is

ignored during the self-timed program operation.

Changing VCLK from high-to-low during the self-timed

program operation will not halt programming of the

device.

4.2 Page Write

The write control byte, word address and the first data

byte are tra nsmitted to the 24L CS21A in the same way

as in a byte write. But instead of generating a Stop

conditi on the m aster tran smit s up to eigh t dat a byt es to

the 24LCS21A which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the mas ter has tra nsmit ted a Stop condition. After

the rece ipt of each word, the th ree lowe r order a ddres s

pointer bits are internally incremented by one. The

higher order five bits of the word address remains

const a nt. If the ma ste r s hou ld transmit more tha n eight

words prior to generating the Stop condition, the

address counter will roll over and the previously

receive d dat a will be overwri tten. As w ith the byte w rite

operation, once the Stop condition is received an

internal write cycle will begin (Figure 5-2).

It is required that VCLK be held at a logic high level

during comman d and data transfer in order to program

the device. This applies to both byte write and page

write operation. Note, however, that the VCLK is

ignored during the self-timed program operation.

Changing VCLK from high-to-low during the self-timed

program operation will not halt programming of the

device.

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page,

regardless of the number of bytes ac tua ll y

being written. Physical page boundaries

start at addresses that are integer

multiples of the page buffer size (or ‘page

size’) and end at addresses that are

integer multiples of [page size - 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritte n to th e nex t page as mi ght be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

24LCS21A

DS21161F-page 10  2003 Microchip Technology Inc.

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: VCLK WRITE ENABLE TIMING

BUS ACTIVITY

MASTER

SDA LINE

BUS ACT IV IT Y

CONTROL

BYTE WORD

ADDRESS DATA S

VCLK

SCL

SDA

VCLK

THD:STA TSU:STO

TVHST TSPVL

 2003 Microchip Technology Inc. DS21161F-page 11

24LCS21A

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If the cycle is complete, then the device will return the

ACK and the master can then proceed with the next

Read or Write command. See Figure 5-1 for the flow

diagram.

FIGURE 5-1: ACKNOWLEDGE

POLLING FLOW

FIGURE 5-2: PAG E WRITE

Did Device

Acknowledge

(ACK = 0)?

Send

Write Command

Send St op

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Operation

Yes

SDA LINE

CONTROL

BYTE WORD

ADDRESS

DATA n + 1 DATA n + 7

DATA (n)

VCLK

BUS ACT IV IT Y

MASTER

BUS ACTIVITY

24LCS21A

DS21161F-page 12  2003 Microchip Technology Inc.

6.0 WRITE PROTECTION

When using the 24LCS21A in the Bidirectional mode,

the VCLK pin can be used as a write-protect control

pin. Setting VCLK high allows normal write operations,

while setting VCLK low prev ent s writing to any locatio n

in the array. Connecting the VCLK pin to VSS would

allow the 24LCS21A to operate as a serial ROM,

although this configuration would prevent using the

device in the Transmit-only mode.

Additionally, Pin three performs a flexible write-protect

function. The 24LCS21A contains a write-protection

control fuse whose factory default state is cleared.

Writing any data to address 7Fh (normally the

checksum in DDC applications) sets the fuse which

enables the WP pin. Until this fuse is set, the

24LCS2 1A is alway s write enabled (if VC LK = 1). After

the fuse is set, the write capability of the 24LCS21A is

determined by both VCLK and WP pins (Table 6-1).

TABLE 6-1: WRITE-PROTECT TRUTH

TABLE

7.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There a re three basic types

of read operations: current address read, random read

and sequential read.

7.1 Current Address Read

The 24LCS21A contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous access (either a read or write operation) was

to address n, the next current address read operation

would ac ce ss d at a from a ddress n + 1. U pon rec ei pt of

the slave address with R/W bit set to one, the

24LCS21A issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the tr ansfer but does ge nerate a Stop conditi on and th e

24LCS21A discontinues transmission (Figure 7-1).

FIGURE 7-1: CURRENT ADDRESS

READ

7.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad o peration, first the word ad dres s m us t

be set. This is done b y sending the word address to the

24LCS21A as part of a write operation. After the word

address is sent, the master generat es a Start conditio n

following the acknowledge. This terminates the write

operatio n, but not bef ore the internal addre ss pointe r is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24LCS21A will then

issue an acknowledge and transmits the 8-bit data

word. The m aster wil l not a cknowledg e the tra nsfer b ut

does generate a Stop condition and the 24LCS21A

discontinues transmission (Figure 7-2).

VCLK WP Address

7Fh Written

Mode

for

00h - 7Fh

0 X X Read Only

1 X No R/W

11/open X R/W

1 0 Yes Read Only

CONTROL

BYTE DATA n

BUS ACTIVI TY

SDA LINE

BUS ACTIVI TY A

MASTER

10100001

 2003 Microchip Technology Inc. DS21161F-page 13

24LCS21A

FIGURE 7-2: RANDOM READ

FIGURE 7-3: SEQUENTIAL READ

7.3 Sequential Read

Sequential reads are initiated in the same way as a

random r ead exce pt that after the 24LCS21 A tran smit s

the first data byte, the master issues an acknowledge

as opposed to a Stop condition in a random read. This

direct s the 24LCS21A to transmit the nex t se que ntia lly

addressed 8-bit word (Figure 7-3).

To provi de sequential rea ds the 24LC S21A contai ns an

inter nal address poi nter which i s incremented b y one at

the com ple tio n o f ea ch ope rati on. This address pointer

allows the entire memory contents to be serially read

during one operation.

7.4 Noise Protection

The 24LCS21A employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below 1.5 volts at nominal conditions.

The SDA, SCL and VCLK inputs have Schmitt Trigger

and filte r circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

BUS ACT IV IT Y

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS DATA n

RCONTROL

BYTE

10100000 00000111

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE DATA n DATA n+1 DATA n+2 DATA n+X

24LCS21A

DS21161F-page 14  2003 Microchip Technology Inc.

8.0 PIN DESCRIPTIONS

8.1 SDA

This p in is use d to transfer addresses and data into and

out of th e device, w hen the dev ice is in th e Bidirectional

mode. In the Transmit-only mode, which only allows

data to be read from the device, dat a is also tr ansferred

on the SDA pin. This pin is an open drain terminal,

therefore the SDA bus requires a pull-up resistor to

VCC (typical 10 KΩ for 100 kHz, 1 KΩ for 400 kHz).

For normal data transfer in the Bidirection al mode, SDA

is allowed to change only during SCL low. Changes

during SCL high are reserved for indicating the Start

and Stop conditions.

8.2 SCL

This pin is the clock input for the Bidirectional mode,

and is used to synchronize data transfer to and from the

device. It is also used as the signaling input to switch

the device from the Transmit-only mode to the

Bidirectional mode. It must remain high for the chip to

continue operation in the Transmit-only mode.

8.3 VCLK

This pin is the clock input for the Transmit-only mode

(DDC1). In the Transmit-only mode, each bit is clocked

out on the ris ing edg e of this sign al. In the Bidirecti onal

mode, a high logic level is req uired on this pin to enabl e

write capability.

8.4 WP

This pin is used for flexible write protection of the

24LCS21A. When the last memory location (7Fh) is

written with any data, this pin is enabled and

determines the write capability of the 24LCS21A

(Table 6-1).

The WP pin has an internal pull up resistor which will

all ow w rit e capa bi l ity (as su m in g V CLK = 1) at al l tim es

if this pin is floated.

 2003 Microchip Technology Inc. DS21161F-page 15

24LCS21A

APPENDIX A: REVISION HISTORY

Revision F

Corrections to Section 1.0, Electrical Characteristics.

24LCS21A

DS21161F-page 16  2003 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. F AX: (480) 792-7277

3. The Microchip Worldwide Site (www.micro chip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device 24LCS21A Dual Mode I2C Seria l EEPROM

24LCS21AT Dual Mode I2C Serial EEPROM (Tape and Reel)

Temp er atu re Rang e Blank = 0°C to +70°C

I= -40°C to +85°C

Packag e P = Plastic DIP (300 mi l Body ), 8-le ad

SN = Plastic SOIC (150 mil Body), 8-lead

 2003 Microchip Technology Inc. DS21161F-page 17

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporat ed with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, MPLAB, PIC, PI C m ic ro, PI C START,

PRO MATE and PowerSmart are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,

SEEVAL and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,

SmartSensor , SmartShunt, SmartTel and Total Endurance are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorpora ted in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protect ion features of our

products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such ac t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and M ount ain View, California in M a rch 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, micr operipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

DS21161F-page 18  2003 Microchip Technology Inc.

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