July 2009 Doc ID 14617 Rev 4 1/44
1
VND5E050AJ-E
VND5E050AK-E
Double channel high side driver with analog current sense
for automotive applications
Features
■General
– Inrush current active management by
power limitation
– Very low standby current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
– Very low current sense leakage
■Diagnostic functions
– Proportional load current sense
– High current sense precision for wide
currents range
– Current sense disable
– Off-state open load detection
– Output short to VCC detection
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
■Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Over temperature shutdown with auto
restart (thermal shutdown)
– Reverse battery protected (see Figure 32)
– Electrostatic discharge protection
Applications
■All types of resistive, inductive and capacitive
loads
■Suitable as LED driver
Description
The VND5E050AJ-E and VND5E050AK-E are
double channel high-side drivers manufactured in
the ST proprietary VIPower M0-5 technology and
housed in the tiny PowerSSO-12 and PowerSSO-
24 packages. The VND5E050AJ-E and
VND5E050AK-E are designed to drive 12V
automotive grounded loads delivering protection,
diagnostics and easy 3V and 5V CMOS
compatible interface with any microcontroller.
The devices integrate advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, over-temperature shut-off with
auto-restart and over-voltage active clamp. A
dedicated analog current sense pin is associated
with every output channel in order to provide
Enhanced diagnostic functions including fast
detection of overload and short-circuit to ground
through power limitation indication, over-
temperature indication, short-circuit to Vcc
diagnosis and on & off state open load detection.
The current sensing and diagnostic feedback of
the whole device can be disabled by pulling the
CS_DIS pin high to allow sharing of the external
sense resistor with other similar devices.
Max transient supply voltage VCC 41 V
Operating voltage range VCC 4.5 to 28 V
Max On-state resistance (per ch.) RON 50 mΩ
Current limitation (typ) ILIMH 27 A
Off-state supply current IS2 µA(1)
1. Typical value with all loads connected.
PowerSSO-24
PowerSSO-12
www.st.com
Contents VND5E050AJ-E / VND5E050AK-E
2/44 Doc ID 14617 Rev 4
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 25
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 25
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 26
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 Short to VCC and off-state open load detection . . . . . . . . . . . . . . . . . . 27
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 29
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 PowerSSO-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3 PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4 PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.5 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
VND5E050AJ-E / VND5E050AK-E List of tables
Doc ID 14617 Rev 4 3/44
List of tables
Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Current sense (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Open load detection (8V<VCC<18V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 18. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
List of figures VND5E050AJ-E / VND5E050AK-E
4/44 Doc ID 14617 Rev 4
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Open load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Delay response time between rising edge of output current and rising edge of current sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Off-state open load with external circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. TJ evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 20. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 23. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 24. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 27. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 28. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 31. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 34. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 29
Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 36. Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 30
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 31
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 31
Figure 39. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 40. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 33
Figure 41. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 34
Figure 42. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 34
Figure 43. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 44. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 45. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 46. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 47. PowerSS0-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Block diagram and pin description VND5E050AJ-E / VND5E050AK-E
6/44 Doc ID 14617 Rev 4
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin function
Name Function
VCC Battery connection.
OUTPUT1,2 Power output.
GND Ground connection. Must be reverse battery protected by an external diode/resistor
network.
INPUT1,2
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
CURRENT
SENSE1,2
Analog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
VCC
CH 1
Control & Diagnostic 1
LOGIC
DRIVER
VON
Limitation
Current
Limitation
Power
Clamp
OFF State
Open load
Over
temp.
Undervoltage
VSENSEH
Current
Sense
CH 2
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
IN1
IN2
CS1
CS2
CS_
DIS
GND
OUT2
OUT1
Signal Clamp
CONTROL & DIAGNOSTIC
Channels 2
VND5E050AJ-E / VND5E050AK-E Block diagram and pin description
Doc ID 14617 Rev 4 7/44
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Current sense N.C. Output Input CS_DIS
Floating Not allowed X X X X
To ground Through 1 KΩ
resistor XThrough 22 KΩ
resistor
Through 10 KΩ
resistor
Through 10 KΩ
resistor
PowerSSO-12
TAB = V
cc
V
cc
OUTPUT2
OUTPUT1
OUTPUT1
V
cc
OUTPUT2
12
11
10
9
8
7
1
2
3
4
5
6
CS_DIS
GND
INPUT1
CURRENT SENSE1
INPUT2
CURRENT SENSE2
N.C.
INPUT1
GND
V
CC
N.C.
INPUT2
CS_DIS.
V
CC
CURRENT SENSE1
N.C.
N.C.
CURRENT SENSE2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
PowerSSO-24
TAB = V
CC
Electrical specifications VND5E050AJ-E / VND5E050AK-E
8/44 Doc ID 14617 Rev 4
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VFn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
I
S
I
GND
V
CC
V
CC
V
SENSE2
OUTPUT1
I
OUT1
CURRENT I
SENSE1
INPUT1
I
IN1
V
IN2
V
OUT2
GND
CS_DIS
I
CSD
V
CSD
INPUT2
I
IN2
V
IN1
SENSE1
OUTPUT2
I
OUT2
CURRENT I
SENSE2
SENSE2
V
SENSE1
V
OUT1
V
Fn
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage 0.3 V
-IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
-IOUT Reverse DC output current 20 A
IIN DC input current -1 to 10 mA
ICSD DC current sense disable input current -1 to 10 mA
-ICSENSE DC reverse CS pin current 200 mA
VCSENSE Current sense maximum voltage VCC - 41 to
+VCC
V
VND5E050AJ-E / VND5E050AK-E Electrical specifications
Doc ID 14617 Rev 4 9/44
2.2 Thermal data
2.3 Electrical characteristics
Values specified in this section are for 8 V<VCC<28V; -40°C<T
j<150 °C, unless otherwise
stated.
EMAX
Maximum switching energy (single pulse)
(L= 3mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C; IOUT = IlimL(Typ.))104 mJ
VESD
Electrostatic discharge
(human body model: R=1.5KΩ; C=100pF)
– Input
– Current sense
–CS_DIS
–Output
–V
CC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature - 40 to 150 °C
Tstg Storage temperature - 55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter
Max value
Unit
PowerSSO-12 PowerSSO-24
Rthj-case
Thermal resistance junction-case
(with one channel ON) 2.7 2.7 °C/W
Rthj-amb Thermal resistance junction-ambient See Figure 36 See Figure 40 °C/W
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4.5 13 28 V
VUSD Undervoltage shutdown 3.5 4.5 V
VUSDhyst
Undervoltage shutdown
hysteresis 0.5 V
RON On-state resistance(1)
IOUT= 2A; Tj= 25°C 50
mΩIOUT= 2A; Tj= 150°C 100
IOUT= 2A; VCC= 5V; Tj= 25°C 65
Vclamp Clamp voltage IS= 20mA 41 46 52 V
Electrical specifications VND5E050AJ-E / VND5E050AK-E
10/44 Doc ID 14617 Rev 4
ISSupply current
Off-state; VCC= 13V; Tj= 25°C;
VIN=VOUT=VSENSE=VCSD=0V 2(2) 5(2) µA
On-state; VCC= 13V; VIN= 5V;
IOUT=0A 36mA
IL(off1) Off-state output current
(1)
VIN=VOUT= 0V; VCC= 13V;
Tj=25°C 00.013
µA
VIN=VOUT= 0V; VCC= 13V;
Tj=125°C 05
VF
Output - V
CC
diode voltage
(1)
-IOUT= 4A; Tj= 150°C 0.7 V
1. For each channel.
2. PowerMOS leakage included.
Table 6. Switching (VCC =13V; T
j= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL= 6.5Ω (see Figure 6)20 µs
td(off) Turn-off delay time RL= 6.5Ω (see Figure 6)45 µs
dVOUT/dt(on) Turn-on voltage slope RL= 6.5Ω See
Figure 26 V/µs
dVOUT/dt(off) Turn-off voltage slope RL= 6.5Ω See
Figure 28 V/µs
WON
Switching energy
losses during twon
RL= 6.5Ω (see Figure 6)0.15 mJ
WOFF
Switching energy
losses during twoff
RL= 6.5Ω (see Figure 6)0.3 mJ
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.9 V
IIL Low level input current VIN=0.9V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN=2.1V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
VICL Input clamp voltage IIN=1mA 5.5 7 V
IIN=-1mA -0.7
VCSDL CS_DIS low level voltage 0.9 V
ICSDL
Low level CS_DIS
current VCSD=0.9V 1 µA
Table 5. Power section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VND5E050AJ-E / VND5E050AK-E Electrical specifications
Doc ID 14617 Rev 4 11/44
VCSDH
CS_DIS high level
voltage 2.1 V
ICSDH
High level CS_DIS
current VCSD=2.1V 10 µA
VCSD(hyst)
CS_DIS hysteresis
voltage 0.25 V
VCSCL CS_DIS clamp voltage ICSD=1mA 5.5 7 V
ICSD=-1mA -0.7
Table 8. Protections and diagnostics (1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
IlimH DC short circuit current VCC=13V
5V<VCC< 28V
19 27 38
38
A
A
IlimL
Short circuit current
during thermal cycling VCC= 13V TR<Tj<TTSD 7A
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature TRS+1 TRS+5 °C
TRS Thermal reset of status 135 °C
THYST
Thermal hysteresis
(T
TSD
-T
R
)
7°C
VDEMAG
Turn-off output voltage
clamp IOUT= 2A; VIN=0; L=6mH VCC-41 VCC-46 VCC-52 V
VON
Output voltage drop
limitation
IOUT= 0.1A;
Tj= -40°C...+150°C
(see Figure 8)
25 mV
Table 9. Current sense (8V<VCC<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K0IOUT/ISENSE
IOUT= 0.05A; VSENSE=0.5V;VCSD=0V;
Tj= -40°C...150°C 1440 2250 3630
K1IOUT/ISENSE
IOUT= 1A; VSENSE=4V;VCSD=0V;
Tj= -40°C...150°C
Tj= 25°C...150°C
1740
1750
2070
2070
2820
2562
dK1/K1(1) Current sense ratio
drift
IOUT=1A; VSENSE= 4V;
VCSD=0V;
TJ= -40 °C to 150 °C
-15 15 %
Table 7. Logic inputs (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specifications VND5E050AJ-E / VND5E050AK-E
12/44 Doc ID 14617 Rev 4
K2IOUT/ISENSE
IOUT= 2A; VSENSE= 4V;VCSD= 0V;
Tj= -40°C...150°C
Tj= 25°C...150°C
1900
1899
2000
2000
2395
2282
dK2/K2(1) Current sense ratio
drift
IOUT= 2 A; VSENSE= 4 V;
VCSD=0V;
TJ= -40 °C to 150 °C
-9 9 %
K3IOUT/ISENSE
IOUT= 4A; VSENSE= 4V;VCSD= 0V;
Tj= -40°C...150°C
Tj= 25°C...150°C
1969
1950
1990
1990
2210
2153
dK3/K3(1) Current sense ratio
drift
IOUT= 4 A; VSENSE= 4 V;
VCSD= 0V;
TJ= -40 °C to 150 °C
-6 6 %
ISENSE0
Analog sense
leakage current
IOUT= 0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj= -40°C...150°C
VCSD= 0V; VIN=5V; Tj= -40°C...150°C
0
0
1
2µA
IOUT= 2A; VSENSE= 0V;
VCSD= 5V; VIN= 5V; Tj= -40°C...150°C 01
IOL
Open load on-state
current detection
threshold
VIN = 5V, 8V<VCC<18V
ISENSE= 5 µA 420mA
VSENSE
Max analog sense
output voltage IOUT= 4A; VCSD= 0V 5 V
VSENSEH
Analog sense
output voltage in
fault condition(2)
VCC= 13V; RSENSE= 3.9 KΩ8V
ISENSEH
Analog sense
output current in
fault condition(2)
VCC= 13V; VSENSE= 5V 9 mA
tDSENSE1H
Delay response
time from falling
edge of CS_DIS
pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE= 90% of ISENSEMAX
(see Figure 4)
40 100 µs
tDSENSE1L
Delay response
time from rising
edge of CS_DIS
pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSEMAX
(see Figure 4)
520µs
tDSENSE2H
Delay response
time from rising
edge of INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=90% of ISENSEMAX
(see Figure 4)
80 250 µs
Table 9. Current sense (8V<VCC<18V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VND5E050AJ-E / VND5E050AK-E Electrical specifications
Doc ID 14617 Rev 4 13/44
Figure 4. Current sense delay characteristics
ΔtDSEN
SE
2H
Delay response
time between rising
edge of output
current and rising
edge of current
sense
VSENSE <4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX= 2A (see Figure 7)
40 µs
tDSENSE2L
Delay response
time from falling
edge of INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSEMAX
(see Figure 4)
80 250 µs
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, over temperature and open load off-state detection.
Table 10. Open load detection (8V<VCC<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VOL
Open load off-state
voltage detection
threshold
VIN = 0 V 2 See
Figure 5 4V
tDSTKON
Output short circuit to
VCC detection delay at
turn-off
See Figure 5 180 1200 µs
IL(off2)r
Off-state output current
at VOUT = 4V
VIN=0V; VSENSE=0V
VOUT rising from 0V to 4V -120 0 µA
IL(off2)f
Off-state output current
at VOUT = 2V
VIN=0V; VSENSE=VSENSEH
VOUT falling from VCC to 2V -50 90 µA
td_vol
Delay response from
output rising edge to
VSENSE rising edge in
open load
VOUT= 4 V; VIN= 0V
VSENSE= 90% of VSENSEH
20 µs
Table 9. Current sense (8V<VCC<18V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
SENSE CURRENT
INPUT
LOAD CURRENT
CS_DIS
tDSENSE2H tDSENSE2L
tDSENSE1L tDSENSE1H
Electrical specifications VND5E050AJ-E / VND5E050AK-E
14/44 Doc ID 14617 Rev 4
Figure 5. Open load off-state delay timing
Figure 6. Switching characteristics
VIN
VCS
tDSTKON
OUTPUT STUCK TO VCC
VOUT > VOL
VSENSEH
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10% t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff
VND5E050AJ-E / VND5E050AK-E Electrical specifications
Doc ID 14617 Rev 4 15/44
Figure 7. Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)
Figure 8. Output voltage drop limitation
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90% I
OUTMAX
Δ
t
DSENSE2H
t
t
t
V
on
I
out
V
cc
-V
out
T
j
=150
o
CT
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T)
Electrical specifications VND5E050AJ-E / VND5E050AK-E
16/44 Doc ID 14617 Rev 4
Figure 9. IOUT/ISENSE vs IOUT
Figure 10. Maximum current sense ratio drift vs load current
Note: Parameter guaranteed by design; it is not tested.
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
11,522,533,54
I
OUT
(A)
I
out
/ I
sense
max Tj = -40 °C to 150 °C
max Tj = 25 °C to 150 °C
min Tj = 25 °C to 150 °C
min Tj = -40 °C to 150 °C
typical value
-20
-15
-10
-5
0
5
10
15
20
1234
IOUT (A)
dk/k(%)
VND5E050AJ-E / VND5E050AK-E Electrical specifications
Doc ID 14617 Rev 4 17/44
Table 11. Truth table
Conditions Input Output Sense (VCSD=0V)(1)
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation L
H
L
H
0
Nominal
Overtemperature L
H
L
L
0
VSENSEH
Undervoltage L
H
L
L
0
0
Overload
H
H
X
(no power limitation)
Cycling
(power limitation)
Nominal
VSENSEH
Short circuit to GND
(power limitation)
L
H
L
L
0
VSENSEH
Open load off-state
(with external pull-up) LHV
SENSEH
Short circuit to VCC
(external pull-up
disconnected)
L
H
H
H
VSENSEH
< Nominal
Negative output voltage
clamp LL0
Electrical specifications VND5E050AJ-E / VND5E050AK-E
18/44 Doc ID 14617 Rev 4
Table 12. Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
test pulse
Test levels(1)
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/pulse
repetition time Delays and
Impedance
III IV Min. Max.
1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω
2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω
3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω
3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω
4 -6V -7V 1 pulse 100ms, 0.01Ω
5b(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
+65V +87V 1 pulse 400ms, 2Ω
Table 13. Electrical transient requirements (part 2)
ISO 7637-2:
2004E
test pulse
Test level results
III VI
1C C
2a C C
3a C C
3b C C
4C C
5b(1)
1. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Table 14. Electrical transient requirements (part 3)
Class Contents
C All functions of the device performed as designed after exposure to disturbance.
E
One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the
device.
VND5E050AJ-E / VND5E050AK-E Electrical specifications
Doc ID 14617 Rev 4 19/44
2.4 Waveforms
Figure 11. Normal operation
Figure 12. Overload or short to GND
IOUT
VSENSE
VCS_DIS
INPUT
Nominal load Nominal load
Normal operation
Power Limitation
ILimH >
ILimL >
IOUT
VSENSE
VCS_DIS
INPUT
Thermal cycling
Overload or Short to GND
Electrical specifications VND5E050AJ-E / VND5E050AK-E
20/44 Doc ID 14617 Rev 4
Figure 13. Intermittent overload
Figure 14. Off-state open load with external circuitry
IOUT
VSENSE
VCS_DIS
INPUT
ILimH >Nominal load
Intermittent Overload
ILimL >
Overload
VSENSEH>
INPUT
OFF-State Open Load
with external circuitry
VOL
IOUT
VSENSE
VCS_DIS
VOUT
VOUT > VOL
tDSTK(on)
VSENSEH >
VND5E050AJ-E / VND5E050AK-E Electrical specifications
Doc ID 14617 Rev 4 21/44
Figure 15. Short to VCC
Figure 16. TJ evolution in overload or short to GND
tDSTK(on)
VOUT > VOL
Resistive
Short to VCC
Hard
Short to VCC
Short to VCC
IOUT
VCS_DIS
VOUT
VOL
tDSTK(on)
TTSD
TR
TJ evolution in
Overload or Short to GND
ILimH >
< ILimL
TJ_START
THYST
Power Limitation
Self-limitation of fast thermal transients
INPUT
IOUT
TJ
Electrical specifications VND5E050AJ-E / VND5E050AK-E
22/44 Doc ID 14617 Rev 4
2.5 Electrical characteristics curves
Figure 17. Off-state output current Figure 18. High level input current
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
450
500
550
Iloff (nA)
Off State
Vcc=13V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
Iih (µA)
Vin=2.1V
Figure 19. Input clamp voltage Figure 20. Input low level
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
5,2
5,4
5,6
5,8
6
6,2
6,4
6,6
6,8
7
Vicl (V)
lin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
Vil (V)
Figure 21. Input high level Figure 22. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
Vihyst (V)
VND5E050AJ-E / VND5E050AK-E Electrical specifications
Doc ID 14617 Rev 4 23/44
Figure 23. On-state resistance vs Tcase Figure 24. On-state resistance vs VCC
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
Ron (mOhm)
Iout= 2A
Vcc=13V
0 5 10 15 20 25 30 35 40
Vcc (V)
0
20
40
60
80
100
Ron (mOhm)
Tc=-40°C
Tc=25°C
Tc=125°C
Tc=150°C
Figure 25. Undervoltage shutdown Figure 26. Turn-on voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
2
4
6
8
10
12
14
16
Vusd (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
(dVout/dt )On (V/ms)
Vcc=13V
RI=6.5 Ohm
Figure 27. ILIMH vs Tcase Figure 28. Turn-off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
10
15
20
25
30
35
40
Ilimh (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
450
500
550
600
(dVout/dt )Off (V/ms)
Vcc=13V
RI= 6.5 Ohm
Electrical specifications VND5E050AJ-E / VND5E050AK-E
24/44 Doc ID 14617 Rev 4
Figure 29. CS_DIS high level voltage Figure 30. CS_DIS clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vcsdh (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
9
10
Vcsdcl(V)
Icsd = 1 mA
Figure 31. CS_DIS low level voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
Vcsdl (V)
VND5E050AJ-E / VND5E050AK-E Application information
Doc ID 14617 Rev 4 25/44
3 Application information
Figure 32. Application schematic
Note: Channel 2 has the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600mV / (IS(on)max)
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are on in the case of several
high side drivers sharing the same RGND.
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
Μ
CU
+5V
V
GND
CS_DIS
INPUT
R
prot
R
prot
CURRENT SENSE
R
SENSE
R
prot
C
EXT
Application information VND5E050AJ-E / VND5E050AK-E
26/44 Doc ID 14617 Rev 4
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Section 3.1.2: Solution 2: diode (DGND) in the
ground line.
3.1.2 Solution 2: diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ
Recommended values: Rprot =10kΩ, CEXT=10nF.
3.4 Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
●Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a know ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V
minimum (see parameter VSENSE in Table 9: Current sense (8V<VCC<18V)). The
VND5E050AJ-E / VND5E050AK-E Application information
Doc ID 14617 Rev 4 27/44
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8V<VCC<18V)).
●Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a
maximum current ISENSEH in case of the following fault conditions (refer to ):
– Power limitation activation
– Over-temperature
–Short to V
CC in off-state
– Open load in off-state with additional external components.
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.
Figure 33. Current sense and diagnostic
3.4.1 Short to VCC and off-state open load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
Off-state open load with external circuitry
Detection of an open load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
Main MOSn
41V
OUTn
ILoff2r
RSENSE
RPROT
To uC ADC
RPD
RPU
VPU
Pwr_Lim
VSENSE
PU_CMD
Overtemperature
OL OFF
+
-
VOL
CURRENT
SENSEn
IOUT/KX
ISENSEH
VBAT
ILoff2f
VSENSEH
Load
INPUTn
VCC
GND
CS_DIS
Application information VND5E050AJ-E / VND5E050AK-E
28/44 Doc ID 14617 Rev 4
It is preferable VPU to be switched off during the module stand-by mode in order to avoid the
overall stand-by current consumption to increase in normal conditions, i.e. when load is
connected.
An external pull down resistor RPD connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in off-state (see Figure 33: Current sense and
diagnostic).
RPD must be selected in order to ensure VOUT < VOLmin unless pulled up by the external
circuitry:
RPD ≤ 22 KΩ is recommended.
For proper open load detection in off-state, the external pull-up resistor must be selected
according to the following formula:
For the values of VOLmin,VOLmax, IL(off2)r and IL(off2)f see Table 10: Open load detection
(8V<VCC<18V).
VVIRV OLfoffLPD
OFFupPull
OUT 2
min)2(
_=<⋅=
−
VV
RR
IRRVR
VOL
PDPU
roffLPDPUPUPD
ONupPull
OUT 4
max
)2(
_=>
+
⋅⋅−⋅
=
−
VND5E050AJ-E / VND5E050AK-E Application information
Doc ID 14617 Rev 4 29/44
3.5 Maximum demagnetization energy (VCC = 13.5V)
Figure 34. Maximum turn-off current versus inductance (for each channel)
Note: Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
1
10
100
0,1 1 10 100L (mH)
I (A)
C: Tjstart = 125°C repetitive pulse
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
VIN, IL
A
B
C
Package and PCB thermal data VND5E050AJ-E / VND5E050AK-E
30/44 Doc ID 14617 Rev 4
4 Package and PCB thermal data
4.1 PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 36. Rthj-amb Vs. PCB copper area in open box free air condition (one channel
ON)
30
35
40
45
50
55
60
65
70
0246810
RTHj_amb(°C/ W)
PCB Cu heatsink area (cm^ 2)
VND5E050AJ-E / VND5E050AK-E Package and PCB thermal data
Doc ID 14617 Rev 4 31/44
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON)
Equation 1: pulse calculation formula
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 (a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
0,1
1
10
100
0,0001 0,001 0,01 0,1 1 10 100 1000
Time ( s)
ZTH (°C/ W)
Footprint
8 cm
2
2 cm
2
ZTHδRTH δZTHtp 1δ–()+⋅=
where δtpT⁄=
Package and PCB thermal data VND5E050AJ-E / VND5E050AK-E
32/44 Doc ID 14617 Rev 4
4.2 PowerSSO-24 thermal data
Figure 39. PowerSSO-24 PC board
Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Table 15. Thermal parameters
Area/island (cm2)Footprint28
R1=R7 (°C/W) 0.7
R2=R8 (°C/W) 2.8
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
VND5E050AJ-E / VND5E050AK-E Package and PCB thermal data
Doc ID 14617 Rev 4 33/44
Figure 40. Rthj-amb vs PCB copper area in open box free air condition (one channel
ON)
30
35
40
45
50
55
0246810
RTHj_amb(°C/W)
PCB Cu heatsink area (cm^2)
Package and PCB thermal data VND5E050AJ-E / VND5E050AK-E
34/44 Doc ID 14617 Rev 4
Figure 41. PowerSSO-24 thermal impedance junction ambient single pulse (one
channel ON)
Equation 2: pulse calculation formula
Figure 42. Thermal fitting model of a double channel HSD in PowerSSO-24 (b)
b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
ZTHδRTH δZTHtp 1δ–()+⋅=
where δtpT⁄=
VND5E050AJ-E / VND5E050AK-E Package and PCB thermal data
Doc ID 14617 Rev 4 35/44
Table 16. Thermal parameters
Area / island (cm2)Footprint 2 8
R1= R7 (°C/W) 0.4
R2= R8 (°C/W) 2
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1= C7 (W.s/°C) 0.001
C2= C8 (W.s/°C) 0.0022
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
Package and packing information VND5E050AJ-E / VND5E050AK-E
36/44 Doc ID 14617 Rev 4
5 Package and packing information
5.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2 PowerSSO-12 package information
Figure 43. PowerSSO-12 package dimensions
VND5E050AJ-E / VND5E050AK-E Package and packing information
Doc ID 14617 Rev 4 37/44
Table 17. PowerSSO-12 mechanical data
Symbol
Millimeters
Min. Typ. Max.
A 1.25 1.62
A1 0 0.1
A2 1.10 1.65
B 0.23 0.41
C 0.19 0.25
D4.8 5.0
E3.8 4.0
e0.8
H5.8 6.2
h 0.25 0.5
L 0.4 1.27
k0° 8°
X1.9 2.5
Y3.6 4.2
ddd 0.1
Package and packing information VND5E050AJ-E / VND5E050AK-E
38/44 Doc ID 14617 Rev 4
5.3 PowerSSO-24 package information
Figure 44. PowerSSO-24 package dimensions
VND5E050AJ-E / VND5E050AK-E Package and packing information
Doc ID 14617 Rev 4 39/44
Table 18. PowerSSO-24 mechanical data(1) (2)
1. No intrusion allowed inwards the leads.
2. Flash or bleeds on exposed die pad shall not exceed 0.5 mm per side
Symbol
Millimeters
Min. Typ. Max.
A2.45
A2 2.15 2.35
a1 0 0.1
b0.33 0.51
c0.23 0.32
D(3)
3. “D and E” do not include mold Flash or protusions. Mold Flash or protusions shall not exceed 0.15 mm per
side
10.10 10.50
E(3) 7.40 7.60
e0.8
e3 8.8
F2.3
G0.1
H 10.1 10.5
h0.4
k0° 8°
L0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N10°
X4.1 4.7
Y6.5 7.1
Package and packing information VND5E050AJ-E / VND5E050AK-E
40/44 Doc ID 14617 Rev 4
5.4 PowerSSO-12 packing information
Figure 45. PowerSSO-12 tube shipment (no suffix)
Figure 46. PowerSSO-12 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base q.ty 100
Bulk q.ty 2000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
A
C
B
Base q.ty 2500
Bulk q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape hole spacing P0 (± 0.1) 4
Component spacing P 8
Hole diameter D (± 0.05) 1.5
Hole diameter D1 (min) 1.5
Hole position F (± 0.1) 5.5
Compartment depth K (max) 4.5
Hole spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
VND5E050AJ-E / VND5E050AK-E Package and packing information
Doc ID 14617 Rev 4 41/44
5.5 PowerSSO-24 packing information
Figure 47. PowerSS0-24 tube shipment (no suffix)
Figure 48. PowerSSO-24 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base qty 49
Bulk qty 1225
Tube length (±0.5) 532
A3.5
B13.8
C (±0.1) 0.6
A
C
B
Base qty 1000
Bulk qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape hole spacing P0 (±0.1) 4
Component spacing P 12
Hole diameter D (±0.05) 1.55
Hole diameter D1 (min) 1.5
Hole position F (±0.1) 11.5
Compartment depth K (max) 2.85
Hole spacing P1 (±0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Order codes VND5E050AJ-E / VND5E050AK-E
42/44 Doc ID 14617 Rev 4
6 Order codes
Table 19. Device summary
Package
Order codes
Tube Tape and reel
PowerSSO-12 VND5E050AJ-E VND5E050AJTR-E
PowerSSO-24 VND5E050AK-E VND5E050AKTR-E
VND5E050AJ-E / VND5E050AK-E Revision history
Doc ID 14617 Rev 4 43/44
7 Revision history
Table 20. Document revision history
Date Revision Changes
01-Apr-2008 1 Initial release.
05-Mar-2009 2 Changed Table 18: PowerSSO-24 mechanical data
19-Jun-2009 3
Table 18: PowerSSO-24 mechanical data:
– Changed L (min) value from 0.6 to 0.55
– Changed L (max) value from 1 to 0.85
22-Jul-2009 4 Updated Figure 44: PowerSSO-24 package dimensions.
VND5E050AJ-E / VND5E050AK-E
44/44 Doc ID 14617 Rev 4
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