LTC4211
1
4211fb
TYPICAL APPLICATION
FEATURES DESCRIPTION
Hot Swap Controller with
Multifunction Current Control
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
n Allows Safe Board Insertion and Removal
from a Live Backplane
n Controls Supply Voltages from 2.5V to 16.5V
n Programmable Soft-Start with Inrush Current
Limiting, No External Gate Capacitor Required
n Faster Turn-Off Time Because No External Gate
Capacitor is Required
n Dual Level Overcurrent Fault Protection
n Programmable Response Time for Overcurrent
Protection (MS)
n Programmable Overvoltage Protection (MS)
n Automatic Retry or Latched Mode Operation (MS)
n High Side Drive for an External N-Channel FET
n User-Programmable Supply Voltage Power-Up Rate
n FB Pin Monitors VOUT and Signals RESET
n Glitch Filter Protects Against Spurious RESET Signal
n Electronic Circuit Breaker
n Hot Board Insertion and Removal (Either On
Backplane or On Removable Card)
n Industrial High Side Switch/Circuit Breaker
The LTC
®
4211 is a Hot Swap™ controller that allows a board
to be safely inserted and removed from a live backplane.
An internal high side switch driver controls the gate of an
external N-channel MOSFET for supply voltages ranging
from 2.5V to 16.5V. The LTC4211 provides soft-start and
inrush current limiting during the start-up period which
has a programmable duration.
Two on-chip current limit comparators provide dual level
overcurrent circuit breaker protection. The slow com-
parator trips at VCC – 50mV and activates in 20μs (or is
programmed by an external filter capacitor, MS only).
The fast comparator trips at VCC – 150mV and typically
responds in 300ns.
The FB pin monitors the output supply voltage and signals
the RESET output pin. The ON pin signal turns the chip on
and off and can also be used for the reset function. The
MS package has FAULT and FILTER pins to provide addi-
tional functions like fault indication, autoretry or latch-off
modes, programmable current limit response time and
programmable overvoltage protection using an external
Zener diode clamp.
Single Channel 5V Hot Swap Controller Power-Up Sequence
+
VCC SENSE
LTC4211
8
2
34
76
CLOAD
VOUT
5V
5A
GND
4211 TA01A
5
1
R4
15k
GATE
GNDTIMER
PCB CONNECTION SENSE CTIMER
10nF
FB
ON
SHORT
LONG
VCC
5V
GND LONG
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
RESET
R2
10k
R1
20k
RX
10Ω
RSENSE
0.007Ω
PCB EDGE
CONNECTOR
(MALE) M1
Si4410DY
Z1*
R3
36k
R5
10k
μP
LOGIC
RESET
CX
100nF
BACKPLANE
CONNECTOR
(FEMALE)
4211 TA01b
2.5ms/DIV
NO CLOAD
VGATE
5V/DIV
VRESET
5V/DIV
VON
1V/DIV
VTIMER
1V/DIV
LTC4211
2
4211fb
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(Note 1)
1
2
3
4
8
7
6
5
TOP VIEW
VCC
SENSE
GATE
FB
RESET
ON
TIMER
GND
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 150°C/W
1
2
3
4
RESET
ON
TIMER
GND
8
7
6
5
VCC
SENSE
GATE
FB
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 200°C/W
1
2
3
4
5
RESET
ON
FILTER
TIMER
GND
10
9
8
7
6
FAULT
VCC
SENSE
GATE
FB
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 200°C/W
ORDER INFORMATION
Supply Voltage (VCC) ................................................17V
Input Voltage
FB, ON .................................................. –0.3V to 17V
SENSE, FILTER ........................... –0.3V to VCC + 0.3V
TIMER ...................................................... –0.3V to 2V
Output Voltage
GATE ................................. Internally Limited (Note 3)
RESET, FAULT ....................................... –0.3V to 17V
Operating Temperature Range
LTC4211C ................................................ 0°C to 70°C
LTC4211I ............................................. – 40°C to 85°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4211CS8#PBF LTC4211CS8#TRPBF 4211 8-Lead Plastic SO 0°C to 70°C
LTC4211IS8#PBF LTC4211IS8#TRPBF 4211I 8-Lead Plastic SO –40°C to 85°C
LTC4211CMS8#PBF LTC4211CMS8#TRPBF LTSC 8-Lead Plastic MSOP 0°C to 70°C
LTC4211IMS8#PBF LTC4211IMS8#TRPBF LTSD 8-Lead Plastic MSOP –40°C to 85°C
LTC4211CMS#PBF LTC4211CMS#TRPBF LTSU 10-Lead Plastic MSOP 0°C to 70°C
LTC4211IMS#PBF LTC4211IMS#TRPBF LTSV 10-Lead Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC VCC Supply Voltage Range l2.5 16.5 V
ICC VCC Supply Current FB = High, ON = High, TIMER = Low l1 1.5 mA
VLKO Internal VCC Undervoltage Lockout VCC Low-to-High Transition l2.13 2.3 2.47 V
VLKOHST VCC Undervoltage Lockout Hysteresis 120 mV
IINFB FB Input Current VFB = VCC or GND ±1 ±10 μA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
LTC4211
3
4211fb
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IINON ON Input Current VON = VCC or GND ±1 ±10 μA
ILEAK RESET, FAULT Leakage Current VRESET = VFAULT = 15V, Pull-Down Device Off l±0.1 ±2.5 μA
IINSENSE SENSE Input Current VSENSE = VCC or GND ±1 ±10 μA
VCB(FAST) SENSE Trip Voltage (VCC – VSENSE) Fast Comparator Trips l130 150 170 mV
VCB(SLOW) SENSE Trip Voltage (VCC – VSENSE) Slow Comparator Trips l40 50 60 mV
IGATEUP GATE Pull-Up Current Charge Pump On, VGATE ≤ 0.2V l–12.5 –10 –7.5 μA
IGATEDOWN Normal GATE Pull-Down Current ON Low l130 200 270 μA
Fast GATE Pull-Down Current FAULT Latched and Circuit Breaker Tripped or in
UVLO
50 mA
ΔVGATE External N-Channel Gate Drive VGATE – VCC (For VCC = 2.5V)
VGATE – VCC (For VCC = 2.7V)
VGATE – VCC (For VCC = 3.3V)
VGATE – VCC (For VCC = 5V)
VGATE – VCC (For VCC = 12V)
VGATE – VCC (For VCC = 15V)
l
l
l
l
l
l
2.5
4.5
5.0
10
10
8
8
8
10
16
18
18
V
V
V
V
V
V
VGATEOV GATE Overvoltage Lockout Threshold l0.08 0.2 0.3 V
VFB FB Voltage Threshold FB High to Low l1.223 1.236 1.248 V
ΔVFB FB Threshold Line Regulation 2.5V ≤ VCC ≤ 16.5V l0.5 5 mV
VFBHST FB Voltage Threshold Hysteresis 3mV
VONHI ON Threshold High l1.23 1.316 1.39 V
VONLO ON Threshold Low l1.20 1.236 1.26 V
VONHST ON Hysteresis 80 mV
IFILTER FILTER Current During Slow Fault Condition l–2.5 –2 –1.5 μA
During Normal and Reset Conditions l71013 μA
VFILTER FILTER Threshold Latched Off Threshold, FILTER Low to High l1.20 1.236 1.26 V
VFILTERHST FILTER Threshold Hysteresis 80 mV
ITMR TIMER Current Timer On, VTIMER = 1V l– 2.5 –2 –1.5 μA
Timer Off, TIMER = 1.5V 3 mA
VTMR TIMER Threshold TIMER Low to High l1.20 1.236 1.26 V
TIMER High to Low l0.15 0.200 0.40 V
VFAULT FAULT Threshold Latched Off Threshold, FAULT High to Low l1.20 1.236 1.26 V
VFAULTHST FAULT Threshold Hysteresis 50 mV
VOLFAULT Output Low Voltage IFAULT = 1.6mA l0.14 0.4 V
VOLRESET Output Low Voltage IRESET = 1.6mA l0.14 0.4 V
tFAULTFC FAST COMP Trip to GATE Discharging VCB = 0mV to 200mV Step l300 700 ns
tFAULTSC SLOW COMP Trip to GATE Discharging VCB = 0mV to 100mV Step,
8-Pin Version or FILTER Floating
l10 20 30 μs
VCB = 0mV to 100mV Step,
10nF at FILTER Pin to GND
l468 ms
tEXTFAULT FAULT Low to GATE Discharging VFAULT = 5V to 0V l135 μs
tFILTER FILTER High to FAULT Latched VFILTER = 0V to 5V l2 4.5 7 μs
LTC4211
4
4211fb
TYPICAL PERFORMANCE CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tRESET Circuit Breaker Reset Delay Time ON Low to FAULT High l150 250 μs
tOFF Turn-Off Time ON Low to GATE Off 8 μs
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All current into device pins are positive; all current out of device
pins are negative; all voltages are referenced to ground unless otherwise
specified.
Note 3: An internal Zener at the GATE pin clamps the charge pump voltage
to a typical maximum operating voltage of 26V. External voltage applied to
the GATE pin beyond the internal Zener voltage may damage the part. If a
lower GATE pin voltage is desired, use an external Zener diode. The GATE
capacitance must be <0.15μF at maximum VCC.
Supply Current vs Supply Voltage Supply Current vs Temperature
Undervoltage Lockout Threshold
vs Temperature
ON Pin Threshold
vs Supply Voltage
ON Pin Threshold
vs Temperature GATE Voltage vs Supply Voltage
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
16
4211 G01
4 8 12 20142 6 10 18
TA = 25°C
TEMPERATURE (°C)
–75
SUPPLY CURRENT (mA)
2.0
2.5
3.0
125
4211 G02
1.5
1.0
0–25 25 75
–50 150
050 100
0.5
4.0
3.5
VCC = 15V
VCC = 12V
VCC = 5V
VCC = 3V
TEMPERATURE (°C)
–75
2.0
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.1
2.3
2.4
2.5
–25 25 50 150
4211 G03
2.2
–50 0 75 100 125
FALLING EDGE
RISING EDGE
SUPPLY VOLTAGE (V)
1.10
ON PIN THRESHOLD (V)
1.20
1.30
1.40
1.15
1.25
1.35
4 8 12 16
4211 G04
2020 6 10 14 18
TA = 25°C
HIGH THRESHOLD
LOW THRESHOLD
TEMPERATURE (°C)
–75
1.10
ON PIN THRESHOLD (V)
1.15
1.25
1.30
1.35
–25 25 50 150
4211 G05
1.20
–50 0 75 100 125
1.40 VCC = 5V
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
0
GATE VOLTAGE (V)
10
20
30
5
15
25
4 8 12 16
4211 G06
2020 6 10 14 18
TA = 25°C
LTC4211
5
4211fb
TYPICAL PERFORMANCE CHARACTERISTICS
GATE Voltage vs Temperature VGATE – VCC vs Supply Voltage VGATE – VCC vs Temperature
GATE Output Source Current
vs Supply Voltage
Normal GATE Pull-Down Current
vs Supply Voltage
Normal GATE Pull-Down Current
vs Temperature
Fast GATE Pull-Down Current
vs Supply Voltage
GATE Output Source Current
vs Temperature
Fast GATE Pull-Down Current
vs Temperature
TEMPERATURE (°C)
–75
0
GATE VOLTAGE (V)
5
15
20
25
–25 25 50 150
4211 G07
10
–50 0 75 100 125
30
VCC = 15V
VCC = 12V
VCC = 5V
VCC = 3V
SUPPLY VOLTAGE (V)
0
0
VGATE – VCC (V)
2
6
8
10
12 14 16 18
18
4211 G08
4
246810 20
12
14
16
TA = 25°C
TEMPERATURE (°C)
–75
0
VGATE – VCC (V)
2
6
8
10
75
18
4211 G09
4
0 150
25
–50 100
50
–25 125
12
14
16
VCC = 12V
VCC = 15V VCC = 5V
VCC = 3V
SUPPLY VOLTAGE (V)
7
GATE OUTPUT SOURCE CURRENT (μA)
9
11
13
8
10
12
4 8 12 16
4211 G10
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
7
GATE OUTPUT SOURCE CURRENT (μA)
8
10
11
12
–25 25 50 150
4211 G11
9
–50 0 75 100 125
13
VCC = 15V
VCC = 3V
VCC = 5V
VCC = 12V
SUPPLY VOLTAGE (V)
140
NORMAL GATE PULL-DOWN CURRENT (μA)
180
220
260
160
200
240
4 8 12 16
4211 G12
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
140
NORMAL GATE PULL-DOWN CURRENT (μA)
160
200
220
240
–25 25 50 150
4211 G13
180
–50 0 75 100 125
260 VCC = 5V
SUPPLY VOLTAGE (V)
20
FAST GATE PULL-DOWN CURRENT (mA)
40
60
80
30
50
70
4 8 12 16
4211 G14
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
20
FAST GATE PULL-DOWN CURRENT (mA)
30
50
60
70
–25 25 50 150
4211 G15
40
–50 0 75 100 125
80 VCC = 5V
LTC4211
6
4211fb
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY VOLTAGE (V)
0
FEEDBACK THRESHOLD (V)
1.240
1.245
1.250
16
4211 G16
1.235
1.230
1.225 481221861014 20
TA = 25°C
HIGH THRESHOLD
LOW THRESHOLD
TEMPERATURE (°C)
–75
1.225
FEEDBACK THRESHOLD (V)
1.230
1.240
1.245
1.250
–25 25 50 150
4211 G17
1.235
–50 0 75 100 125
VCC = 5V
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
1.10
FILTER THRESHOLD (V)
1.20
1.30
1.40
1.15
1.25
1.35
4 8 12 16
4211 G18
2020 6 10 14 18
TA = 25°C
HIGH THRESHOLD
LOW THRESHOLD
TEMPERATURE (°C)
–75
1.10
FILTER THRESHOLD (V)
1.15
1.25
1.30
1.35
–25 25 50 150
4211 G19
1.20
–50 0 75 100 125
1.40 VCC = 5V
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
1.7
FILTER PULL-UP CURRENT (μA)
1.9
2.1
2.3
1.8
2.0
2.2
4 8 12 16
4211 G20
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
1.7
FILTER PULL-UP CURRENT (μA)
1.8
2.0
2.1
2.2
–25 25 50 150
4211 G21
1.9
–50 0 75 100 125
2.3 VCC = 5V
SUPPLY VOLTAGE (V)
0
FILTER PULL-DOWN CURRENT (μA)
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
16
4211 G22
4 8 12 20142 6 10 18
TA = 25°C
TEMPERATURE (°C)
–75
FILTER PULL-DOWN CURRENT (μA)
10.0
10.5
11.0
125
4211 G23
9.5
9.0
8.0 –25 25 75
–50 150
050 100
8.5
12.0
11.5
VCC = 5V
SUPPLY VOLTAGE (V)
1.20
TIMER HIGH THRESHOLD (V)
1.22
1.24
1.26
1.21
1.23
1.25
4 8 12 16
4211 G24
2020 6 10 14 18
TA = 25°C
Feedback Threshold
vs Supply Voltage
Feedback Threshold
vs Temperature
FILTER Threshold
vs Supply Voltage
FILTER Threshold vs Temperature
FILTER Pull-Up Current
vs Temperature
FILTER Pull-Down Current
vs Supply Voltage
FILTER Pull-Down Current
vs Temperature
FILTER Pull-Up Current
vs Supply Voltage
TIMER High Threshold
vs Supply Voltage
LTC4211
7
4211fb
TYPICAL PERFORMANCE CHARACTERISTICS
TIMER High Threshold
vs Temperature
TIMER Low Threshold
vs Supply Voltage
TIMER Low Threshold
vs Temperature
TEMPERATURE (°C)
–75
1.20
TIMER HIGH THRESHOLD (V)
1.21
1.23
1.24
1.25
–25 25 50 150
4211 G25
1.22
–50 0 75 100 125
1.26 VCC = 5V
SUPPLY VOLTAGE (V)
0
TIMER LOW THRESHOLD (V)
0.6
0.8
1.0
16
4211 G26
0.4
0.2
04812
218
610 14 20
TA = 25°C
TEMPERATURE (°C)
–75
0
TIMER LOW THRESHOLD (V)
0.2
0.6
0.8
1.0
–25 25 50 150
4211 G27
0.4
–50 0 75 100 125
VCC = 5V
SUPPLY VOLTAGE (V)
1.70
TIMER PULL-UP CURRENT (μA)
1.90
2.10
2.30
1.80
2.00
2.20
4 8 12 16
4211 G28
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
1.7
TIMER PULL-UP CURRENT (μA)
1.8
2.0
2.1
2.2
–25 25 50 150
4211 G29
1.9
–50 0 75 100 125
2.3 VCC = 5V
SUPPLY VOLTAGE (V)
0
TIMER PULL-DOWN CURRENT (mA)
2
4
6
1
3
5
4 8 12 16
4211 G30
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
0
TIMER PULL-DOWN CURRENT (mA)
1
3
4
5
–25 25 50 150
4211 G31
2
–50 0 75 100 125
6VCC = 5V
SUPPLY VOLTAGE (V)
0
VOL (V)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
16
4211 G32
4 8 12 20142 6 10 18
TA = 25°C
RESET OR FAULT
IOL = 5mA
IOL = 1mA
TEMPERATURE (°C)
–75
VOL (V)
0.8
1.0
1.2
125
4211 G33
0.6
0.4
0–25 25 75
–50 150
050 100
0.2
1.6
1.4
VCC = 5V
RESET OR FAULT
IOL = 5mA
IOL = 1mA
TIMER Pull-Up Current
vs Supply Voltage
TIMER Pull-Down Current
vs Supply Voltage
TIMER Pull-Down Current
vs Temperature VOL vs Supply Voltage
TIMER Pull-Up Current
vs Temperature
VOL vs Temperature
LTC4211
8
4211fb
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY VOLTAGE (V)
0
VCB (SLOW COMP) (mV)
52
56
60
16
4211 G34
48
44
50
54
58
46
42
40 42 86 12 14 18
10 20
TA = 25°C
TEMPERATURE (°C)
–75
40
VCB (SLOW COMP) (mV)
42
46
48
50
60
54
–25 25 50 150
4211 G35
44
56
58
52
–50 0 75 100 125
VCC = 5V
SUPPLY VOLTAGE (V)
0
VCB (FAST COMP) (mV)
170
165
160
155
150
145
140
135
130
16
4211 G36
4 8 12 20142 6 10 18
TA = 25°C
TEMPERATURE (°C)
–75
VCB (FAST COMP) (mV)
150
155
160
125
4211 G37
145
140
130 –25 25 75
–50 150
050 100
135
170
165
VCC = 5V
SUPPLY VOLTAGE (V)
0
SLOW COMP RESPONSE TIME (μs)
26
24
22
20
18
16
14
12
10
16
4211 G38
4 8 12 20142 6 10 18
TA = 25°C
8-PIN VERSION
OR FILTER FLOATING
TEMPERATURE (°C)
–75
SLOW COMP RESPONSE TIME (μs)
18
20
22
125
4211 G39
16
14
10 –25 25 75
–50 150
050 100
12
26
24
8-PIN VERSION OR FILTER FLOATING
VCC = 15V
VCC = 3V
VCC = 12V
VCC = 5V
SUPPLY VOLTAGE (V)
0
FAST COMP RESPONSE TIME (ns)
800
700
600
500
400
300
200
100
0
16
4211 G40
4 8 12 20142 6 10 18
TA = 25°C
VCB = 0mV TO 200mV STEP
TEMPERATURE (°C)
–75
FAST COMP RESPONSE TIME (ns)
400
500
600
125
4211 G41
300
200
0–25 25 75
–50 150
050 100
100
800
700
VCB = 0mV TO 200mV STEP
VCC = 15V
VCC = 3V
VCC = 12V
VCC = 5V
SUPPLY VOLTAGE (V)
3.0
FILTER HIGH TO FAULT ACTIVATION TIME (μs)
4.0
5.0
6.0
3.5
4.5
5.5
4 8 12 16
4211 G42
2020 6 10 14 18
TA = 25°C
VCB (SLOW COMP)
vs Supply Voltage
VCB (SLOW COMP)
vs Temperature
VCB (FAST COMP)
vs Supply Voltage
VCB (FAST COMP)
vs Temperature
SLOW COMP Response Time vs
Temperature
FAST COMP Response Time vs
Supply Voltage
SLOW COMP Response Time vs
Supply Voltage
FAST COMP Response Time vs
Temperature
FILTER High to FAULT Activation
Time vs Supply Voltage
LTC4211
9
4211fb
TYPICAL PERFORMANCE CHARACTERISTICS
FILTER High to FAULT Activation
Time vs Temperature
Circuit Breaker RESET Time
vs Supply Voltage
Circuit Breaker RESET Time
vs Temperature
TEMPERATURE (°C)
–75
3.0
FILTER HIGH TO FAULT ACTIVATION TIME (μs)
3.5
4.5
5.0
5.5
–25 25 50 150
4211 G43
4.0
–50 0 75 100 125
6.0 VCC = 5V
SUPPLY VOLTAGE (V)
80
CIRCUIT BREAKER RESET TIME (μs)
120
160
200
100
140
180
4 8 12 16
4211 G44
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
80
CIRCUIT BREAKER RESET TIME (μs)
100
140
160
180
–25 25 50 150
4211 G45
120
–50 0 75 100 125
200 VCC = 5V
SUPPLY VOLTAGE (V)
1.5
FAULT PIN LOW TO GATE DISCHARGING TIME (μs)
2.5
3.5
4.5
2.0
3.0
4.0
4 8 12 16
4211 G46
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
1.5
FAULT PIN LOW TO GATE DISCHARGING TIME (μs)
2.0
3.0
3.5
4.0
–25 25 50 150
4211 G47
2.5
–50 0 75 100 125
4.5 VCC = 5V
SUPPLY VOLTAGE (V)
0
FAULT THRESHOLD VOLTAGE (V)
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
16
4211 G48
4 8 12 20142 6 10 18
TA = 25°C
HIGH THRESHOLD
LOW THRESHOLD
TEMPERATURE (°C)
–75
FAULT THRESHOLD VOLTAGE (V)
1.30
1.35
1.40
125
4211 G49
1.25
1.20
1.10 –25 25 75
–50 150
050 100
1.15
1.50
1.45
VCC = 5V
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
5
TURN OFF TIME (μs)
7
9
11
6
8
10
4 8 12 16
4211 G50
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
5
TURN OFF TIME (μs)
6
8
9
10
–25 25 50 150
4211 G51
7
–50 0 75 100 125
11 VCC = 5V
FAULT Pin Low to GATE Discharging
Time vs Supply Voltage
FAULT Threshold Voltage
vs Supply Voltage
FAULT Threshold Voltage
vs Temperature
FAULT Pin Low to GATE Discharging
Time vs Temperature
Turn Off Time
vs Supply Voltage Turn Off Time vs Temperature
LTC4211
10
4211fb
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY VOLTAGE (V)
0
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
0.3
0.4
0.5
16
4211 G52
0.2
0.1
04812
218
610 14 20
TA = 25°C
TEMPERATURE (°C)
–75
0
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
0.1
0.3
0.4
0.5
–25 25 50 150
4211 G53
0.2
–50 0 75 100 125
VCC = 5V
GATE Overvoltage Lockout Threshold
vs Supply Voltage
GATE Overvoltage Lockout Threshold
vs Temperature
PIN FUNCTIONS
(8-Lead Package/10-Lead Package)
RESET (Pin 1/Pin 1): An open-drain output that pulls to
GND if the voltage at the FB pin (Pin 5/Pin 6) falls below
the FB pin threshold (1.236V). During the start-up cycle,
the RESET pin goes high impedance at the end of the
second timing cycle after the FB pin goes above the FB
threshold. This pin requires an external pull-up resistor
to VCC. If an undervoltage lockout condition occurs, the
RESET pin pulls low independently of the FB pin to prevent
false glitches.
ON (Pin 2/Pin 2): An active high signal used to enable or
disable LTC4211 operation. COMP1’s high-to-low thresh-
old is set at 1.236V and its hysteresis is set at 80mV. If a
logic high signal is applied to the ON pin (VON > 1.316V),
the first timing cycle begins if an overvoltage condition
does not exist on the GATE pin (Pin 6/Pin 7). If a logic
low signal is applied to the ON pin (VON < 1.236V), the
GATE pin is pulled low by an internal 200μA current sink.
The ON pin can also be used to reset the electronic circuit
breaker. If the ON pin is cycled low and then high following
a circuit breaker trip, the internal circuit breaker is reset,
and the LTC4211 begins a new start-up cycle.
TIMER (Pin 3/Pin 4): A capacitor connected from this pin
to GND sets the LTC4211’s system timing. The LTC4211’s
initial and second start-up timing cycles and its internal
“power good” delay time are defined by this capacitor.
GND (Pin 4/Pin 5): Device Ground Connection. Connect
this pin to the system’s analog ground plane.
FB (Pin 5/Pin 6): The FB (Feedback) pin is an input to the
COMP2 comparator and monitors the output supply voltage
through an external resistor divider. If VFB < 1.236V, the
RESET pin pulls low. An internal glitch filter at COMP2’s
output helps prevent negative voltage transients from
triggering a reset condition. If VFB > 1.239V, the RESET
pin goes high at the end of the second timing cycle.
GATE (Pin 6/Pin 7): The output signal at this pin is the
high side gate drive for the external N-channel FET pass
transistor.
As shown in the Block Diagram, an internal charge pump
supplies a 10μA gate current and sufficient gate volt-
age drive to the external FET for supply voltages from
2.5V to 16.5V. The internal charge-pump and zener
LTC4211
11
4211fb
PIN FUNCTIONS
(8-Lead Package/10-Lead Package)
clamps at the GATE pin determine the gate drive voltage
(ΔVGATE = VGATE – VCC). The charge pump produces a
minimum 4.5V of ΔVGATE for supplies in the range of 2.7V
≤ VCC < 4.75V. For 4.75V ≤ VCC ≤ 12V the ΔVGATE is limited
by zener clamp Z1 connected between the GATE and VCC
pins. The ΔVGATE is typically at 12V and with guaranteed
minimum value of 10V. For VCC > 12V, the Zener clamp
Z2 begins to set the limitation for ΔVGATE. Z2 clamps the
gate voltage to ground to 26V typically. The minimum Z2’s
clamp voltage is 23V. This effectively sets ΔVGATE to 8V
minimum at VCC = 15V.
SENSE (Pin 7/Pin 8): Circuit Breaker Set Pin. With a sense
resistor placed in the power path between VCC and SENSE,
the LTC4211’s electronic circuit breaker trips if the voltage
across the sense resistor exceeds the thresholds set inter-
nally for the SLOW COMP and the FAST COMP, as shown
in the Block Diagram. The threshold for the SLOW COMP is
VCB(SLOW) = 50mV, and the electronic circuit breaker trips
if the voltage across the sense resistor exceeds 50mV for
20μs. The SLOW COMP delay is fixed in the S8/MS8 ver-
sion and adjustable in the MS version of the LTC4211. To
adjust the SLOW COMP’s delay, please refer to the section
on Adjusting SLOW COMP’s Response Time.
Under transient conditions where large step current
changes can and do occur over shorter periods of time,
a second (fast) comparator instead trips the electronic
circuit breaker. The threshold for the FAST COMP is set at
VCB(FAST) = 150mV, and the circuit breaker trips if the
voltage across the sense resistor exceeds 150mV for
more than 300ns. The FAST COMP’s delay is fixed in the
LTC4211 and cannot be adjusted. To disable the electronic
circuit breaker, connect the VCC and SENSE pins together.
VCC (Pin 8/Pin 9): This is the positive supply input to
the LTC4211. The LTC4211 operates from 2.5V < VCC <
16.5V, and the supply current is typically 1mA. An internal
undervoltage lockout circuit disables the device until the
voltage at VCC exceeds 2.3V.
FAULT (Not available on S8/MS8, Pin 10 MS): FAULT is
both an input and an output. Connected to this pin are an
analog comparator (COMP6) and an open-drain N-channel
FET. During normal operation, if COMP6 is driven below
1.236V, the electronic circuit breaker trips and the GATE
pin pulls low. Typically, a 10k pull-up resistor connects
to the FAULT pin. This pull-up is required to allow the
LTC4211 to begin a second timing cycle (VFAULT > 1.286)
and start-up properly. This also allows the use of the
FAULT pin as a status output. Under normal operating
conditions, the FAULT output is a logic high. Two condi-
tions cause an active low on FAULT: (1) the LTC4211’s
electronic circuit breaker trips because of an output short
circuit causing a fast output overcurrent transient (FAST
COMP trips circuit breaker); or (2) VFILTER > 1.236V. The
FAULT output is driven to logic low and is latched logic
low until the ON pin is driven to logic low for 150μs (the
tRESET duration).
FILTER (Not available S8/MS8, Pin 3 MS): Overcurrent
Fault Timing Pin and Overvoltage Fault Set pin. With a
capacitor connected from this pin to ground, the SLOW
COMP’s response time can be adjusted. In the S8/MS8
version of the LTC4211, the FILTER pin is not available
and the delay time from overcurrent detect to GATE OFF
is fixed at 20μs.
LTC4211
12
4211fb
BLOCK DIAGRAM
–
+
VREF VREF
–+
+
–+
–
SLOW
COMP
50mV 150mV
0.2V
COMP7
M3
GLITCH FILTER
(SEE NOTE 1)
UVLO
–+
FAST
COMP
–
+
–
+
300ns
DELAY
GLITCH FILTER
150μs
GLITCH FILTER
FUNCTION OF
OVERDRIVE
BG
VREF
0.2V
VREF = 1.236V
CB
TRIPS
OR UVLO ON LOW
START-UP
CURRENT
REGULATOR
GATE
CHARGING
200μA 10μA
POWER BAD
CB TRIPS
VREF
10μA
6 (7)GATE7 (8)SENSE8 (9)VCC
M1
CHARGE
PUMP
Z1
VZ (TYP) = 12V
M2
GND
4 (5)
FAULT
(10)
MS ONLY
–
+
COMP1
2 ON 5 (6) 4211 BD
FB
COMP2
–
+
–
+
COMP3
tTIMER
0.2V
VREF
COMP4
–
+
VREF
COMP5
NORMAL, RESET
NOTE 1: SET BY FILTER CAPACITOR FOR MS
20μs DEFAULT FOR MS8, S8
PIN NUMBERS FOR S8/MS8 (MS)
NORMAL
FAULT
TIMER
3 (4)
FILTER
(3)
MS ONLY
2μA
M6
M5
VCC
2μA
M4
VCC
10μA
LOGIC
RESET
1
COMP6
Z2
VZ (TYP) = 26V
VCC
LTC4211
13
4211fb
OPERATION
+
SENSE
RSENSE
R2
R1 R3
10k
7
VCC
VOUT
8
GATELTC4211
6
2
FB
Q2
GND
ON
4211 F01
1RESET
5
CTIMER
3
TIMER
4
CLOAD
Q1
LOGIC
TIMER 1.236V
REFERENCE
COMP2
μP
RESET
SHORT
LONG
VCC
ON/RESET
GND LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
+
–
VOUT
TIMER
RESET
V2 V2V1V1
1.236V
POWER GOOD
DELAY
1234
4211 F02
Figure 1. Supply Voltage Monitor Block Diagram
Figure 2. Supply Monitor Waveforms in Normal Mode
HOT CIRCUIT INSERTION
When circuit boards are inserted into or removed from
live backplanes, the supply bypass capacitors can draw
huge transient currents from the backplane power bus as
they charge. The transient current can cause permanent
damage to the connector pins as well as cause glitches
on the system supply, causing other boards in the system
to reset.
The LTC4211 is designed to turn a printed circuit board’s
supply voltages ON and OFF in a controlled manner, al-
lowing the circuit board to be safely inserted or removed
from a live backplane. The device provides a system
reset signal to indicate when board supply voltage drops
below a predetermined level, as well as a dual function
fault monitor.
OUTPUT VOLTAGE MONITOR
The LTC4211 uses a 1.236V bandgap reference, precision
voltage comparator and an external resistor divider to
monitor the output supply voltage as shown in Figure 1.
The operation of the supply monitor in normal mode is
illustrated in Figure2. When the voltage at the FB pin
drops below its reset threshold (1.236V), the comparator
COMP2 output goes high. After a glitch filter delay, RESET
is pulled low (Time Point 1). When the voltage at the FB
pin rises above its reset threshold (1.239V), COMP2’s
output goes low and a timing cycle starts (Time Point 4).
After a complete timing cycle, RESET is pulled high by
the external pull-up resistor. If the FB pin rises above the
reset threshold for less than a timing cycle, the RESET
output remains low (Time Points 2 to 3).
As shown in Figure 5, the LTC4211’s RESET pin is logic
low during any undervoltage lockout condition and during
the initial insertion of a PC board. Under normal opera-
tion, RESET goes to logic high at the end of the soft-start
cycle only after the FB pin voltage rises above its reset
threshold of 1.239V.
LTC4211
14
4211fb
OPERATION
UNDERVOLTAGE LOCKOUT
The LTC4211’s power-on reset circuit initializes the start-
up procedure and ensures the chip is in the proper state if
the input supply voltage is too low. If the supply voltage
falls below 2.18V, the LTC4211 is in undervoltage lockout
(UVLO) mode, and the GATE pin is pulled low. Since the
UVLO circuitry uses hysteresis, the chip restarts after the
supply voltage rises above 2.3V and the ON pin goes high.
In addition, users can utilize the ON comparator (COMP1)
or the FAULT comparator (COMP6) to effectively program
a higher undervoltage lockout level. Figure 3 shows how
the external resistor divider at the ON pin programs the
system’s undervoltage lockout voltage. The system will
enter the plug-in cycle after the ON pin rises above 1.316V.
The resistor divider sets the circuit to turn on when VCC
reaches around 79% of its final value. If a different turn on
VCC voltage is desired change the resistor divider values
accordingly. Alternatively, the FAULT comparator can be
used to configure the external undervoltage lockout level.
If the FAULT comparator is used for this purpose, the
system will wait for the input voltage to increase above
the level set by the user before starting the second timing
cycle. Also, if the input voltage drops below the set level
in normal operating mode, the user must cycle the ON pin
or VCC to restart the system.
GLITCH FILTER FOR RESET
The LTC4211 has a glitch filter to prevent transients on the
FB pin from generating a system reset. The relationship
between glitch filter time and the FB transient voltage is
shown in Figure 4.
Figure 4. FB Comparator Glitch Filter Time
vs Feedback Transient Voltage
Figure 3. ON Pin Sets the Undervoltage
Lockout Voltage Externally
SYSTEM TIMING
System timing for the LTC4211 is generated at the TIMER
pin (see the Block Diagram). If the LTC4211’s internal
timing circuit is off, an internal N-channel FET connects
the TIMER pin to GND. If the timing circuit is enabled,
an internal 2μA current source is then connected to the
TIMER pin to charge CTIMER at a rate given by Equation 1:
C
TIMER
Charge-Up Rate =2µA
C
TIMER
(1)
When the TIMER pin voltage reaches COMP4’s threshold
of 1.236V, the TIMER pin is reset to GND. Equation 2 gives
an expression for the timer period:
t
TIMER
=1.236V • C
TIMER
2µA
(2)
As a design aid, the LTC4211’s timer period as a function
of the CTIMER using standard values from 3.3nF to 0.33μF
is shown in Table 1.
VIN
3.3V
R1
10k
R2
10k
ON PIN
(a) 3.3VIN
VIN
5V
R1
20k
R2
10k
ON PIN
(b) 5VIN
VIN
12V
R1
61.9k
R2
10k
ON PIN
(c) 12VIN
4211 F03
FB TRANSIENT (mV)
0
GLITCH FILTER TIME (μs)
150
200
250
160
4211 F04
100
50
040 80 12020 18060 100 140 200
TA = 25°C
LTC4211
15
4211fb
OPERATION
The CTIMER value is vital to ensure a proper start-up and
reliable operation. A system may not start up if a timing
period is set too short relative to the time needed for the
output voltage to ramp up from zero to its rated value.
Conversely, this timing period should not be too long as
an output short can occur at start-up causing the exter-
nal MOSFET to overheat. A good starting point is to set
CTIMER = 10nF and adjust its value accordingly to suit the
specific applications.
OPERATING SEQUENCE
Power-Up, Start-Up Check and Plug-In Timing Cycle
The sequence of operation for the LTC4211 is illustrated
in the timing diagram of Figure 5. When a PC board is
inserted into a live backplane, the LTC4211 first performs
Figure 5. Normal Power-Up Sequence
VCC
ON
2μA 2μA
10μA
PLUG-IN CYCLE
FIRST TIMING CYCLE
200μA
POWER
GOOD
(VFB > VREF)
VTMR = VREF
TIMER
12 345 6 7 8 9
RESET PULLED LOW DUE TO POWER BAD
10
SLOW COMPARATOR ARMEDCHECK FOR GATE < 0.2V
FAST COMPARATOR ARMED
CHECK FOR FILTER LOW (<VREF – 80mV)
CHECK FOR FAULT HIGH (>VREF + 50mV)
ON GOES LOW
GATE
VOUT
RESET
POWER BAD
(VFB < VREF)
SOFT-START CYCLE
SECOND TIMING CYCLE
4211 F05
Table 1. tTIMER vs CTIMER
CTIMER tTIMER
0.0033μF 2.0ms
0.0047μF 2.9ms
0.0068μF 4.2ms
0.0082μF 5.1ms
0.01μF 6.2ms
0.015μF 9.3ms
0.022μF 13.6ms
0.033μF 20.4ms
0.047μF 29.0ms
0.068μF 42.0ms
0.082μF 50.7ms
0.1μF 61.8ms
0.15μF 92.7ms
0.22μF 136ms
0.33μF 204ms
LTC4211
16
4211fb
OPERATION
a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass tran-
sistor is pulled to ground by the internal 200μA current
source connected at the GATE pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4211 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10μA current source.
Once VCC and ON (the ON pin is >1.316) are valid, the
LTC4211 checks to make sure that GATE is OFF (VGATE <
0.2V) at Time Point 2. An internal timing circuit is enabled
and the TIMER pin voltage ramps up at the rate described by
Equation 1. At Time Point 3 (the timing period programmed
by CTIMER), the TIMER pin voltage equals VTMR (1.236V).
Next, the TIMER pin voltage ramps down to Time Point 4
where the LTC4211 performs two checks: (1) FILTER pin
voltage is low (VFILTER < 1.156V) and (2) FAULT pin volt-
age is high (VFAULT > 1.286V). If both conditions are met,
the LTC4211 begins a second timing (soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point5),
the LTC4211’s FAST COMP is armed and an internal 10μA
current source working with an internal charge pump
provides the gate drive to the external pass transistor.
The
LTC4211 automatically limits the inrush current in one of
two ways: by controlling the GATE pin voltage slew rate
or by actively limiting the inrush current. If GATE voltage
slew rate control is preferred, an external capacitor CGATE
can be used from GATE to ground, as shown in Figure 6.
An expression for the GATE voltage slew rate is given by
Equation 3:
VGATE Slew Rate, dVGATE
dt =10µA
CGATE
(3)
Adding CGATE slows the GATE voltage slew rate at the ex-
pense of slower system turn-on and turn-off time. Should
this technique be used, values for CGATE less than 150nF
are recommended.
The inrush current being delivered to the load while
the GATE is ramping is dependent on CLOAD and CGATE.
Equation 4 gives an expression for the inrush current
during the second timing cycle:
I
INRUSH
=dV
GATE
dt •C
LOAD
=10µA • C
LOAD
C
GATE
(4)
For example, if CGATE = 3300pF and CLOAD = 2000μF, the
inrush current charging CLOAD is:
IINRUSH =10µA • 2000µF
0.0033µF =6.06A
(5)
At Time Point 6, the output voltage trips COMP2’s thresh-
old, signaling an output voltage “power good” condition.
At Time Point 7, RESET is asserted high, SLOW COMP is
armed and the LTC4211 enters a fault monitor mode. The
TIMER voltage then ramps down to Time Point 8.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (VON < 1.236V). The GATE pin
voltage is ramped to ground by the internal 200μA cur-
rent source, discharging CGATE and turning off the pass
transistor. As CLOAD discharges, the output voltage crosses
COMP2’s threshold, signaling a “power bad” condition at
Time Point 10. At this point, RESET is asserted low.
Figure 6. Using an External Capacitor at GATE for
GATE Voltage Slew Rate Control
M1
Si4410DY
RSENSE
0.007Ω
CGATE*
CLOAD
4211 F06
+
VCC SENSE
LTC4211**
GATE
FB
R1
36k
VOUT
5V
5A
VIN
5V
R2
15k
*
**
VALUES ≤150nF SUGGESTED
ADDITIONAL DETAILS OMITTED
FOR CLARITY =
dVGATE
dt
VGATE SLEW RATE CONTROL
10μA
CGATE
()
LTC4211
17
4211fb
OPERATION
SOFT-START WITH CURRENT LIMITING
During the second timing cycle, the inrush current was
described by Equation 4. Note that there is a one-to-one
correspondence in the inrush current to CLOAD. If the inrush
current is large enough to cause a voltage drop greater
than 50mV across the sense resistor, an internal servo
loop controls the operation of the 10μA current source at
the GATE pin to regulate the load current to:
ILIMIT(SOFTSTART) =50mV
RSENSE
(6)
For example, the inrush current is limited to 5A when
RSENSE = 0.01Ω.
In this fashion, the inrush current is controlled and CLOAD
is charged up slowly during the soft-start cycle.
The timing diagram in Figure 7 illustrates the operation
of the LTC4211 in a normal power-up sequence with lim-
ited inrush current as described by Equation 6. At Time
Point5, the GATE pin voltage begins to ramp and the power
MOSFET starts to charge CLOAD. At Time Point 5A, the inrush
current causes a 50mV voltage drop across RSENSE and
the internal servo loop engages, limiting the inrush cur-
rent to a fixed level. At Time Point 6, the GATE pin voltage
continues to ramp as CLOAD charges until VOUT reaches its
final value. The charging current reduces, and the internal
servo loop disengages. At the end of the soft-start cycle
(Time Point 7), RESET is high and SLOW COMP is armed.
Figure 7. Normal Power-Up Sequence (with Current Limiting in Second Timing Cycle)
PLUG-IN CYCLE
FIRST TIMING CYCLE
TIMER
ON
VCC
12 345 6 7 8 9
RESET PULLED LOW DUE TO POWER BAD
10
200μA
4211 F07
2μA2μA
VREF
10μA
GATE
VOUT
POWER BAD
VFB < VREF
5A
SLOW COMPARATOR ARMEDCHECK FOR GATE < 0.2V
FAST COMPARATOR ARMED
CHECK FOR FILTER LOW (<VREF – 80mV)
CHECK FOR FAULT HIGH (>VREF + 50mV)
ON GOES LOW
GATE
VOUT
ILOAD
RESET
SOFT-START CYCLE
SECOND TIMING CYCLE
POWER GOOD
VFB > VREF
LOAD CURRENT IS
REGULATING AT 50mV/RSENSE
LTC4211
18
4211fb
OPERATION
breaker if the voltage across the SENSE resistor (VCC –
VSENSE = VCB) is greater than 50mV for 20μs. There may
be applications where this comparator’s response time
is not long enough, for example, because of excessive
supply voltage noise. To adjust the response time of the
SLOW COMP, the MS version of the LTC4211 is chosen
and a capacitor is used at the LTC4211’s FILTER pin (see
section on Adjusting SLOW Comp’s Response Time). The
FAST COMP trips the circuit breaker to protect against fast
load overcurrents if the transient voltage across the sense
resistor is greater than 150mV for 300ns. The response
time of the LTC4211’s FAST COMP is fixed.
The timing diagram of Figure 7 illustrates when the
LTC4211’s electronic circuit breaker is armed. After the
first timing cycle, the LTC4211’s FAST COMP is armed
at Time Point 5. Arming FAST COMP at Time Point 5 en-
sures that the system is protected against a short-circuit
condition during the second timing cycle. At Time Point 7,
SLOW COMP is armed when the internal control loop is
disengaged.
The timing diagrams in Figures 8 and 9 illustrate the op-
eration of the LTC4211 when the load current conditions
exceed the thresholds of the FAST COMP (VCB(FAST) >
150mV) and SLOW COMP (VCB(SLOW) > 50mV), respec-
tively.
RESETTING THE ELECTRONIC CIRCUIT BREAKER
Once the LTC4211’s circuit breaker is tripped, FAULT is
asserted low and the GATE pin is pulled to ground. The
LTC4211 remains latched OFF in this fault state until the
external fault is cleared. To clear the internal fault detect
circuitry and to restart the LTC4211, its ON pin must be
driven low (VON < 1.236V) for at least 150μs, after which
time FAULT goes high. Toggling the ON pin from low to
high (VON > 1.316V) initiates a restart sequence in the
LTC4211. The timing diagram in Figure 10 illustrates a
start-up sequence where the LTC4211 is powered up into
a load overcurrent condition. Note that the circuit breaker
trips at Time Point B and is reset at Time Point 9A.
FREQUENCY COMPENSATION AT SOFT-START
If the external gate capacitance is greater than 600pF, no
external gate capacitor is required at GATE to stabilize
the internal current-limiting loop during soft-start. Oth-
erwise, connect a gate capacitor between the GATE pin
and ground to increase the total gate capacitance to be
equal to or above 600pF. The servo loop that controls the
external MOSFET during current limiting has a unity-gain
frequency of about 105kHz and phase margin of 80° for
external MOSFET gate input capacitances to 2.5nF.
USING AN EXTERNAL GATE CAPACITOR
In addition to reducing the inrush current (Equation 4), an
external gate capacitor (Figure 6) may also be useful to
decrease or eliminate current spikes through the MOSFET
when power is first applied. At power-up, the instantaneous
input voltage step attempts to pull the MOSFET gate up
through the MOSFET’s drain-to-gate capacitance. If the
MOSFET’s CGS is small, the gate can be pulled up high
enough to turn on the MOSFET, thereby allowing a cur-
rent spike to the output. This event occurs during the time
that the LTC4211 is coming out of UVLO and getting its
intelligence to hold the GATE pin low. An external capaci-
tor attenuates the voltage to which the GATE is pulled up
and eliminates the current spike. The value required is
dependent on the MOSFET capacitance specifications. In
typical applications, this capacitor is not required.
ELECTRONIC CIRCUIT BREAKER
The LTC4211 features an electronic circuit breaker function
that protects against externally-generated fault conditions
and shorts or excessive load current and can also be con-
figured to protect against input supply overvoltage. If the
circuit breaker trips, the GATE pin is immediately pulled to
ground, the external N-channel MOSFET is quickly turned
OFF and FAULT is latched low.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, set by the
LTC4211’s SLOW COMP and FAST COMP thresholds
(see Block Diagram). The SLOW COMP trips the circuit
LTC4211
19
4211fb
OPERATION
GATE
TIMER
VCC ON
12 345 6 78
GATE
VOUT
A
SHORT CIRCUIT RESET PULLED LOW DUE TO POWER BAD
B C
SLOW COMPARATOR ARMED
CIRCUIT BREAKER TRIPS
FAST COMPARATOR ARMED
VOUT
VCC – VSENSE
FAULT
RESET
POWER GOOD
VFB > VREF
POWER BAD
VFB < VREF
FPD
>150mV
4211 F08
300ns
TYP
Figure 8. Output Short Circuit Causes Fast Comparator to Trip the Circuit Breaker
LTC4211
20
4211fb
OPERATION
GATE
TIMER
VCC
12 3 45 6 7 8 A
OVER CURRENT RESET PULLED LOW DUE TO POWER BAD
B C
FAST COMPARATOR ARMED
CIRCUIT BREAKER TRIPS
CIRCUIT BREAKER TRIPS
10μA
2μA
VREF
POWER BAD
VFB < VREF
FPD
GATE
VOUT
>50mV
4211 F09
SLOW COMPARATOR ARMED
VOUT
VCC – VSENSE
FILTER
FAULT
RESET
ON
POWER GOOD
VFB > VREF
Figure 9. Mild Overcurrent Slow Comparator Trips the Circuit Breaker After Filter Programming Period
LTC4211
21
4211fb
OPERATION
GATE
TIMER
VCC
12 3 45 6
GATE
VFB < VREF
>50mV
VREF
10μA
4211 F10
tRESET
tFAULTSC
2μA
FPD
VOUT
78 B 9 9A 1
FAST COMPARATOR ARMED
CIRCUIT BREAKER TRIPS
CIRCUIT BREAKER RESET
SLOW COMPARATOR ARMED
VOUT
VCC – VSENSE
FILTER
FAULT
RESET
ON ONON
VSENSE = 50mV
REGULATING
LOAD CURRENT
Figure 10. Power-Up in Overcurrent, Slow Comparator Trips the Circuit Breaker
ADJUSTING SLOW COMP’S RESPONSE TIME
The response time of SLOW COMP is adjusted using a
capacitor connected from the LTC4211’s FILTER pin to
ground. If this pin is left unused, SLOW COMP’s delay
defaults to 20μs. During normal operation, the FILTER
output pin is held low as an internal 10μA pull-down
current source is connected to this pin by transistor M4.
This pull-down current source is turned off when an
overcurrent load condition is detected by SLOW COMP.
During an overcurrent condition, the internal 2μA pull-
up current source is connected to the FILTER pin by
transistor M5, thereby charging CFILTER. As the charge
on the capacitor accumulates, the voltage across CFILTER
increases. Once the FILTER pin voltage increases to 1.236V,
the electronic circuit breaker trips and the LTC4211’s
GATE pin is switched quickly to ground by transistor M3.
After the circuit breaker is tripped, M5 is turned OFF, M4
is turned ON and the 10μA pull-down current then holds
the FILTER pin voltage low.
The SLOW COMP response time from an overcurrent fault
condition to when the circuit breaker trips (GATE OFF) is
given by Equation 7:
tSLOWCOMP =1.236V • CFILTER
2µA +20µs
(7)
For example, if CFILTER = 1000pF, SLOW COMP’s response
time = 638μs. As a design aid, SLOW COMP’s delay time
(tSLOW COMP) versus CFILTER for standard values of CFILTER
from 100pF to 1000pF is illustrated in Table 2.
LTC4211
22
4211fb
OPERATION
SENSE RESISTOR CONSIDERATIONS
The fault current level at which the LTC4211’s internal
electronic circuit breaker trips is determined by a sense
resistor connected between the LTC4211’s VCC and SENSE
pins and two separate trip points. The first trip point is
set by the SLOW COMP’s threshold, VCB(SLOW) = 50mV,
and occurs should a load current fault condition exist for
more than 20μs. The current level at which the electronic
circuit breaker trips is given by Equation 8:
ITRIP(SLOW) =
VCB(SLOW)
RSENSE
=50mV
RSENSE
(8)
The second trip point is set by the FAST COMP’s threshold,
VCB(FAST) = 150mV, and occurs during fast load current
transients that exist for 300ns or longer. The current level
at which the circuit breaker trips in this case is given by
Equation 9:
I
TRIP(FAST)
=
V
CB(FAST)
R
SENSE
=150mV
R
SENSE
(9)
As a design aid, the currents at which the electronic circuit
breaker trips for common values for RSENSE are shown
in Table 3.
Figure 11. Making PCB Connections to the Sense Resistor
Table 2. tSLOWCOMP vs CFILTER
CFILTER tSLOWCOMP
100pF 82μs
220pF 156μs
330pF 224μs
470pF 310μs
680pF 440μs
820pF 527μs
1000pF 638μs
Table 3. ITRIP(SLOW) and ITRIP(FAST) vs RSENSE
RSENSE ITRIP(SLOW) ITRIP(FAST)
0.005Ω 10A 30A
0.006Ω 8.3A 25A
0.007Ω 7.1A 21A
0.008Ω 6.3A 19A
0.009Ω 5.6A 17A
0.01Ω 5A 15A
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4211’s
VCC and SENSE pins are strongly recommended. The
drawing in Figure 11 illustrates the correct way of making
connections between the LTC4211 and the sense resis-
tor. PCB layout should be balanced and symmetrical to
minimize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
The power rating of the sense resistor should accommodate
steady-state fault current levels so that the component is
not damaged before the circuit breaker trips. Table4 in
the Appendix lists sense resistors that can be used with
the LTC4211’s circuit breaker.
IRC-TT SENSE RESISTOR
LR251201R010F
OR EQUIVALENT
0.01, 1%, 1W
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
TO
VCC
TO
SENSE
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
4211 F11
CALCULATING CIRCUIT BREAKER TRIP CURRENT
For a selected RSENSE value, the nominal load current that
trips the circuit breaker is given by Equation 10:
(10)
The minimum load current that trips the circuit breaker is
given by Equation 11.
ITRIP(MIN) =
VCB(MIN)
RSENSE(MAX)
=40mV
RSENSE(MAX)
(11)
where
RSENSE(MAX) =RSENSE(NOM) s1+RTOL
100
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
LTC4211
23
4211fb
OPERATION
The maximum load current that trips the circuit breaker
is given in Equation 12.
ITRIP(MAX) =
VCB(MAX)
RSENSE(MIN)
=60mV
RSENSE(MIN)
(12)
where
RSENSE(MIN) =RSENSE(NOM) s1– RTOL
100
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
For example:
If a sense resistor with 7mΩ ±5% RTOL is used for current
limiting, the nominal trip current ITRIP(NOM) = 7.1A. From
Equations 11 and 12, ITRIP(MIN) = 5.4A and ITRIP(MAX) =
9.02A respectively.
For proper operation and to avoid the circuit breaker trip-
ping unnecessarily, the minimum trip current (ITRIP(MIN))
must exceed the circuit’s maximum operating load current.
For reliability purposes, the operation at the maximum
trip current (ITRIP(MAX)) must be evaluated carefully. If
necessary, two resistors with the same RTOL can be con-
nected in parallel to yield an RSENSE(NOM) value that fits
the circuit requirements.
POWER MOSFET SELECTION CRITERIA
To start the power MOSFET selection process, choose the
maximum drain-to-source voltage, VDS(MAX), and the maxi-
mum drain current, ID(MAX) of the MOSFET. The VDS(MAX)
rating must exceed the maximum input supply voltage
(including surges, spikes, ringing, etc.) and the ID(MAX)
rating must exceed the maximum short-circuit current in
the system during a fault condition. In addition, consider
three other key parameters: 1) the required gate-source
(VGS) voltage drive, 2) the voltage drop across the drain-
to-source on resistance, RDS(ON) and 3) the maximum
junction temperature rating of the MOSFET.
Power MOSFETs are classified into three categories:
standard MOSFETs (RDS(ON) specified at VGS = 10V)
logic-level MOSFETs (RDS(ON) specified at VGS = 5V), and
sub-logic-level MOSFETs (RDS(ON) specified at VGS = 2.5V).
The absolute maximum rating for VGS is typically ±20V for
standard MOSFETs. However, the VGS maximum rating for
logic-level MOSFETs ranges from ±8V to ±20V depend-
ing upon the manufacturer and the specific part number.
The LTC4211’s GATE overdrive as a function of VCC is
illustrated in the Typical Performance curves. Logic-level
and sub-logic-level MOSFETs are recommended for low
supply voltage applications and standard MOSFETs can
be used for applications where supply voltage is greater
than 4.75V.
Note that in some applications, the gate of the external
MOSFET can discharge faster than the output voltage
when the circuit breaker is tripped. This causes a nega-
tive VGS voltage on the external MOSFET. Usually, the
selected external MOSFET should have a ±VGS(MAX) rat-
ing that is higher than the operating input supply voltage
to ensure that the external MOSFET is not destroyed by
a negative VGS voltage. In addition, the ±VGS(MAX) rating
of the MOSFET must be higher than the gate overdrive
voltage. Lower ±VGS(MAX) rating MOSFETs can be used
with the LTC4211 if the GATE overdrive is clamped to a
lower voltage. The circuit in Figure 12 illustrates the use
of Zener diodes to clamp the LTC4211’s GATE overdrive
signal if lower voltage MOSFETs are used.
Figure 12. Optional Gate Clamp for Lower VGS(MAX) MOSFETs
VCC VOUT
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
4211 F12
RSENSE
GATE
D2*
D1*
Q1
RG
200Ω
The RDS(ON) of the external pass transistor should be low
to make its drain-source voltage (VDS) a small percentage
of VCC. At a VCC = 2.5V, VDS + VRSENSE = 0.1V yields 4%
error at the output voltage. This restricts the choice of
MOSFETs to very low RDS(ON). At higher VCC voltages, the
VDS requirement can be relaxed in which case MOSFET
package dissipation (PD and TJ) may limit the value of
LTC4211
24
4211fb
OPERATION
RDS(ON). Table 5 lists some power MOSFETs that can be
used with the LTC4211.
For reliable circuit operation, the maximum junction
temperature (TJ(MAX)) for a power MOSFET should not
exceed the manufacturer’s recommended value. This
includes normal mode operation, start-up, current-limit
and autoretry mode in a fault condition. Under normal
conditions the junction temperature of a power MOSFET
is given by Equation 13:
MOSFET Junction Temperature,
T
J(MAX) ≤ TA(MAX) + θJA • PD (13)
where
P
D = (ILOAD)2 • RDS(ON)
θJA = junction-to-ambient thermal resistance
T
A(MAX) = maximum ambient temperature
If a short circuit happens during start-up, the external
MOSFET can experience a big single pulse energy. This
is especially true if the applications only employ a small
gate capacitor or no gate capacitor at all. Consult the safe
operating area (SOA) curve of the selected MOSFET to
ensure that the TJ(MAX) is not exceeded during start-up.
USING STAGGERED PIN CONNECTORS
The LTC4211 can be used on either a printed circuit board
or on the backplane side of the connector, and examples
for both are shown in Figures 13 and 14. Printed circuit
board edge connectors with staggered pins are recom-
mended as the insertion and removal of circuit boards do
sequence the pin connections. Supply voltage and ground
connections on the printed circuit board should be wired
to the edge connector’s long pins or blades. Control and
status signals (like RESET, FAULT and ON) passing through
the card’s edge connector should be wired to short length
pins or blades.
PCB CONNECTION SENSE
There are a number of ways to use the LTC4211’s ON pin
to detect whether the printed circuit board has been fully
seated in the backplane before the LTC4211 commences
a start-up cycle.
The first example is shown in the schematic on the front
page of this data sheet. In this case, the LTC4211 is
mounted on the PCB and a 20k/10k resistive divider is
connected to the ON pin. On the edge connector, R1 is
wired to a short pin. Until the connectors are fully mated,
the ON pin is held low, keeping the LTC4211 in an OFF
state. Once the connectors are mated, the resistive divider
is con
nected to VCC, VON > 1.316V and the LTC4211 begins
a start-up cycle.
In Figure 13, an LTC4211 is illustrated in a basic configura-
tion on a PCB daughter card. The ON pin is connected to
VCC on the backplane through a 10k pull-up resistor once
the card is seated into the backplane. R2 bleeds off any
potential static charge which might exist on the backplane,
the connector or during card installation.
A third example is shown in Figure 14 where the LTC4211
is mounted on the backplane. In this example, a 2N2222
transistor and a pair of resistors (R4, R5) form the PCB
connection sense circuit. With the card out of the chassis,
Q2’s base is biased to VCC through R5, biasing Q2 ON
and driving the LTC4211’s ON pin low. The base of Q2 is
also wired to a socket on the backplane connector. When
a card is firmly seated into the backplane, the base of Q2
is then grounded through a short pin connection on the
card. Q2 is biased OFF, the LTC4211’s ON pin is pulled-up
to VCC and a start-up cycle begins.
In the previous three examples, the connection sense was
hard wired with no processor (low) interrupt capability.
As illustrated in Figure 15, the addition of an inexpensive
logic-level discrete MOSFET and a couple of resistors offers
processor interrupt control to the connection sense. R4
keeps the gate of M2 at VCC until the card is firmly mated
to the backplane. A logic low for the ON/OFF signal turns
M2 OFF, allows the ON pin to pull high and turns on the
LTC4211.
LTC4211
25
4211fb
APPLICATIONS INFORMATION
A more elaborate connection sense scheme is shown in
Figure 16. The bases of Q1 and Q2 are wired to short pins
located on opposite ends of the edge connector because
the installation/removal of printed circuit cards gener-
ally requires rocking the card back and forth. When VCC
makes connection, the bases of transistors Q1 and Q2
are pulled high, biasing them ON. When either one of
them is ON, the LTC4211’s ON pin is held low, keeping
the LTC4211 OFF. When both the short base connector
+
VCC
RESET
SENSEON
R5
15k
LTC4211
GATE
FB
8
7
6
5
4211 F13
1
2
4
3CTIMER
10nF
GND
TIMER
R4
36k
VOUT
5V
5A
Q1
Si4410DY
RSENSE
0.007Ω
COUT
R6
10k
Z1*
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
R1
10Ω
C1
0.1μF
R2
10k
VIN
5V
SHORT
LONG
5V
VCC
RESET
LONG
PCB EDGE
CONNECTOR
(MALE)
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
+
VCC SENSE
ON
R2
100k
RESET
LTC4211
GATE
FB
78
6
1
5
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
4211 F14
2
4
3CTIMER
10nF
R3
10k
GND
TIMER
RESET
VOUT
5V
5A
Q1
Si4410DY
RSENSE
0.007Ω
COUT
R1
36k
R4
10k
R5
10k
PCB
CONNECTION
SENSE
RX
10Ω
CX
0.1μF
Z1*
VIN
5V
SHORT
LONG
SHORT
PCB EDGE
CONNECTOR
(MALE)
LONG
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
Q2
R7
15k
pins of Q1 and Q2 finally mate to the backplane, their
bases are grounded, biasing the transistors OFF. The
ON pin voltage is then pulled high by R3 enabling the
LTC4211 and a power-up cycle begins.
A software-initiated power-down cycle can be started by
momentarily driving transistor M1 with a logic high signal.
This in turn will drive the LTC4211’s ON pin low. If the ON
pin is held low for more than 8μs, the LTC4211’s GATE
pin is switched to ground.
Figure 13. Hot Swap Controller On Daughter Board (Staggered Pin Connections)
Figure 14. Hot Swap Controller on Backplane (Staggered Pin Connections)
LTC4211
26
4211fb
APPLICATIONS INFORMATION
+
VCC SENSE
LTC4211
8
2
34
76
CLOAD
VOUT
5V
5A
4211 F15
5
1
R6
15k
GATE
GNDTIMER
PCB CONNECTION SENSE
CTIMER
10nF
FB
ON
SHORT
LONG
VCC
5V
GND
ON/OFF
LONG
ZZ1 = 1SMA10A OR SMAJ10A
M2: 2N7002LT1
* OPTIONAL
RESET
R2
10k
R4
10k
M2
R1
10k
RX
10Ω
RSENSE
0.007Ω
PCB EDGE
CONNECTOR
(MALE) M1
Si4410DY
Z1*
R5
36k
R7
10k
μP
LOGIC
RESET
SHORT
CX
100nF
BACKPLANE
CONNECTOR
(FEMALE)
+
VCC SENSE
LTC4211
8
2
34
76
CLOAD
VOUT
5V
5A
4211 F16
5
1
R5
15k
GATE
GNDTIMER
PCB CONNECTION SENSE
CTIMER
10nF
FB
ON
LONG
VCC
GND
ON/RESET
LONG
RESET
M1
RX
10Ω
RSENSE
0.007Ω
PCB EDGE
CONNECTOR
(MALE)
M2
Si4410DY
Z1* R3
10k
R2
10k
R1
10k
R8
10k
R4
36k
R7
10k
μP
LOGIC
RESET
SHORT
SHORT
LAST BLADE OR PIN ON CONNECTOR
SHORT
CX
0.1μF
BACKPLANE
CONNECTOR
(FEMALE)
Q1
Q2
LAST BLADE OR PIN ON CONNECTOR
Z1 = 1SMA10A OR SMAJ10A
M1: 2N7002LT1
Q1, Q2: MMBT3904LT1
* OPTIONAL
Figure 15. Connection Sense with ON/OFF Control
Figure 16. Connection Sense for Rocking the Daughter Board Back and Forth
LTC4211
27
4211fb
APPLICATIONS INFORMATION
+
VCC SENSE
LTC4211
8
2
34
76
CLOAD
VOUT
12V
3A
GND
4211 F17
5
1
R4
12.4k
GATE
GNDTIMER
PCB CONNECTION SENSE CTIMER
8.2nF
FB
ON
SHORT
LONG
VCC
12V
GND LONG
Z1 = 1SMA12A OR SMAJ12A
** HIGHLY RECOMMENDED
RESET
R2
10k
R1
61.9k
RX
10Ω
RSENSE
0.012Ω
PCB EDGE
CONNECTOR
(MALE) M1
Si4410DY
Z1** RG
100Ω R3
93.1k
R5
10k
μP
LOGIC
RESET
CX
100nF
BACKPLANE
CONNECTOR
(FEMALE)
12V Hot Swap Application
Figure 17 shows a 12V, 3A Hot Swap application circuit.
The resistor divider R1/R2 programs the undervoltage
lockout externally and allows the system to start up after
VCC increases above 9.46V. The resistor divider R3/R4
monitors VOUT and signals the RESET pin when VOUT
goes above 10.54V. Transient voltage suppressor Z1 and
snubber network (CX, RX) are highly recommended to
protect the 12V applications system from ringing and
voltage spikes. RG is recommended for VCC > 10V and it
can minimize high frequency parasitic oscillations in the
power MOSFET.
AUTORETRY AFTER A FAULT
To configure the LTC4211 to automatically retry after a
fault condition, the FAULT and ON pins can be connected
to a pull-up resistor (RAUTO) to the supply, as shown in
Figure 17. 12V Hot Swap Application
Figure 18. In this case, the autoretry circuitry will attempt
to restart the LTC4211 with a 50% duty cycle, as shown
in the timing diagram of Figure 19. To prevent overheat-
ing the external MOSFET and other components during
the autoretry sequence, adding a capacitor (CAUTO) to the
circuit introduces an RC time constant (tOFF) that adjusts
the autoretry duty cycle. Equation 14 gives the autoretry
duty cycle, modified by this external time constant:
Autoretry Duty Cycle ≈tTIMER
tOFF +2•tTIMER
•100%
(14)
where tTIMER = LTC4211 system timing(see TIMER func-
tion) and tOFF is a time needed to charge capacitor CAUTO
from 0V to the ON pin threshold (1.316V).
In Figure 18 with RAUTO = 1M, the external RC time constant
is set at 1 second, the tTIMER delay equals 6.2ms and the
autoretry duty cycle drops from 50% to 2.5%.
Figure 18. LTC4211MS Autoretry Application
FAULT
VCC
LTC4211MS
SENSE
GATE
FB
1
2
3
4
5
10
RSENSE
0.007Ω
Q1
Si4410DY
9
8
7
6
RESET
ON
FILTER
TIMER
CTIMER
10nF
GND
CFILTER
100pF
RAUTO
(SEE NOTE)
RPULL-UP
10k
CAUTO
1μF
R3
10Ω Z1*
NOTE:
Q1 MOUNTED TO 300mm2 COPPER AREA
RAUTO = 1M YIELDS 2.5%
DUTY CYCLE AND Q1 TCASE = 50°C
RAUTO = 3.2M YIELDS 0.8%
DUTY CYCLE AND Q1 TCASE = 37°C
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
4211 F18
C1
0.1μF
R1
36k
VOUT
5V
5A
CLOAD
R2
15k
+
LONG
VCC
5V
GND
RESET
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
LTC4211
28
4211fb
APPLICATIONS INFORMATION
1
VCC
TIMER
GATE
RESET
VCC – VSENSE
FILTER
VOUT
235674 B8
SLOW COMPARATOR ARMED
FAST COMPARATOR ARMED
tOFF t1t2tFILTER tOFF
VREF
>50mV
GATE
VFB < VREF VOUT
FPD
tRESET
VSENSE = 50mV
REGULATED
LOAD CURRENT
10μA
4211 F19
2μA
ON/FAULTON/FAULT
DUTY CYCLE = (tFILTER << t1, t2 AND tOFF)
t2
tOFF + t1 + t2
To increase the RC delay, the user may either increase
CAUTO or RAUTO. However, increasing CAUTO > 2μF will
actually limit the RC delay due to the reset sink-current
capability of the FAULT pin. Therefore, in order to increase
the RC delay, it is more effective to either increase RAUTO
or to put a bleed resistor in parallel with CAUTO to GND.
For example, increasing RAUTO in Figure 18 from 1M to
3.2M decreases the duty cycle to 0.8%.
HOT SWAPPING TWO SUPPLIES
Using two external pass transistors, the LTC4211 can
switch two supply voltages. In some cases, it is necessary
to bring up the dominant supply first during power-up but
ramp them down together during the power-down phase.
The circuit in Figure 20 shows how to program two dif-
ferent delays for the pass transistors. The 5V supply is
powered up first. R1 and C3 are used to set the rise and
fall times on the 5V supply. Next, the 3.3V supply ramps
up with 20ms delay set by R6 and C2. On the falling edge,
both supplies ramp down together because D1 and D2
bypass R1 and R6.
OVERVOLTAGE TRANSIENT PROTECTION
Good engineering practice calls for bypassing the supply
rail of any analog circuit. Bypass capacitors are often placed
at the supply connection of every active device, in addition
to one or more large value bulk bypass capacitors per sup-
ply rail. If power is connected abruptly, the large bypass
capacitors slow the rate of rise of the supply voltage and
heavily damp any parasitic resonance of lead or PC track
inductance working against the supply bypass capacitors.
The opposite is true for LTC4211 Hot Swap circuits mounted
on plug-in cards. In most cases, there is no supply bypass
capacitor present on the powered supply voltage side of
the MOSFET switch. An abrupt connection, produced by
Figure 19. Autoretry Timing
LTC4211
29
4211fb
APPLICATIONS INFORMATION
1
2
3
4
8
7
6
5
VCC
SENSE
GATE
FB
RESET
ON
TIMER
GND
LTC4211
4211 F20
D1
1N4148
D2
1N4148
Q1
1/2 Si4936DY
Q2
1/2 Si4936DY
R2
0.015Ω
5%
R3
10Ω
5%
R8
10Ω
Z1* C4
0.1μF
C1
10nF
16V
R1
10k
5%
R6
1M
5%
R7
10Ω
5%
R4
2.74k
1%
TRIP POINT: 4.06V
R5
1.2k
1%
C3
0.047μF
25V
C2
0.022μF
25V
CLOAD
CLOAD
D3**
VOUT1
3.3V
2A
VOUT2
5V
2A
5V OUT
3.3V OUT
CURRENT LIMIT: 3.3A
+
+
R9
10Ω
R10
10k
10k
Z2* C5
0.1μF
R11
10k
LONG
3.3V
GND
RESET
LONG
**D3 IS OPTIONAL AND HELPS DISCHARGE VOUT1 IF VOUT2 SHORTS
PCB EDGE
CONNECTOR
(MALE)
LONG
BACKPLANE
CONNECTOR
(FEMALE)
5V
SHORT
SHORT
ON
Z1, Z2: 1SMA10A OR SMAJ10A
* OPTIONAL
+
VCC SENSE
LTC4211
8
34
76
COUT
VOUT
5V
5A
OUTPUT
GND
INPUT
GND
4211 F21
5
1
2
R2
15k
GATE
GND TIMER
CTIMER
FB
ON ON
RESET
RX
10Ω
VIN
5V
RSENSE
0.007Ω
Q1
Si4410DY
R1
36k
RESET
Z1*
CX
0.1μF
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
inserting the board into a backplane connector, results in a
fast rising edge applied on the supply line of the LTC4211.
Since there is no bulk capacitance to damp the para-
sitic track inductance, supply voltage transients excite
parasitic resonant circuits formed by the power MOSFET
capacitance and the combined parasitic inductance from
the wiring harness, the backplane and the circuit board
traces.
I
n these applications, there are two methods that should
be applied together for eliminating these supply voltage
transients: using transient voltage suppressor to clip the
transient to a safe level and snubber networks. Snubber
networks are series RC networks whose time constants are
experimentally determined based on the board’s parasitic
resonance circuits. As a starting point, the capacitors in
these networks are chosen to be 10× to 100× the power
MOSFET’s COSS under bias. The series resistor is a value
determined experimentally and ranges from 1Ω to 50Ω,
depending on the parasitic resonance circuit. For applica-
tions with supply voltages of 12V or higher the ringing
and overshoot during hot-swapping or when the output is
short-circuited can easily exceed the absolute maximum
specification of the LTC4211. To reduce the danger, tran-
sient voltage suppressors and snubber networks are highly
recommended. For applications with lower supply voltages
such as 5V, usually a snubber is adequate to reduce the
supply ringing, although a transient voltage suppressor
may be required for inductive and high current applications.
Note that in all LTC4211 5V applications schematics, tran-
sient suppressor and snubber networks have been added
for protection. The transient suppressor is optional and a
simple short-circuit test can be performed to determine
if it is necessary. These protection networks should be
mounted very close to the LTC4211’s supply input rail
using short lead lengths to minimize lead inductance.
This is shown in Figure 21, and a recommended layout
of the transient protection devices around the LTC4211
is shown in Figure 22.
Figure 20. Switching 5V and 3.3V
Figure 21. Placing Transient Protection Devices
Close to the LTC4211’s Input Rail
LTC4211
30
4211fb
APPLICATIONS INFORMATION
RESET
ON
TIMER
GND
VCC
SENSE
LTC4211**
1
4211 F22
GATE
FB
D
D
D
D
G
S
S
S
W
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
CURRENT FLOW
FROM LOAD
SENSE RESISTOR
(RSENSE)
POWER MOSFET
(SO-8)
W
W
VIA TO
GND PLANE
NOTES:
DRAWING IS NOT TO SCALE!
*OPTIONAL COMPONENTS
**ADDITIONAL DETAILS OMITTED
FOR CLARITY
R4
15k
CTIMER
10nF
R3
36k
CGX*
RGX*
RX
CX
SNUBBER
NETWORK
Z1*
TRANSIENT
VOLTAGE
SUPPRESSOR
Figure 22. Recommended Layout for LTC4211 Protection Devices, RSENSE, Power MOSFET and Feedback Network
LTC4211
31
4211fb
APPLICATIONS INFORMATION
1
2
3
4
5
10
9
8
7
6
FAULT
VCC
SENSE
GATE
FB
RESET
ON
FILTER
TIMER
GND
LTC4211
Z1 = 1SMA10A OR SMAJ10A
Z2 = 1N4691
* OPTIONAL
Q1
Si4410DY
R1
36k
VOUT
5V
5A
R2
15k
CLOAD
4211 F23
RSENSE
0.007Ω
+
CTIMER
10nF
CFILTER
47pF
Z2
6.2V
LONG
5V
GND
FAULT
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
SHORT
SHORT
RESET
ON/OFF
R3
10Ω
Z1* C1
0.1μF
R5
10k
R6
10k
R7
10k
R4
10k
SUPPLY OVERVOLTAGE DETECTION/
PROTECTION USING FILTER PIN
In addition to using external protection devices around the
LTC4211 for large scale transient protection, low power
Zener diodes can be used with the LTC4211’s FILTER
pin to act as a supply overvoltage detection/protection
circuit on either the high side (input) or low side (output)
of the external pass transistor. Recall that internal control
circuitry keeps the LTC4211 GATE voltage from ramping
up if VFILTER > 1.156V, or when an external fault condition
(VFILTER > 1.236V) causes FAULT to be asserted low.
High Side (Input) Overvoltage Protection
As shown in Figure 23, a low power Zener diode can
be used to sense an overvoltage condition on the input
(high) side of the main 5V supply. In this example, a low
bias current 1N4691 Zener diode is chosen to protect the
system. Here, the Zener diode is connected from VCC to
the LTC4211’s FILTER pin (Pin 3 MS). If the input volt-
age to the system is greater than 6.8V during start-up,
the voltage on the FILTER pin is pulled higher than its
1.156V threshold. As a result, the GATE pin is not allowed
to ramp and the second timing cycle will not commence
until the supply overvoltage condition is removed. Should
the supply overvoltage condition occur during normal
operation, internal control logic would trip the electronic
circuit breaker and the GATE would be pulled to ground,
shutting OFF the external pass transistor. If a lower supply
overvoltage threshold is desired, use a Zener diode with
a smaller breakdown voltage.
A timing diagram for illustrating LTC4211 operation under a
high side overvoltage condition is shown in Figure 24. The
start-up sequence in this case (between Time Points 1 and
2) is identical to any other start-up sequence under normal
operating conditions. At Time Point 2A, the input supply
voltage causes the Zener diode to conduct thereby forcing
VFILTER > 1.156V. At Time Point 3, FAULT is asserted low
and the TIMER pin voltage ramps down. At Time Point 4,
the LTC4211 checks if VFILTER < 1.156V. FAULT is asserted
low (but not latched) to indicate a start-up failure. The
start-up sequence only resumes with the second timing
cycle at Time Point 5 when the input overvoltage condition
is removed. At this point in time, the GATE pin voltage is
allowed to ramp up, FAULT is pulled to logic high and the
circuit breaker is armed. At any time after Time Point 5,
should a supply overvoltage condition develop (VFILTER >
1.236V), the electronic circuit breaker will trip, the GATE
will be pulled low to turn off the external MOSFET and
FAULT will be asserted low and latched. This sequence is
shown in detail at Time Point B.
Figure 23. LTC4211MS High Side Overvoltage Protection Implementation
LTC4211
32
4211fb
APPLICATIONS INFORMATION
1
VCC ON
TIMER
GATE
RESET
FILTER
>VREF – 80mV
FAULT
VOUT
GATE
VOUT
23 5672A 4 8 A B C
SLOW COMPARATOR ARMED
IF OVERVOLTAGE GOES
AWAY, SECOND CYCLE
CONTINUES
OVERVOLTAGE
IF ANY FAULT HAPPENS
AFTER THIS POINT, THE
CIRCUIT BREAKER TRIPS
AND FAULT LATCHES LOW
OVERVOLTAGE CIRCUIT BREAKER
TRIPS, GATE PULLS DOWN AND
FAULT LATCHES LOW
FAULT IS PULLED LOW (BUT NOT LATCHED)
DUE TO A START-UP OVERVOLTAGE PROBLEM
POWER GOOD
VFB > VREF
POWER BAD
VFB < VREF
FPD
4211 F24
>VREF
FAULT
LATCHED LOW
Low Side (Output) Overvoltage Protection
A Zener diode can be used in a similar fashion to detect/
protect the system against a supply overvoltage condition
on the load (or low) side of the pass transistor. In this
case, the Zener diode is connected from the load to the
LTC4211’s FILTER pin, as shown in Figure 25. An additional
diode, D1, prevents the FILTER pin from pulling low during
an output short-circuit. Figure 26 illustrates the timing
diagram for a low side output overvoltage condition. In
this example, VCC starts up in an overvoltage condition
but the LTC4211 can only sense the overvoltage supply
condition at Time Point 6 when the GATE pin has ramped
up. At Time Point 6, VFILTER is greater than 1.236V, the
circuit breaker is tripped, the GATE pin voltage is pulled
to ground and FAULT is asserted low and latched.
Figure 24. High Side Overvoltage Protection
LTC4211
33
4211fb
APPLICATIONS INFORMATION
1
2
3
4
5
10
9
8
7
6
FAULT
VCC
SENSE
GATE
FB
RESET
ON
FILTER
TIMER
GND
LTC4211
Q1
Si4410DY
R1
36k
VOUT
5V
5A
R2
15k
CLOAD
4211 F25
RSENSE
0.007Ω
+
CTIMER
10nF
CFILTER
47pF
Z2
6.2V
LONG
5V
GND
FAULT
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
SHORT
SHORT
RESET
ON/OFF
R4
10Ω
Z1* C1
0.1μF
R5
10k
R7
10k
R6
10k
R3
10k
Z1 = 1SMA10A OR SMAJ10A
Z2 = 1N4691
* OPTIONAL
D1
IN4148
12 34 5
OVERVOLTAGE SENSED BY FILTER PIN AND CIRCUIT BREAKER TRIPS
VCC
TIMER
GATE
VOUT
RESET
FILTER
ON
6
FAULT
FPD
4211 F26
VREF
Figure 25. LTC4211MS Low Side Overvoltage Protection Implementation
Figure 26. Low Side Overvoltage Protection
LTC4211
34
4211fb
APPLICATIONS INFORMATION
In either case, the LTC4211 can be configured to au-
tomatically initiate a start-up sequence. Please refer
to the section on AutoRetry After a Fault for additional
information.
PCB Layout Considerations
For proper operation of the LTC4211’s circuit breaker
function, a 4-wire Kelvin connection to the sense resis-
tors is highly recommended. A recommended PCB layout
for the sense resistor, the power MOSFET and the GATE
drive components around the LTC4211 is illustrated in
Figure22. In Hot Swap applications where load currents
can reach 10A or more, narrow PCB tracks exhibit more
resistance than wider tracks and operate at more elevated
temperatures. Since the sheet resistance of 1 ounce cop-
per foil is approximately 0.54mΩ/square, track resistances
add up quickly in high current applications. Thus, to keep
PCB track resistance and temperature rise to a minimum,
PCB track width must be appropriately sized. Consult Ap-
pendix A of LTC Application Note 69 for details on sizing
and calculating trace resistances as a function of copper
thickness.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal
to the PC board. For 1 ounce copper foil plating, a good
starting point is 1A of DC current per via, making sure the
via is properly dimensioned so that solder completely fills
any void. For other plating thicknesses, check with your
PCB fabrication facility.
LTC4211
35
4211fb
APPENDIX
Table 4 lists some current sense resistors that can be used
with the circuit breaker. Table 5 lists some power MOSFETs
that are available. Table 6 lists the web sites of several
manufacturers. Since this information is subject to change,
please verify the part numbers with the manufacturer.
Table 4. Sense Resistor Selection Guide
CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER
1A LR120601R050 0.05Ω 0.5W 1% Resistor IRC-TT
2A LR120601R025 0.025Ω 0.5W 1% Resistor IRC-TT
2.5A LR120601R020 0.02Ω 0.5W 1% Resistor IRC-TT
3.3A WSL2512R015F 0.015Ω 1W 1% Resistor Vishay-Dale
5A LR251201R010F 0.01Ω 1.5W 1% Resistor IRC-TT
10A WSR2R005F 0.005Ω 2W 1% Resistor Vishay-Dale
Table 5. N-Channel Selection Guide
CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER
0 to 2 MMDF3N02HD Dual N-Channel SO-8
RDS(ON) = 0.1Ω, CISS = 455pF
ON Semiconductor
2 to 5 MMSF5N02HD Single N-Channel SO-8
RDS(ON) = 0.025Ω, CISS = 1130pF
ON Semiconductor
5 to 10 MTB50N06V Single N-Channel DD Pak
RDS(ON) = 0.028Ω, CISS = 1570pF
ON Semiconductor
10 to 20 MTB75N05HD Single N-Channel DD Pak
RDS(ON) = 0.0095Ω, CISS = 2600pF
ON Semiconductor
Table 6. Manufacturers’ Web Sites
MANUFACTURER WEB SITE
TEMIC Semiconductor www.temic.com
International Rectifier www.irf.com
ON Semiconductor www.onsemi.com
Harris Semiconductor www.semi.harris.com
IRC-TT www.irctt.com
Vishay-Dale www.vishay.com
Vishay-Siliconix www.vishay.com
Diodes, Inc. www.diodes.com
LTC4211
36
4211fb
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSOP (MS8) 0307 REV F
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 p 0.0508
(.004 p .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 p 0.152
(.193 p .006)
8765
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
LTC4211
37
4211fb
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSOP (MS) 0307 REV E
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
LTC4211
38
4211fb
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)w 45s
0s– 8s TYP
.008 – .010
(0.203 – 0.254)
SO8 REV G 0212
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 t.005
RECOMMENDED SOLDER PAD LAYOUT
.045 t.005
.050 BSC
.030 t.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
LTC4211
39
4211fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
B 03/12 Updated Pin description information
Updated Figure 2 and supporting text
Moved Figure 7 and supporting text to page 16 and renumbered to Figure 6
Updated text under Second Timing (Soft-Start) Cycle
Replaced CGX with CGATE in Figure 6
Revised Figure 26 and supporting Low Side (Output) Overvoltage Protection text
10, 11
13
16
16
16
32, 33
(Revision history begins at Rev B)
LTC4211
40
4211fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0312 REV B • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
LOW COST OVERVOLTAGE PROTECTION
There is an alternative method to implementing the over-
voltage protection using a resistor divider at the FILTER
pin (see Figures 27 and 28). In this implementation, the
SLOW COMP is NULL in Normal Mode. Only the FAST
COMP circuit breaker is available and the current limit
level is 150mV/RSENSE. During the soft-cycle, the inrush
current servo loop is at 50mV/RSENSE. So, the heavy load
should only turn on at/after the end of second cycle where
the RESET pin goes high.
Figure 27. LTC4211MS High Side Overvoltage Protection Implementation
(In Normal Mode, SLOW COMP Is Disabled. In Soft-Start Cycle, ISOFTSTART Is Still 50mV/RSENSE)
Figure 28. LTC4211MS Low Side Overvoltage Protection Implementation
(In Normal Mode, SLOW COMP Is Disabled. In Soft-Start Cycle, ISOFTSTART Is Still 50mV/RSENSE)
1
2
3
4
5
10
9
8
7
6
FAULT
VCC
SENSE
GATE
FB
RESET
ON
FILTER
TIMER
GND
LTC4211
Q1
Si4410DY
R1
3.6k
VOUT
5V
5A
R2
750Ω
CLOAD
4211 F28
RSENSE
0.007Ω
+
R8
750Ω
CTIMER
10nF
LONG
5V
GND
FAULT
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
SHORT
SHORT
RESET
ON/OFF
R7
10Ω
Z1* C1
0.1μF
R4
10k
R6
10k
R5
10k
R3
10k
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
PART NUMBER DESCRIPTION COMMENTS
LTC1421 Two Channels, Hot Swap Controller 24-Pin, Operates from 3V to 12V and Supports –12V
LTC1422 Single Channel, Hot Swap Controller 8-Pin, Operates from 2.7V to 12V
LT1640AL/LT1640AH Negative Voltage Hot Swap Controller 8-Pin, Operates from –10V to –80V
LT1641-1/LT1641-2 Positive Voltage Hot Swap Controller 8-Pin, Operates from 9V to 80V, Latch-Off/Auto Retry
LTC1642 Single Channel, Hot Swap Controller 16-Pin, Overvoltage Protection to 33V
LTC1644 PCI Hot Swap Controller 16-Pin, 3.3V, 5V and ±12V, 1V Precharge, PCI Reset Logic
LTC1647 Dual Channel, Hot Swap Controller 8-Pin, 16-Pin, Operates from 2.7V to 16.5V
LTC4230 Triple Hot Swap Controller with Multifunction Current Control Operates from 1.7V to 16.5V
1
2
3
4
5
10
9
8
7
6
FAULT
VCC
SENSE
GATE
FB
RESET
ON
FILTER
TIMER
GND
LTC4211
Q1
Si4410DY
R1
36k
VOUT
5V
5A
R2
15k
CLOAD
4211 F27
RSENSE
0.007Ω
+
CTIMER
10nF
LONG
5V
GND
FAULT
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
SHORT
SHORT
RESET
ON/OFF
R3
10Ω
Z1* C1
0.1μF
R5
10k
R6
10k
R8
4.3k
R7
10k
R9
750Ω
R4
10k
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL