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   
SCES487B − SEPTEMBER 2003 − REVISED FEBRUAR Y 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAvailable in the Texas Instruments
NanoStarand NanoFreePackages
DSupports 5-V VCC Operation
DInputs Accept Voltages to 5.5 V
DMax tpd of 4.1 ns at 3.3 V
DLow Power Consumption, 10-µA Max ICC
D±24-mA Output Drive at 3.3 V
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74LVC1G11 performs the Boolean function Y+A•B•CorY+A)B)C in positive logic.
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel
SN74LVC1G11YEPR
_ _ _C3_
−40°C to 85°CNanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel SN74LVC1G11YZPR _ _ _C3_
SOT (SOT-23) − DBV Tape and reel SN74LVC1G11DBVR C11_
SOT (SC-70) − DCK Tape and reel SN74LVC1G11DCKR C3_
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, •= Pb-free).
Copyright 2004, Texas Instruments Incorporated
NanoStar and NanoFree are trademarks of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
6
5
4
A
GND
B
C
VCC
Y
3
2
1
4
5
6
B
GND
A
Y
VCC
C
YEP OR YZP PACKAGE
(BOTTOM VIEW)
    !   "#$ %!&
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SCES487B − SEPTEMBER 2003 − REVISED FEBRUAR Y 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUT
A B C
OUTPUT
Y
H H H H
LXX L
XLX L
X X L L
logic diagram (positive logic)
A
CY
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DBV package 165°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 259°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package 123°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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SCES487B − SEPTEMBER 2003 − REVISED FEBRUAR Y 2004
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recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC
Supply voltage
Operating 1.65 5.5
V
VCC Supply voltage Data retention only 1.5 V
VCC = 1.65 V to 1.95 V 0.65 ×VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V 1.7
V
VIH High-level input voltage VCC = 3 V to 3.6 V 2V
VCC = 4.5 V to 5.5 V 0.7 ×VCC
VCC = 1.65 V to 1.95 V 0.35 ×VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V 0.7
V
VIL Low-level input voltage VCC = 3 V to 3.6 V 0.8 V
VCC = 4.5 V to 5.5 V 0.3 ×VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V −4
VCC = 2.3 V −8
I
OH
High-level output current
VCC = 3 V
−16 mA
IOH
High-level output current
VCC = 3 V −24
mA
VCC = 4.5 V −32
VCC = 1.65 V 4
VCC = 2.3 V 8
I
OL
Low-level output current
VCC = 3 V
16 mA
IOL
Low-level output current
VCC = 3 V 24
mA
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
∆t/∆vInput transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
∆t/∆v
Input transition rise or fall rate
VCC = 5 V ±0.5 V 10
ns/V
TAOperating free-air temperature −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES487B − SEPTEMBER 2003 − REVISED FEBRUAR Y 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP†MAX UNIT
IOH = −100 mA1.65 V to 5.5 V VCC−0.1
IOH = −4 mA 1.65 V 1.2
V
IOH = −8 mA 2.3 V 1.9
VOH IOH = −16 mA
3 V
2.4 V
IOH = −24 mA 3 V 2.3
IOH = −32 mA 4.5 V 3.8
IOL = 100 mA1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
V
IOL = 8 mA 2.3 V 0.3
VOL IOL = 16 mA
3 V
0.4 V
IOL = 24 mA 3 V 0.55
IOL = 32 mA 4.5 V 0.55
IIAll inputs VI = 5.5 V or GND 0 to 5.5 V ±5mA
Ioff VI or VO = 5.5 V 0±10 mA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 mA
∆ICC One input at VCC − 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 mA
CiVI = VCC or GND 3.3 V 3.5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A, B, or C Y2.6 15.2 1.6 5.6 1.2 4.1 1 3.1 ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF or
50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A, B, or C Y2.9 17.2 1.4 6.2 1.3 4.9 1 3.5 ns
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER
TEST CONDITIONS
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 18 19 20 23 pF
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   
SCES487B − SEPTEMBER 2003 − REVISED FEBRUAR Y 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V∆
VOH − V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 MΩ
1 MΩ
1 MΩ
1 MΩ
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms

   
SCES487B − SEPTEMBER 2003 − REVISED FEBRUAR Y 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V∆
VOH − V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 2. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCK (R-PDSO-G6) PLASTIC SMALL-OUTLINE PACKAGE
0,15
Gage Plane
0,10
M
0,10
0,65
0°–8°0,46
0,26
0,13 NOM
4093553-3/D 01/02
0,15
0,30
1,40
1,10 2,40
1,80
46
2,15
1,85
1 3
1,10
0,80 0,10
0,00
Seating Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
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